#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
+#include <linux/io.h>
#include <mach/hardware.h>
-#include <asm/io.h>
#include <asm/mach/map.h>
#include <mach/tc.h>
#include <mach/board.h>
#include <mach/mux.h>
#include <mach/gpio.h>
+#include <mach/mmc.h>
/*-------------------------------------------------------------------------*/
};
static struct platform_device mbox_device = {
- .name = "mailbox",
+ .name = "omap1-mailbox",
.id = -1,
.num_resources = ARRAY_SIZE(mbox_resources),
.resource = mbox_resources,
static inline void omap_init_mbox(void) { }
#endif
+/*-------------------------------------------------------------------------*/
+
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+
+static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
+ int controller_nr)
+{
+ if (controller_nr == 0) {
+ omap_cfg_reg(MMC_CMD);
+ omap_cfg_reg(MMC_CLK);
+ omap_cfg_reg(MMC_DAT0);
+ if (cpu_is_omap1710()) {
+ omap_cfg_reg(M15_1710_MMC_CLKI);
+ omap_cfg_reg(P19_1710_MMC_CMDDIR);
+ omap_cfg_reg(P20_1710_MMC_DATDIR0);
+ }
+ if (mmc_controller->slots[0].wires == 4) {
+ omap_cfg_reg(MMC_DAT1);
+ /* NOTE: DAT2 can be on W10 (here) or M15 */
+ if (!mmc_controller->slots[0].nomux)
+ omap_cfg_reg(MMC_DAT2);
+ omap_cfg_reg(MMC_DAT3);
+ }
+ }
+
+ /* Block 2 is on newer chips, and has many pinout options */
+ if (cpu_is_omap16xx() && controller_nr == 1) {
+ if (!mmc_controller->slots[1].nomux) {
+ omap_cfg_reg(Y8_1610_MMC2_CMD);
+ omap_cfg_reg(Y10_1610_MMC2_CLK);
+ omap_cfg_reg(R18_1610_MMC2_CLKIN);
+ omap_cfg_reg(W8_1610_MMC2_DAT0);
+ if (mmc_controller->slots[1].wires == 4) {
+ omap_cfg_reg(V8_1610_MMC2_DAT1);
+ omap_cfg_reg(W15_1610_MMC2_DAT2);
+ omap_cfg_reg(R10_1610_MMC2_DAT3);
+ }
+
+ /* These are needed for the level shifter */
+ omap_cfg_reg(V9_1610_MMC2_CMDDIR);
+ omap_cfg_reg(V5_1610_MMC2_DATDIR0);
+ omap_cfg_reg(W19_1610_MMC2_DATDIR1);
+ }
+
+ /* Feedback clock must be set on OMAP-1710 MMC2 */
+ if (cpu_is_omap1710())
+ omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
+ MOD_CONF_CTRL_1);
+ }
+}
+
+void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ int nr_controllers)
+{
+ int i;
+
+ for (i = 0; i < nr_controllers; i++) {
+ unsigned long base, size;
+ unsigned int irq = 0;
+
+ if (!mmc_data[i])
+ continue;
+
+ omap1_mmc_mux(mmc_data[i], i);
+
+ switch (i) {
+ case 0:
+ base = OMAP1_MMC1_BASE;
+ irq = INT_MMC;
+ break;
+ case 1:
+ if (!cpu_is_omap16xx())
+ return;
+ base = OMAP1_MMC2_BASE;
+ irq = INT_1610_MMC2;
+ break;
+ default:
+ continue;
+ }
+ size = OMAP1_MMC_SIZE;
+
+ omap_mmc_add(i, base, size, irq, mmc_data[i]);
+ };
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
#if defined(CONFIG_OMAP_STI)
-#define OMAP1_STI_BASE IO_ADDRESS(0xfffea000)
+#define OMAP1_STI_BASE 0xfffea000
#define OMAP1_STI_CHANNEL_BASE (OMAP1_STI_BASE + 0x400)
static struct resource sti_resources[] = {
/*
* Mailbox reservation modules for DSP
*
- * Copyright (C) 2006 Nokia Corporation
+ * Copyright (C) 2006-2008 Nokia Corporation
* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
*
* This file is subject to the terms and conditions of the GNU General Public
#include <linux/resource.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
+#include <linux/io.h>
#include <mach/mailbox.h>
#include <mach/irqs.h>
-#include <asm/io.h>
+ #define DRV_NAME "omap1-mailbox"
+
#define MAILBOX_ARM2DSP1 0x00
#define MAILBOX_ARM2DSP1b 0x04
#define MAILBOX_DSP2ARM1 0x08
#define MAILBOX_DSP2ARM1_Flag 0x1c
#define MAILBOX_DSP2ARM2_Flag 0x20
- unsigned long mbox_base;
+ static void __iomem *mbox_base;
struct omap_mbox1_fifo {
unsigned long cmd;
struct omap_mbox1_fifo rx_fifo;
};
- static inline int mbox_read_reg(unsigned int reg)
+ static inline int mbox_read_reg(size_t ofs)
{
- return __raw_readw(mbox_base + reg);
+ return __raw_readw(mbox_base + ofs);
}
- static inline void mbox_write_reg(unsigned int val, unsigned int reg)
+ static inline void mbox_write_reg(u32 val, size_t ofs)
{
- __raw_writew(val, mbox_base + reg);
+ __raw_writew(val, mbox_base + ofs);
}
/* msg */
};
EXPORT_SYMBOL(mbox_dsp_info);
- static int __init omap1_mbox_probe(struct platform_device *pdev)
+ static int __devinit omap1_mbox_probe(struct platform_device *pdev)
{
struct resource *res;
int ret = 0;
}
mbox_dsp_info.irq = res->start;
- ret = omap_mbox_register(&mbox_dsp_info);
-
- return ret;
+ return omap_mbox_register(&pdev->dev, &mbox_dsp_info);
}
- static int omap1_mbox_remove(struct platform_device *pdev)
+ static int __devexit omap1_mbox_remove(struct platform_device *pdev)
{
omap_mbox_unregister(&mbox_dsp_info);
static struct platform_driver omap1_mbox_driver = {
.probe = omap1_mbox_probe,
- .remove = omap1_mbox_remove,
+ .remove = __devexit_p(omap1_mbox_remove),
.driver = {
- .name = "mailbox",
+ .name = DRV_NAME,
},
};
module_init(omap1_mbox_init);
module_exit(omap1_mbox_exit);
- MODULE_LICENSE("GPL");
+ MODULE_LICENSE("GPL v2");
+ MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions");
+ MODULE_AUTHOR("Hiroshi DOYU" <Hiroshi.DOYU@nokia.com>);
+ MODULE_ALIAS("platform:"DRV_NAME);
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/clk.h>
#include <mach/hardware.h>
-#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
+#include <mach/control.h>
#include <mach/tc.h>
#include <mach/board.h>
#include <mach/mux.h>
#include <mach/gpio.h>
+#include <mach/eac.h>
+#include <mach/mmc.h>
-#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
+#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
-#define OMAP2_I2C_BASE2 0x48072000
-#define OMAP2_I2C_INT2 57
-
-static struct resource i2c_resources2[] = {
+static struct resource cam_resources[] = {
{
- .start = OMAP2_I2C_BASE2,
- .end = OMAP2_I2C_BASE2 + 0x3f,
+ .start = OMAP24XX_CAMERA_BASE,
+ .end = OMAP24XX_CAMERA_BASE + 0xfff,
.flags = IORESOURCE_MEM,
},
{
- .start = OMAP2_I2C_INT2,
+ .start = INT_24XX_CAM_IRQ,
.flags = IORESOURCE_IRQ,
- },
+ }
};
-static struct platform_device omap_i2c_device2 = {
- .name = "i2c_omap",
- .id = 2,
- .num_resources = ARRAY_SIZE(i2c_resources2),
- .resource = i2c_resources2,
+static struct platform_device omap_cam_device = {
+ .name = "omap24xxcam",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(cam_resources),
+ .resource = cam_resources,
};
-/* See also arch/arm/plat-omap/devices.c for first I2C on 24xx */
-static void omap_init_i2c(void)
+static inline void omap_init_camera(void)
{
- /* REVISIT: Second I2C not in use on H4? */
- if (machine_is_omap_h4())
- return;
-
- if (!cpu_is_omap2430()) {
- omap_cfg_reg(J15_24XX_I2C2_SCL);
- omap_cfg_reg(H19_24XX_I2C2_SDA);
- }
- (void) platform_device_register(&omap_i2c_device2);
+ platform_device_register(&omap_cam_device);
}
-#else
+#elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
+
+static struct resource cam_resources[] = {
+ {
+ .start = OMAP34XX_CAMERA_BASE,
+ .end = OMAP34XX_CAMERA_BASE + 0x1B70,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_34XX_CAM_IRQ,
+ .flags = IORESOURCE_IRQ,
+ }
+};
-static void omap_init_i2c(void) {}
+static struct platform_device omap_cam_device = {
+ .name = "omap34xxcam",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(cam_resources),
+ .resource = cam_resources,
+};
+static inline void omap_init_camera(void)
+{
+ platform_device_register(&omap_cam_device);
+}
+#else
+static inline void omap_init_camera(void)
+{
+}
#endif
- #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
- #define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE)
+ #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
- static struct resource mbox_resources[] = {
+ #define MBOX_REG_SIZE 0x120
+
+ static struct resource omap2_mbox_resources[] = {
{
- .start = OMAP2_MBOX_BASE,
- .end = OMAP2_MBOX_BASE + 0x11f,
+ .start = OMAP24XX_MAILBOX_BASE,
+ .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
},
};
+ static struct resource omap3_mbox_resources[] = {
+ {
+ .start = OMAP34XX_MAILBOX_BASE,
+ .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_34XX_MAIL_U0_MPU,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
static struct platform_device mbox_device = {
- .name = "mailbox",
+ .name = "omap2-mailbox",
.id = -1,
- .num_resources = ARRAY_SIZE(mbox_resources),
- .resource = mbox_resources,
};
static inline void omap_init_mbox(void)
{
+ if (cpu_is_omap2420()) {
+ mbox_device.num_resources = ARRAY_SIZE(omap2_mbox_resources);
+ mbox_device.resource = omap2_mbox_resources;
+ } else if (cpu_is_omap3430()) {
+ mbox_device.num_resources = ARRAY_SIZE(omap3_mbox_resources);
+ mbox_device.resource = omap3_mbox_resources;
+ } else {
+ return;
+ }
platform_device_register(&mbox_device);
}
#else
static inline void omap_init_mbox(void) { }
- #endif
+ #endif /* CONFIG_OMAP_MBOX_FWK */
#if defined(CONFIG_OMAP_STI)
-#define OMAP2_STI_BASE IO_ADDRESS(0x48068000)
+#if defined(CONFIG_ARCH_OMAP2)
+
+#define OMAP2_STI_BASE 0x48068000
#define OMAP2_STI_CHANNEL_BASE 0x54000000
#define OMAP2_STI_IRQ 4
.flags = IORESOURCE_IRQ,
}
};
+#elif defined(CONFIG_ARCH_OMAP3)
+
+#define OMAP3_SDTI_BASE 0x54500000
+#define OMAP3_SDTI_CHANNEL_BASE 0x54600000
+
+static struct resource sti_resources[] = {
+ {
+ .start = OMAP3_SDTI_BASE,
+ .end = OMAP3_SDTI_BASE + 0xFFF,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = OMAP3_SDTI_CHANNEL_BASE,
+ .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+#endif
static struct platform_device sti_device = {
.name = "sti",
static inline void omap_init_sti(void) {}
#endif
-#if defined(CONFIG_SPI_OMAP24XX)
+#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
#include <mach/mcspi.h>
#define OMAP2_MCSPI1_BASE 0x48098000
#define OMAP2_MCSPI2_BASE 0x4809a000
+#define OMAP2_MCSPI3_BASE 0x480b8000
+#define OMAP2_MCSPI4_BASE 0x480ba000
static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
.num_cs = 4,
},
};
-struct platform_device omap2_mcspi1 = {
+static struct platform_device omap2_mcspi1 = {
.name = "omap2_mcspi",
.id = 1,
.num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
},
};
-struct platform_device omap2_mcspi2 = {
+static struct platform_device omap2_mcspi2 = {
.name = "omap2_mcspi",
.id = 2,
.num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
},
};
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
+static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
+ .num_cs = 2,
+};
+
+static struct resource omap2_mcspi3_resources[] = {
+ {
+ .start = OMAP2_MCSPI3_BASE,
+ .end = OMAP2_MCSPI3_BASE + 0xff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device omap2_mcspi3 = {
+ .name = "omap2_mcspi",
+ .id = 3,
+ .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
+ .resource = omap2_mcspi3_resources,
+ .dev = {
+ .platform_data = &omap2_mcspi3_config,
+ },
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
+ .num_cs = 1,
+};
+
+static struct resource omap2_mcspi4_resources[] = {
+ {
+ .start = OMAP2_MCSPI4_BASE,
+ .end = OMAP2_MCSPI4_BASE + 0xff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device omap2_mcspi4 = {
+ .name = "omap2_mcspi",
+ .id = 4,
+ .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
+ .resource = omap2_mcspi4_resources,
+ .dev = {
+ .platform_data = &omap2_mcspi4_config,
+ },
+};
+#endif
+
static void omap_init_mcspi(void)
{
platform_device_register(&omap2_mcspi1);
platform_device_register(&omap2_mcspi2);
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
+ if (cpu_is_omap2430() || cpu_is_omap343x())
+ platform_device_register(&omap2_mcspi3);
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+ if (cpu_is_omap343x())
+ platform_device_register(&omap2_mcspi4);
+#endif
}
#else
static inline void omap_init_mcspi(void) {}
#endif
+#ifdef CONFIG_SND_OMAP24XX_EAC
+
+#define OMAP2_EAC_BASE (L4_24XX_BASE + 0x90000)
+
+static struct resource omap2_eac_resources[] = {
+ {
+ .start = OMAP2_EAC_BASE,
+ .end = OMAP2_EAC_BASE + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device omap2_eac_device = {
+ .name = "omap24xx-eac",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(omap2_eac_resources),
+ .resource = omap2_eac_resources,
+ .dev = {
+ .platform_data = NULL,
+ },
+};
+
+void omap_init_eac(struct eac_platform_data *pdata)
+{
+ omap2_eac_device.dev.platform_data = pdata;
+ platform_device_register(&omap2_eac_device);
+}
+
+#else
+void omap_init_eac(struct eac_platform_data *pdata) {}
+#endif
+
+#ifdef CONFIG_OMAP_SHA1_MD5
+static struct resource sha1_md5_resources[] = {
+ {
+ .start = OMAP24XX_SEC_SHA1MD5_BASE,
+ .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_24XX_SHA1MD5,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct platform_device sha1_md5_device = {
+ .name = "OMAP SHA1/MD5",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(sha1_md5_resources),
+ .resource = sha1_md5_resources,
+};
+
+static void omap_init_sha1_md5(void)
+{
+ platform_device_register(&sha1_md5_device);
+}
+#else
+static inline void omap_init_sha1_md5(void) { }
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef CONFIG_ARCH_OMAP3
+
+#define MMCHS_SYSCONFIG 0x0010
+#define MMCHS_SYSCONFIG_SWRESET (1 << 1)
+#define MMCHS_SYSSTATUS 0x0014
+#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
+
+static struct platform_device dummy_pdev = {
+ .dev = {
+ .bus = &platform_bus_type,
+ },
+};
+
+/**
+ * omap_hsmmc_reset() - Full reset of each HS-MMC controller
+ *
+ * Ensure that each MMC controller is fully reset. Controllers
+ * left in an unknown state (by bootloader) may prevent retention
+ * or OFF-mode. This is especially important in cases where the
+ * MMC driver is not enabled, _or_ built as a module.
+ *
+ * In order for reset to work, interface, functional and debounce
+ * clocks must be enabled. The debounce clock comes from func_32k_clk
+ * and is not under SW control, so we only enable i- and f-clocks.
+ **/
+static void __init omap_hsmmc_reset(void)
+{
+ u32 i, nr_controllers = cpu_is_omap34xx() ? OMAP34XX_NR_MMC :
+ OMAP24XX_NR_MMC;
+
+ for (i = 0; i < nr_controllers; i++) {
+ u32 v, base = 0;
+ struct clk *iclk, *fclk;
+ struct device *dev = &dummy_pdev.dev;
+
+ switch (i) {
+ case 0:
+ base = OMAP2_MMC1_BASE;
+ break;
+ case 1:
+ base = OMAP2_MMC2_BASE;
+ break;
+ case 2:
+ base = OMAP3_MMC3_BASE;
+ break;
+ }
+
+ dummy_pdev.id = i;
+ iclk = clk_get(dev, "mmchs_ick");
+ if (iclk && clk_enable(iclk))
+ iclk = NULL;
+
+ fclk = clk_get(dev, "mmchs_fck");
+ if (fclk && clk_enable(fclk))
+ fclk = NULL;
+
+ if (!iclk || !fclk) {
+ printk(KERN_WARNING
+ "%s: Unable to enable clocks for MMC%d, "
+ "cannot reset.\n", __func__, i);
+ break;
+ }
+
+ omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
+ v = omap_readl(base + MMCHS_SYSSTATUS);
+ while (!(omap_readl(base + MMCHS_SYSSTATUS) &
+ MMCHS_SYSSTATUS_RESETDONE))
+ cpu_relax();
+
+ if (fclk) {
+ clk_disable(fclk);
+ clk_put(fclk);
+ }
+ if (iclk) {
+ clk_disable(iclk);
+ clk_put(iclk);
+ }
+ }
+}
+#else
+static inline void omap_hsmmc_reset(void) {}
+#endif
+
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
+ defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+
+static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
+ int controller_nr)
+{
+ if (cpu_is_omap2420() && controller_nr == 0) {
+ omap_cfg_reg(H18_24XX_MMC_CMD);
+ omap_cfg_reg(H15_24XX_MMC_CLKI);
+ omap_cfg_reg(G19_24XX_MMC_CLKO);
+ omap_cfg_reg(F20_24XX_MMC_DAT0);
+ omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
+ omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
+ if (mmc_controller->slots[0].wires == 4) {
+ omap_cfg_reg(H14_24XX_MMC_DAT1);
+ omap_cfg_reg(E19_24XX_MMC_DAT2);
+ omap_cfg_reg(D19_24XX_MMC_DAT3);
+ omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
+ omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
+ omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
+ }
+
+ /*
+ * Use internal loop-back in MMC/SDIO Module Input Clock
+ * selection
+ */
+ if (mmc_controller->slots[0].internal_clock) {
+ u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+ v |= (1 << 24);
+ omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
+ }
+ }
+}
+
+void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ int nr_controllers)
+{
+ int i;
+
+ for (i = 0; i < nr_controllers; i++) {
+ unsigned long base, size;
+ unsigned int irq = 0;
+
+ if (!mmc_data[i])
+ continue;
+
+ omap2_mmc_mux(mmc_data[i], i);
+
+ switch (i) {
+ case 0:
+ base = OMAP2_MMC1_BASE;
+ irq = INT_24XX_MMC_IRQ;
+ break;
+ case 1:
+ base = OMAP2_MMC2_BASE;
+ irq = INT_24XX_MMC2_IRQ;
+ break;
+ case 2:
+ if (!cpu_is_omap34xx())
+ return;
+ base = OMAP3_MMC3_BASE;
+ irq = INT_34XX_MMC3_IRQ;
+ break;
+ default:
+ continue;
+ }
+
+ if (cpu_is_omap2420())
+ size = OMAP2420_MMC_SIZE;
+ else
+ size = HSMMC_SIZE;
+
+ omap_mmc_add(i, base, size, irq, mmc_data[i]);
+ };
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
+#define OMAP_HDQ_BASE 0x480B2000
+#endif
+static struct resource omap_hdq_resources[] = {
+ {
+ .start = OMAP_HDQ_BASE,
+ .end = OMAP_HDQ_BASE + 0x1C,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_24XX_HDQ_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+static struct platform_device omap_hdq_dev = {
+ .name = "omap_hdq",
+ .id = 0,
+ .dev = {
+ .platform_data = NULL,
+ },
+ .num_resources = ARRAY_SIZE(omap_hdq_resources),
+ .resource = omap_hdq_resources,
+};
+static inline void omap_hdq_init(void)
+{
+ (void) platform_device_register(&omap_hdq_dev);
+}
+#else
+static inline void omap_hdq_init(void) {}
+#endif
+
/*-------------------------------------------------------------------------*/
static int __init omap2_init_devices(void)
/* please keep these calls, and their implementations above,
* in alphabetical order so they're easier to sort through.
*/
- omap_init_i2c();
+ omap_hsmmc_reset();
+ omap_init_camera();
omap_init_mbox();
omap_init_mcspi();
+ omap_hdq_init();
omap_init_sti();
+ omap_init_sha1_md5();
return 0;
}
/*
- * Mailbox reservation modules for OMAP2
+ * Mailbox reservation modules for OMAP2/3
*
- * Copyright (C) 2006 Nokia Corporation
+ * Copyright (C) 2006-2008 Nokia Corporation
* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- * and Paul Mundt <paul.mundt@nokia.com>
+ * and Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
+#include <linux/io.h>
#include <mach/mailbox.h>
#include <mach/irqs.h>
-#include <asm/io.h>
- #define MAILBOX_REVISION 0x00
- #define MAILBOX_SYSCONFIG 0x10
- #define MAILBOX_SYSSTATUS 0x14
- #define MAILBOX_MESSAGE_0 0x40
- #define MAILBOX_MESSAGE_1 0x44
- #define MAILBOX_MESSAGE_2 0x48
- #define MAILBOX_MESSAGE_3 0x4c
- #define MAILBOX_MESSAGE_4 0x50
- #define MAILBOX_MESSAGE_5 0x54
- #define MAILBOX_FIFOSTATUS_0 0x80
- #define MAILBOX_FIFOSTATUS_1 0x84
- #define MAILBOX_FIFOSTATUS_2 0x88
- #define MAILBOX_FIFOSTATUS_3 0x8c
- #define MAILBOX_FIFOSTATUS_4 0x90
- #define MAILBOX_FIFOSTATUS_5 0x94
- #define MAILBOX_MSGSTATUS_0 0xc0
- #define MAILBOX_MSGSTATUS_1 0xc4
- #define MAILBOX_MSGSTATUS_2 0xc8
- #define MAILBOX_MSGSTATUS_3 0xcc
- #define MAILBOX_MSGSTATUS_4 0xd0
- #define MAILBOX_MSGSTATUS_5 0xd4
- #define MAILBOX_IRQSTATUS_0 0x100
- #define MAILBOX_IRQENABLE_0 0x104
- #define MAILBOX_IRQSTATUS_1 0x108
- #define MAILBOX_IRQENABLE_1 0x10c
- #define MAILBOX_IRQSTATUS_2 0x110
- #define MAILBOX_IRQENABLE_2 0x114
- #define MAILBOX_IRQSTATUS_3 0x118
- #define MAILBOX_IRQENABLE_3 0x11c
-
- static unsigned long mbox_base;
-
- #define MAILBOX_IRQ_NOTFULL(n) (1 << (2 * (n) + 1))
- #define MAILBOX_IRQ_NEWMSG(n) (1 << (2 * (n)))
+ #define DRV_NAME "omap2-mailbox"
+
+ #define MAILBOX_REVISION 0x000
+ #define MAILBOX_SYSCONFIG 0x010
+ #define MAILBOX_SYSSTATUS 0x014
+ #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
+ #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
+ #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
+ #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
+ #define MAILBOX_IRQENABLE(u) (0x108 + 8 * (u))
+
+ #define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u)))
+ #define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1))
+
+ #define MBOX_REG_SIZE 0x120
+
+ static void __iomem *mbox_base;
struct omap_mbox2_fifo {
unsigned long msg;
unsigned long irqstatus;
u32 newmsg_bit;
u32 notfull_bit;
+ char ctx[MBOX_REG_SIZE];
};
static struct clk *mbox_ick_handle;
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq);
- static inline unsigned int mbox_read_reg(unsigned int reg)
+ static inline unsigned int mbox_read_reg(size_t ofs)
{
- return __raw_readl(mbox_base + reg);
+ return __raw_readl(mbox_base + ofs);
}
- static inline void mbox_write_reg(unsigned int val, unsigned int reg)
+ static inline void mbox_write_reg(u32 val, size_t ofs)
{
- __raw_writel(val, mbox_base + reg);
+ __raw_writel(val, mbox_base + ofs);
}
/* Mailbox H/W preparations */
}
clk_enable(mbox_ick_handle);
+ l = mbox_read_reg(MAILBOX_REVISION);
+ pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
+
/* set smart-idle & autoidle */
l = mbox_read_reg(MAILBOX_SYSCONFIG);
l |= 0x00000011;
return (enable & status & bit);
}
+ static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
+ {
+ int i;
+ struct omap_mbox2_priv *p = mbox->priv;
+
+ for (i = 0; i < MBOX_REG_SIZE; i += sizeof(u32)) {
+ u32 val;
+
+ val = mbox_read_reg(i);
+ *(u32 *)(p->ctx + i) = val;
+
+ dev_dbg(mbox->dev, "%s\t[%02d] %08x\n", __func__, i, val);
+ }
+ }
+
+ static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
+ {
+ int i;
+ struct omap_mbox2_priv *p = mbox->priv;
+
+ for (i = 0; i < MBOX_REG_SIZE; i += sizeof(u32)) {
+ u32 val;
+
+ val = *(u32 *)(p->ctx + i);
+ mbox_write_reg(val, i);
+
+ dev_dbg(mbox->dev, "%s\t[%02d] %08x\n", __func__, i, val);
+ }
+ }
+
static struct omap_mbox_ops omap2_mbox_ops = {
.type = OMAP_MBOX_TYPE2,
.startup = omap2_mbox_startup,
.disable_irq = omap2_mbox_disable_irq,
.ack_irq = omap2_mbox_ack_irq,
.is_irq = omap2_mbox_is_irq,
+ .save_ctx = omap2_mbox_save_ctx,
+ .restore_ctx = omap2_mbox_restore_ctx,
};
/*
/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
.tx_fifo = {
- .msg = MAILBOX_MESSAGE_0,
- .fifo_stat = MAILBOX_FIFOSTATUS_0,
+ .msg = MAILBOX_MESSAGE(0),
+ .fifo_stat = MAILBOX_FIFOSTATUS(0),
},
.rx_fifo = {
- .msg = MAILBOX_MESSAGE_1,
- .msg_stat = MAILBOX_MSGSTATUS_1,
+ .msg = MAILBOX_MESSAGE(1),
+ .msg_stat = MAILBOX_MSGSTATUS(1),
},
- .irqenable = MAILBOX_IRQENABLE_0,
- .irqstatus = MAILBOX_IRQSTATUS_0,
+ .irqenable = MAILBOX_IRQENABLE(0),
+ .irqstatus = MAILBOX_IRQSTATUS(0),
.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
};
};
EXPORT_SYMBOL(mbox_dsp_info);
- /* IVA */
+ #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
static struct omap_mbox2_priv omap2_mbox_iva_priv = {
.tx_fifo = {
- .msg = MAILBOX_MESSAGE_2,
- .fifo_stat = MAILBOX_FIFOSTATUS_2,
+ .msg = MAILBOX_MESSAGE(2),
+ .fifo_stat = MAILBOX_FIFOSTATUS(2),
},
.rx_fifo = {
- .msg = MAILBOX_MESSAGE_3,
- .msg_stat = MAILBOX_MSGSTATUS_3,
+ .msg = MAILBOX_MESSAGE(3),
+ .msg_stat = MAILBOX_MSGSTATUS(3),
},
- .irqenable = MAILBOX_IRQENABLE_3,
- .irqstatus = MAILBOX_IRQSTATUS_3,
+ .irqenable = MAILBOX_IRQENABLE(3),
+ .irqstatus = MAILBOX_IRQSTATUS(3),
.notfull_bit = MAILBOX_IRQ_NOTFULL(2),
.newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
};
.ops = &omap2_mbox_ops,
.priv = &omap2_mbox_iva_priv,
};
+ #endif
- static int __init omap2_mbox_probe(struct platform_device *pdev)
+ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
{
struct resource *res;
- int ret = 0;
-
- if (pdev->num_resources != 3) {
- dev_err(&pdev->dev, "invalid number of resources: %d\n",
- pdev->num_resources);
- return -ENODEV;
- }
+ int ret;
/* MBOX base */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
dev_err(&pdev->dev, "invalid mem resource\n");
return -ENODEV;
}
- mbox_base = res->start;
+ mbox_base = ioremap(res->start, res->end - res->start);
+ if (!mbox_base)
+ return -ENOMEM;
- /* DSP IRQ */
+ /* DSP or IVA2 IRQ */
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (unlikely(!res)) {
dev_err(&pdev->dev, "invalid irq resource\n");
- return -ENODEV;
+ ret = -ENODEV;
+ goto err_dsp;
}
mbox_dsp_info.irq = res->start;
- ret = omap_mbox_register(&mbox_dsp_info);
-
- /* IVA IRQ */
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
- if (unlikely(!res)) {
- dev_err(&pdev->dev, "invalid irq resource\n");
- return -ENODEV;
+ ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
+ if (ret)
+ goto err_dsp;
+
+ #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
+ if (cpu_is_omap2420()) {
+ /* IVA IRQ */
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+ if (unlikely(!res)) {
+ dev_err(&pdev->dev, "invalid irq resource\n");
+ ret = -ENODEV;
+ goto err_iva1;
+ }
+ mbox_iva_info.irq = res->start;
+ ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
+ if (ret)
+ goto err_iva1;
}
- mbox_iva_info.irq = res->start;
-
- ret = omap_mbox_register(&mbox_iva_info);
+ #endif
+ return 0;
+ err_iva1:
+ omap_mbox_unregister(&mbox_dsp_info);
+ err_dsp:
+ iounmap(mbox_base);
return ret;
}
- static int omap2_mbox_remove(struct platform_device *pdev)
+ static int __devexit omap2_mbox_remove(struct platform_device *pdev)
{
+ #if defined(CONFIG_ARCH_OMAP2420)
+ omap_mbox_unregister(&mbox_iva_info);
+ #endif
omap_mbox_unregister(&mbox_dsp_info);
+ iounmap(mbox_base);
return 0;
}
static struct platform_driver omap2_mbox_driver = {
.probe = omap2_mbox_probe,
- .remove = omap2_mbox_remove,
+ .remove = __devexit_p(omap2_mbox_remove),
.driver = {
- .name = "mailbox",
+ .name = DRV_NAME,
},
};
module_init(omap2_mbox_init);
module_exit(omap2_mbox_exit);
- MODULE_LICENSE("GPL");
+ MODULE_LICENSE("GPL v2");
+ MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions");
+ MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");
+ MODULE_ALIAS("platform:"DRV_NAME);
config ARCH_OMAP2
bool "TI OMAP2"
+config ARCH_OMAP3
+ bool "TI OMAP3"
+
endchoice
comment "OMAP Feature Selections"
depends on OMAP_DEBUG_DEVICES
default y if LEDS || LEDS_OMAP_DEBUG
+config OMAP_DEBUG_POWERDOMAIN
+ bool "Emit debug messages from powerdomain layer"
+ depends on ARCH_OMAP2 || ARCH_OMAP3
+ default n
+ help
+ Say Y here if you want to compile in powerdomain layer
+ debugging messages for OMAP2/3. These messages can
+ provide more detail as to why some powerdomain calls
+ may be failing, and will also emit a descriptive message
+ for every powerdomain register write. However, the
+ extra detail costs some memory.
+
+config OMAP_DEBUG_CLOCKDOMAIN
+ bool "Emit debug messages from clockdomain layer"
+ depends on ARCH_OMAP2 || ARCH_OMAP3
+ default n
+ help
+ Say Y here if you want to compile in clockdomain layer
+ debugging messages for OMAP2/3. These messages can
+ provide more detail as to why some clockdomain calls
+ may be failing, and will also emit a descriptive message
+ for every clockdomain register write. However, the
+ extra detail costs some memory.
+
+config OMAP_SMARTREFLEX
+ bool "SmartReflex support"
+ depends on ARCH_OMAP34XX && TWL4030_CORE
+ help
+ Say Y if you want to enable SmartReflex.
+
+ SmartReflex can perform continuous dynamic voltage
+ scaling around the nominal operating point voltage
+ according to silicon characteristics and operating
+ conditions. Enabling SmartReflex reduces power
+ consumption.
+
+ Please note, that by default SmartReflex is only
+ initialized. To enable the automatic voltage
+ compensation for VDD1 and VDD2, user must write 1 to
+ /sys/power/sr_vddX_autocomp, where X is 1 or 2.
+
+config OMAP_SMARTREFLEX_TESTING
+ bool "Smartreflex testing support"
+ depends on OMAP_SMARTREFLEX
+ default n
+ help
+ Say Y if you want to enable SmartReflex testing with SW hardcoded
+ NVALUES intead of E-fuse NVALUES set in factory silicon testing.
+
+ In some devices the E-fuse values have not been set, even though
+ SmartReflex modules are included. Using these hardcoded values set
+ in software, one can test the SmartReflex features without E-fuse.
+
+ WARNING: Enabling this option may cause your device to hang!
+
config OMAP_RESET_CLOCKS
bool "Reset unused clocks during boot"
depends on ARCH_OMAP
probably do not want this option enabled until your
device drivers work properly.
+config OMAP_BOOT_TAG
+ bool "OMAP bootloader information passing"
+ depends on ARCH_OMAP
+ default n
+ help
+ Say Y, if you have a bootloader which passes information
+ about your board and its peripheral configuration.
+
+config OMAP_BOOT_REASON
+ bool "Support for boot reason"
+ depends on OMAP_BOOT_TAG
+ default n
+ help
+ Say Y, if you want to have a procfs entry for reading the boot
+ reason in user-space.
+
+config OMAP_COMPONENT_VERSION
+ bool "Support for component version display"
+ depends on OMAP_BOOT_TAG && PROC_FS
+ default n
+ help
+ Say Y, if you want to have a procfs entry for reading component
+ versions (supplied by the bootloader) in user-space.
+
+config OMAP_GPIO_SWITCH
+ bool "GPIO switch support"
+ default n
+ help
+ Say Y, if you want to have support for reporting of GPIO
+ switches (e.g. cover switches) via sysfs. Your bootloader has
+ to provide information about the switches to the kernel via the
+ ATAG_BOARD mechanism if they're not defined by the board config.
+
config OMAP_MUX
bool "OMAP multiplexing support"
depends on ARCH_OMAP
Say Y here if you want support for the OMAP Multichannel
Buffered Serial Port.
+config OMAP_MMU_FWK
+ bool "MMU framework support"
+ depends on ARCH_OMAP
+ default n
+ help
+ Say Y here if you want to use OMAP MMU framework support for
+ DSP, IVA1.0 and Camera in OMAP1/2.
+
config OMAP_MBOX_FWK
tristate "Mailbox framework support"
depends on ARCH_OMAP
default n
help
Say Y here if you want to use OMAP Mailbox framework support for
- DSP and IVA1.0 in OMAP1/2.
+ DSP, IVA1.0 and IVA2 in OMAP1/2/3.
choice
prompt "System timer"
config OMAP_32K_TIMER
bool "Use 32KHz timer"
- depends on ARCH_OMAP16XX || ARCH_OMAP24XX
+ depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
help
Select this option if you want to enable the OMAP 32KHz timer.
This timer saves power compared to the OMAP_MPU_TIMER, and has
support for no tick during idle. The 32KHz timer provides less
intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
- currently only available for OMAP16XX and 24XX.
+ currently only available for OMAP16XX, 24XX and 34XX.
endchoice
config OMAP_DM_TIMER
bool "Use dual-mode timer"
- depends on ARCH_OMAP16XX || ARCH_OMAP24XX
+ depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
help
Select this option if you want to use OMAP Dual-Mode timers.
#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
+#define OMAP34XX_SR1_BASE 0x480C9000
+#define OMAP34XX_SR2_BASE 0x480CB000
#if defined(CONFIG_ARCH_OMAP3430)
#define OMAP2_CM_BASE OMAP3430_CM_BASE
#define OMAP2_PRM_BASE OMAP3430_PRM_BASE
#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)
+#define OMAP34XX_CAMERA_BASE (L4_34XX_BASE + 0xBC000)
+ #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
#endif
projects / linux-2.6-omap-h63xx.git / commitdiff