+ /* clear CORE wake-up events */
+ prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+ prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+
+ /* wakeup domain events */
+ l = prm_read_mod_reg(WKUP_MOD, PM_WKST);
+ l &= 0x5; /* bit 1: GPT1, bit5 GPIO */
+ prm_write_mod_reg(l, WKUP_MOD, PM_WKST);
+
+ /* MPU domain wake events */
+ l = prm_read_reg(OMAP24XX_PRCM_IRQSTATUS_MPU);
+ if (l & 0x01)
+ prm_write_reg(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU);
+ if (l & 0x20)
+ prm_write_reg(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU);
+
+ /* Mask future PRCM-to-MPU interrupts */
+ prm_write_reg(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU);