2 * linux/arch/arm/mach-omap2/pm.c
4 * OMAP2 Power Management Routines
6 * Copyright (C) 2005 Texas Instruments, Inc.
7 * Copyright (C) 2006 Nokia Corporation
10 * Richard Woodruff <r-woodruff2@ti.com>
13 * Amit Kucheria <amit.kucheria@nokia.com>
14 * Igor Stoppa <igor.stoppa@nokia.com>
16 * Based on pm.c for omap1
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
23 #include <linux/suspend.h>
24 #include <linux/sched.h>
25 #include <linux/proc_fs.h>
26 #include <linux/interrupt.h>
27 #include <linux/sysfs.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
34 #include <asm/atomic.h>
35 #include <asm/mach/time.h>
36 #include <asm/mach/irq.h>
37 #include <asm/mach-types.h>
39 #include <asm/arch/irqs.h>
40 #include <asm/arch/clock.h>
41 #include <asm/arch/sram.h>
42 #include <asm/arch/gpio.h>
43 #include <asm/arch/pm.h>
44 #include <asm/arch/mux.h>
45 #include <asm/arch/dma.h>
46 #include <asm/arch/board.h>
47 #include <asm/arch/gpio.h>
50 #include "prm_regbits_24xx.h"
52 #include "cm_regbits_24xx.h"
55 /* These addrs are in assembly language code to be patched at runtime */
56 extern void *omap2_ocs_sdrc_power;
57 extern void *omap2_ocs_sdrc_dlla_ctrl;
59 static void (*omap2_sram_idle)(void);
60 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
61 static void (*saved_idle)(void);
63 static u32 omap2_read_32k_sync_counter(void)
65 return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
68 #ifdef CONFIG_PM_DEBUG
69 int omap2_pm_debug = 0;
71 static int serial_console_clock_disabled;
72 static int serial_console_uart;
73 static unsigned int serial_console_next_disable;
75 static struct clk *console_iclk, *console_fclk;
77 static void serial_console_kick(void)
79 serial_console_next_disable = omap2_read_32k_sync_counter();
80 /* Keep the clocks on for 4 secs */
81 serial_console_next_disable += 4 * 32768;
84 static void serial_wait_tx(void)
86 static const unsigned long uart_bases[3] = {
87 0x4806a000, 0x4806c000, 0x4806e000
89 unsigned long lsr_reg;
92 /* Wait for TX FIFO and THR to get empty */
93 lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
94 while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
97 serial_console_kick();
100 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
102 switch (serial_console_uart) {
115 static void serial_console_sleep(int enable)
117 if (console_iclk == NULL || console_fclk == NULL)
121 BUG_ON(serial_console_clock_disabled);
122 if (clk_get_usecount(console_fclk) == 0)
124 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
127 clk_disable(console_iclk);
128 clk_disable(console_fclk);
129 serial_console_clock_disabled = 1;
131 int serial_wakeup = 0;
134 switch (serial_console_uart) {
136 l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
137 if (l & OMAP24XX_ST_UART1)
141 l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
142 if (l & OMAP24XX_ST_UART2)
146 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
147 if (l & OMAP24XX_ST_UART3)
152 serial_console_kick();
153 if (!serial_console_clock_disabled)
155 clk_enable(console_iclk);
156 clk_enable(console_fclk);
157 serial_console_clock_disabled = 0;
161 static void pm_init_serial_console(void)
163 const struct omap_serial_console_config *conf;
167 conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
168 struct omap_serial_console_config);
171 if (conf->console_uart > 3 || conf->console_uart < 1)
173 serial_console_uart = conf->console_uart;
174 sprintf(name, "uart%d_fck", conf->console_uart);
175 console_fclk = clk_get(NULL, name);
176 if (IS_ERR(console_fclk))
179 console_iclk = clk_get(NULL, name);
180 if (IS_ERR(console_fclk))
182 if (console_fclk == NULL || console_iclk == NULL) {
183 serial_console_uart = 0;
186 switch (serial_console_uart) {
188 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
189 l |= OMAP24XX_ST_UART1;
190 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
193 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
194 l |= OMAP24XX_ST_UART2;
195 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
198 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKEN2);
199 l |= OMAP24XX_ST_UART3;
200 prm_write_mod_reg(l, CORE_MOD, OMAP24XX_PM_WKEN2);
205 #define DUMP_PRM_MOD_REG(mod, reg) \
206 regs[reg_count].name = #mod "." #reg; \
207 regs[reg_count++].val = prm_read_mod_reg(mod, reg)
208 #define DUMP_CM_MOD_REG(mod, reg) \
209 regs[reg_count].name = #mod "." #reg; \
210 regs[reg_count++].val = cm_read_mod_reg(mod, reg)
211 #define DUMP_PRM_REG(reg) \
212 regs[reg_count].name = #reg; \
213 regs[reg_count++].val = prm_read_reg(reg)
214 #define DUMP_CM_REG(reg) \
215 regs[reg_count].name = #reg; \
216 regs[reg_count++].val = cm_read_reg(reg)
217 #define DUMP_INTC_REG(reg, off) \
218 regs[reg_count].name = #reg; \
219 regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
221 static void omap2_pm_dump(int mode, int resume, unsigned int us)
227 int reg_count = 0, i;
228 const char *s1 = NULL, *s2 = NULL;
233 DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU);
234 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
235 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
236 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
237 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
241 DUMP_INTC_REG(INTC_MIR0, 0x0084);
242 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
243 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
246 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
247 DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
248 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
249 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
250 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
251 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
252 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
253 DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL);
254 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
255 DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);
256 DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL);
260 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
261 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
262 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
263 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
264 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
265 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
266 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
267 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
268 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
269 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
272 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
273 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
274 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
275 DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU);
277 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
278 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
279 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
299 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
300 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
301 jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
304 printk("--- Going to %s %s\n", s1, s2);
307 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
308 for (i = 0; i < reg_count; i++)
309 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
313 static inline void serial_console_sleep(int enable) {}
314 static inline void pm_init_serial_console(void) {}
315 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
316 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
318 #define omap2_pm_debug 0
322 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
324 static ssize_t omap_pm_sleep_while_idle_show(struct kset * subsys, char *buf)
326 return sprintf(buf, "%hu\n", enable_dyn_sleep);
329 static ssize_t omap_pm_sleep_while_idle_store(struct kset * subsys,
333 unsigned short value;
334 if (sscanf(buf, "%hu", &value) != 1 ||
335 (value != 0 && value != 1)) {
336 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
339 enable_dyn_sleep = value;
343 static struct subsys_attribute sleep_while_idle_attr = {
345 .name = __stringify(sleep_while_idle),
348 .show = omap_pm_sleep_while_idle_show,
349 .store = omap_pm_sleep_while_idle_store,
352 static struct clk *osc_ck, *emul_ck;
354 #define CONTROL_DEVCONF __REG32(OMAP2_CTRL_BASE + 0x274)
356 static int omap2_fclks_active(void)
360 f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
361 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
362 serial_console_fclk_mask(&f1, &f2);
368 static int omap2_irq_pending(void)
370 u32 pending_reg = IO_ADDRESS(0x480fe098);
373 for (i = 0; i < 4; i++) {
374 if (__raw_readl(pending_reg))
381 static atomic_t sleep_block = ATOMIC_INIT(0);
383 void omap2_block_sleep(void)
385 atomic_inc(&sleep_block);
388 void omap2_allow_sleep(void)
392 i = atomic_dec_return(&sleep_block);
396 static void omap2_enter_full_retention(void)
400 /* There is 1 reference hold for all children of the oscillator
401 * clock, the following will remove it. If no one else uses the
402 * oscillator itself it will be disabled if/when we enter retention
407 /* Clear old wake-up events */
408 /* REVISIT: These write to reserved bits? */
409 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
410 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
411 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
413 /* Try to enter retention */
414 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
415 MPU_MOD, PM_PWSTCTRL);
417 /* Workaround to kill USB */
418 CONTROL_DEVCONF |= 0x00008000;
420 omap2_gpio_prepare_for_retention();
422 if (omap2_pm_debug) {
423 omap2_pm_dump(0, 0, 0);
424 sleep_time = omap2_read_32k_sync_counter();
427 /* One last check for pending IRQs to avoid extra latency due
428 * to sleeping unnecessarily. */
429 if (omap2_irq_pending())
432 serial_console_sleep(1);
433 /* Jump to SRAM suspend code */
434 omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
436 serial_console_sleep(0);
438 if (omap2_pm_debug) {
439 unsigned long long tmp;
442 resume_time = omap2_read_32k_sync_counter();
443 tmp = resume_time - sleep_time;
445 omap2_pm_dump(0, 1, tmp / 32768);
447 omap2_gpio_resume_after_retention();
453 static int omap2_i2c_active(void)
457 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
458 return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
461 static int sti_console_enabled;
463 static int omap2_allow_mpu_retention(void)
467 if (atomic_read(&sleep_block))
470 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
471 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
472 if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
473 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
474 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
476 /* Check for UART3. */
477 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
478 if (l & OMAP24XX_EN_UART3)
480 if (sti_console_enabled)
486 static void omap2_enter_mpu_retention(void)
491 /* Putting MPU into the WFI state while a transfer is active
492 * seems to cause the I2C block to timeout. Why? Good question. */
493 if (omap2_i2c_active())
496 /* The peripherals seem not to be able to wake up the MPU when
497 * it is in retention mode. */
498 if (omap2_allow_mpu_retention()) {
499 /* REVISIT: These write to reserved bits? */
500 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
501 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
502 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
504 /* Try to enter MPU retention */
505 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
507 MPU_MOD, PM_PWSTCTRL);
509 /* Block MPU retention */
511 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
515 if (omap2_pm_debug) {
516 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
517 sleep_time = omap2_read_32k_sync_counter();
522 if (omap2_pm_debug) {
523 unsigned long long tmp;
526 resume_time = omap2_read_32k_sync_counter();
527 tmp = resume_time - sleep_time;
529 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
533 static int omap2_can_sleep(void)
535 if (!enable_dyn_sleep)
537 if (omap2_fclks_active())
539 if (atomic_read(&sleep_block) > 0)
541 if (clk_get_usecount(osc_ck) > 1)
543 if (omap_dma_running())
549 static void omap2_pm_idle(void)
554 if (!omap2_can_sleep()) {
555 /* timer_dyn_reprogram() takes about 100-200 us to complete.
556 * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
557 * transfer to complete), the increased latency is too much.
559 * omap2_block_sleep() and omap2_allow_sleep() can be used
562 if (atomic_read(&sleep_block) == 0) {
563 timer_dyn_reprogram();
564 if (omap2_irq_pending())
567 omap2_enter_mpu_retention();
572 * Since an interrupt may set up a timer, we don't want to
573 * reprogram the hardware timer with interrupts enabled.
574 * Re-enable interrupts only after returning from idle.
576 timer_dyn_reprogram();
578 if (omap2_irq_pending())
581 omap2_enter_full_retention();
588 static int omap2_pm_prepare(void)
590 /* We cannot sleep in idle until we have resumed */
591 saved_idle = pm_idle;
597 static int omap2_pm_suspend(void)
601 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
602 prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
605 mir1 = omap_readl(0x480fe0a4);
606 omap_writel(1 << 5, 0x480fe0ac);
608 omap2_enter_full_retention();
610 omap_writel(mir1, 0x480fe0a4);
611 prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
616 static int omap2_pm_enter(suspend_state_t state)
621 case PM_SUSPEND_STANDBY:
623 ret = omap2_pm_suspend();
632 static void omap2_pm_finish(void)
634 pm_idle = saved_idle;
637 static struct platform_suspend_ops omap_pm_ops = {
638 .prepare = omap2_pm_prepare,
639 .enter = omap2_pm_enter,
640 .finish = omap2_pm_finish,
641 .valid = suspend_valid_only_mem,
644 static void __init prcm_setup_regs(void)
648 /* Enable autoidle */
649 prm_write_reg(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
651 /* Set all domain wakeup dependencies */
652 prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP);
653 prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
654 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
656 l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
657 /* Enable retention for all memory blocks */
658 l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
659 OMAP24XX_MEM1RETSTATE;
661 /* Set power state to RETENTION */
662 l &= ~OMAP_POWERSTATE_MASK;
663 l |= 0x01 << OMAP_POWERSTATE_SHIFT;
664 prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
666 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
668 MPU_MOD, PM_PWSTCTRL);
670 /* Power down DSP and GFX */
671 prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
672 OMAP24XX_DSP_MOD, PM_PWSTCTRL);
673 prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
674 GFX_MOD, PM_PWSTCTRL);
676 /* Enable clock auto control for all domains */
677 cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL);
678 cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 |
679 OMAP24XX_AUTOSTATE_L3,
680 CORE_MOD, CM_CLKSTCTRL);
681 cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL);
682 cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP,
683 OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
685 /* Enable clock autoidle for all domains */
686 cm_write_mod_reg(OMAP24XX_AUTO_CAM |
687 OMAP24XX_AUTO_MAILBOXES |
690 OMAP24XX_AUTO_MSPRO |
695 OMAP24XX_AUTO_UART2 |
696 OMAP24XX_AUTO_UART1 |
699 OMAP24XX_AUTO_MCSPI2 |
700 OMAP24XX_AUTO_MCSPI1 |
701 OMAP24XX_AUTO_MCBSP2 |
702 OMAP24XX_AUTO_MCBSP1 |
703 OMAP24XX_AUTO_GPT12 |
704 OMAP24XX_AUTO_GPT11 |
705 OMAP24XX_AUTO_GPT10 |
714 OMAP2420_AUTO_VLYNQ |
716 CORE_MOD, CM_AUTOIDLE1);
717 cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
720 CORE_MOD, CM_AUTOIDLE2);
721 cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
724 CORE_MOD, OMAP24XX_CM_AUTOIDLE3);
725 cm_write_mod_reg(OMAP24XX_AUTO_PKA |
730 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
732 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
734 /* Put DPLL and both APLLs into autoidle mode */
735 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
736 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
737 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
738 PLL_MOD, CM_AUTOIDLE);
740 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
742 OMAP24XX_AUTO_MPU_WDT |
743 OMAP24XX_AUTO_GPIOS |
744 OMAP24XX_AUTO_32KSYNC |
746 WKUP_MOD, CM_AUTOIDLE);
748 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
750 prm_write_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
752 /* Configure automatic voltage transition */
753 prm_write_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
754 prm_write_reg(OMAP24XX_AUTO_EXTVOLT |
755 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
756 OMAP24XX_MEMRETCTRL |
757 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
758 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
759 OMAP24XX_PRCM_VOLTCTRL);
761 /* Enable wake-up events */
762 prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
766 int __init omap2_pm_init(void)
770 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
771 l = prm_read_reg(OMAP24XX_PRCM_REVISION);
772 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
774 osc_ck = clk_get(NULL, "osc_ck");
775 if (IS_ERR(osc_ck)) {
776 printk(KERN_ERR "could not get osc_ck\n");
780 if (cpu_is_omap242x()) {
781 emul_ck = clk_get(NULL, "emul_ck");
782 if (IS_ERR(emul_ck)) {
783 printk(KERN_ERR "could not get emul_ck\n");
791 pm_init_serial_console();
793 /* Hack to prevent MPU retention when STI console is enabled. */
795 const struct omap_sti_console_config *sti;
797 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
798 struct omap_sti_console_config);
799 if (sti != NULL && sti->enable)
800 sti_console_enabled = 1;
804 * We copy the assembler sleep/wakeup routines to SRAM.
805 * These routines need to be in SRAM as that's the only
806 * memory the MPU can see when it wakes up.
808 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
809 omap24xx_idle_loop_suspend_sz);
811 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
812 omap24xx_cpu_suspend_sz);
814 /* Patch in the correct register addresses for multiboot */
815 omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_power,
817 OMAP_SDRC_REGADDR(SDRC_POWER));
818 omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_dlla_ctrl,
820 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
822 suspend_set_ops(&omap_pm_ops);
823 pm_idle = omap2_pm_idle;
825 l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
827 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
832 late_initcall(omap2_pm_init);