arch/arm/mach-omap2/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Based on pm.c for omap1
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/suspend.h>
  24 #include <linux/sched.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/clk.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34 #include <asm/atomic.h>
  35 #include <asm/mach/time.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <asm/arch/irqs.h>
  40 #include <asm/arch/clock.h>
  41 #include <asm/arch/sram.h>
  42 #include <asm/arch/gpio.h>
  43 #include <asm/arch/pm.h>
  44 #include <asm/arch/mux.h>
  45 #include <asm/arch/dma.h>
  46 #include <asm/arch/board.h>
  47 #include <asm/arch/gpio.h>
  48
  49 #include "prm.h"
  50 #include "prm_regbits_24xx.h"
  51 #include "cm.h"
  52 #include "cm_regbits_24xx.h"
  53 #include "sdrc.h"
  54
  55 /* These addrs are in assembly language code to be patched at runtime */
  56 extern void *omap2_ocs_sdrc_power;
  57 extern void *omap2_ocs_sdrc_dlla_ctrl;
  58
  59 static void (*omap2_sram_idle)(void);
  60 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
  61 static void (*saved_idle)(void);
  62
  63 static u32 omap2_read_32k_sync_counter(void)
  64 {
  65         return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
  66 }
  67
  68 #ifdef CONFIG_PM_DEBUG
  69 int omap2_pm_debug = 0;
  70
  71 static int serial_console_clock_disabled;
  72 static int serial_console_uart;
  73 static unsigned int serial_console_next_disable;
  74
  75 static struct clk *console_iclk, *console_fclk;
  76
  77 static void serial_console_kick(void)
  78 {
  79         serial_console_next_disable = omap2_read_32k_sync_counter();
  80         /* Keep the clocks on for 4 secs */
  81         serial_console_next_disable += 4 * 32768;
  82 }
  83
  84 static void serial_wait_tx(void)
  85 {
  86         static const unsigned long uart_bases[3] = {
  87                 0x4806a000, 0x4806c000, 0x4806e000
  88         };
  89         unsigned long lsr_reg;
  90         int looped = 0;
  91
  92         /* Wait for TX FIFO and THR to get empty */
  93         lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
  94         while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
  95                 looped = 1;
  96         if (looped)
  97                 serial_console_kick();
  98 }
  99
 100 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
 101 {
 102         switch (serial_console_uart)  {
 103         case 1:
 104                 *f1 &= ~(1 << 21);
 105                 break;
 106         case 2:
 107                 *f1 &= ~(1 << 22);
 108                 break;
 109         case 3:
 110                 *f2 &= ~(1 << 2);
 111                 break;
 112         }
 113 }
 114
 115 static void serial_console_sleep(int enable)
 116 {
 117         if (console_iclk == NULL || console_fclk == NULL)
 118                 return;
 119
 120         if (enable) {
 121                 BUG_ON(serial_console_clock_disabled);
 122                 if (clk_get_usecount(console_fclk) == 0)
 123                         return;
 124                 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
 125                         return;
 126                 serial_wait_tx();
 127                 clk_disable(console_iclk);
 128                 clk_disable(console_fclk);
 129                 serial_console_clock_disabled = 1;
 130         } else {
 131                 int serial_wakeup = 0;
 132                 u32 l;
 133
 134                 switch (serial_console_uart)  {
 135                 case 1:
 136                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 137                         if (l & OMAP24XX_ST_UART1)
 138                                 serial_wakeup = 1;
 139                         break;
 140                 case 2:
 141                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 142                         if (l & OMAP24XX_ST_UART2)
 143                                 serial_wakeup = 1;
 144                         break;
 145                 case 3:
 146                         l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
 147                         if (l & OMAP24XX_ST_UART3)
 148                                 serial_wakeup = 1;
 149                         break;
 150                 }
 151                 if (serial_wakeup)
 152                         serial_console_kick();
 153                 if (!serial_console_clock_disabled)
 154                         return;
 155                 clk_enable(console_iclk);
 156                 clk_enable(console_fclk);
 157                 serial_console_clock_disabled = 0;
 158         }
 159 }
 160
 161 static void pm_init_serial_console(void)
 162 {
 163         const struct omap_serial_console_config *conf;
 164         char name[16];
 165         u32 l;
 166
 167         conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
 168                                struct omap_serial_console_config);
 169         if (conf == NULL)
 170                 return;
 171         if (conf->console_uart > 3 || conf->console_uart < 1)
 172                 return;
 173         serial_console_uart = conf->console_uart;
 174         sprintf(name, "uart%d_fck", conf->console_uart);
 175         console_fclk = clk_get(NULL, name);
 176         if (IS_ERR(console_fclk))
 177                 console_fclk = NULL;
 178         name[6] = 'i';
 179         console_iclk = clk_get(NULL, name);
 180         if (IS_ERR(console_fclk))
 181                 console_iclk = NULL;
 182         if (console_fclk == NULL || console_iclk == NULL) {
 183                 serial_console_uart = 0;
 184                 return;
 185         }
 186         switch (serial_console_uart) {
 187         case 1:
 188                 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
 189                 l |= OMAP24XX_ST_UART1;
 190                 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
 191                 break;
 192         case 2:
 193                 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
 194                 l |= OMAP24XX_ST_UART2;
 195                 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
 196                 break;
 197         case 3:
 198                 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKEN2);
 199                 l |= OMAP24XX_ST_UART3;
 200                 prm_write_mod_reg(l, CORE_MOD, OMAP24XX_PM_WKEN2);
 201                 break;
 202         }
 203 }
 204
 205 #define DUMP_PRM_MOD_REG(mod, reg)    \
 206         regs[reg_count].name = #mod "." #reg; \
 207         regs[reg_count++].val = prm_read_mod_reg(mod, reg)
 208 #define DUMP_CM_MOD_REG(mod, reg)     \
 209         regs[reg_count].name = #mod "." #reg; \
 210         regs[reg_count++].val = cm_read_mod_reg(mod, reg)
 211 #define DUMP_PRM_REG(reg) \
 212         regs[reg_count].name = #reg; \
 213         regs[reg_count++].val = prm_read_reg(reg)
 214 #define DUMP_CM_REG(reg) \
 215         regs[reg_count].name = #reg; \
 216         regs[reg_count++].val = cm_read_reg(reg)
 217 #define DUMP_INTC_REG(reg, off) \
 218         regs[reg_count].name = #reg; \
 219         regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
 220
 221 static void omap2_pm_dump(int mode, int resume, unsigned int us)
 222 {
 223         struct reg {
 224                 const char *name;
 225                 u32 val;
 226         } regs[32];
 227         int reg_count = 0, i;
 228         const char *s1 = NULL, *s2 = NULL;
 229
 230         if (!resume) {
 231 #if 0
 232                 /* MPU */
 233                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU);
 234                 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
 235                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
 236                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
 237                 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
 238 #endif
 239 #if 0
 240                 /* INTC */
 241                 DUMP_INTC_REG(INTC_MIR0, 0x0084);
 242                 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
 243                 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
 244 #endif
 245 #if 0
 246                 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
 247                 DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 248                 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
 249                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
 250                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
 251                 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
 252                 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
 253                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL);
 254                 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
 255                 DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);
 256                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL);
 257 #endif
 258 #if 0
 259                 /* DSP */
 260                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
 261                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
 262                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
 263                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 264                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
 265                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 266                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
 267                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
 268                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 269                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
 270 #endif
 271         } else {
 272                 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
 273                 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
 274                 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
 275                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU);
 276 #if 1
 277                 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
 278                 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
 279                 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
 280 #endif
 281         }
 282
 283         switch (mode) {
 284         case 0:
 285                 s1 = "full";
 286                 s2 = "retention";
 287                 break;
 288         case 1:
 289                 s1 = "MPU";
 290                 s2 = "retention";
 291                 break;
 292         case 2:
 293                 s1 = "MPU";
 294                 s2 = "idle";
 295                 break;
 296         }
 297
 298         if (!resume)
 299 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
 300                 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
 301                        jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
 302                                         jiffies));
 303 #else
 304                 printk("--- Going to %s %s\n", s1, s2);
 305 #endif
 306         else
 307                 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
 308         for (i = 0; i < reg_count; i++)
 309                 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 310 }
 311
 312 #else
 313 static inline void serial_console_sleep(int enable) {}
 314 static inline void pm_init_serial_console(void) {}
 315 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
 316 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
 317
 318 #define omap2_pm_debug 0
 319
 320 #endif
 321
 322 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
 323
 324 static ssize_t omap_pm_sleep_while_idle_show(struct kset * subsys, char *buf)
 325 {
 326         return sprintf(buf, "%hu\n", enable_dyn_sleep);
 327 }
 328
 329 static ssize_t omap_pm_sleep_while_idle_store(struct kset * subsys,
 330                                               const char * buf,
 331                                               size_t n)
 332 {
 333         unsigned short value;
 334         if (sscanf(buf, "%hu", &value) != 1 ||
 335             (value != 0 && value != 1)) {
 336                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
 337                 return -EINVAL;
 338         }
 339         enable_dyn_sleep = value;
 340         return n;
 341 }
 342
 343 static struct subsys_attribute sleep_while_idle_attr = {
 344         .attr   = {
 345                 .name = __stringify(sleep_while_idle),
 346                 .mode = 0644,
 347         },
 348         .show   = omap_pm_sleep_while_idle_show,
 349         .store  = omap_pm_sleep_while_idle_store,
 350 };
 351
 352 static struct clk *osc_ck, *emul_ck;
 353
 354 #define CONTROL_DEVCONF         __REG32(OMAP2_CTRL_BASE + 0x274)
 355
 356 static int omap2_fclks_active(void)
 357 {
 358         u32 f1, f2;
 359
 360         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 361         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 362         serial_console_fclk_mask(&f1, &f2);
 363         if (f1 | f2)
 364                 return 1;
 365         return 0;
 366 }
 367
 368 static int omap2_irq_pending(void)
 369 {
 370         u32 pending_reg = IO_ADDRESS(0x480fe098);
 371         int i;
 372
 373         for (i = 0; i < 4; i++) {
 374                 if (__raw_readl(pending_reg))
 375                         return 1;
 376                 pending_reg += 0x20;
 377         }
 378         return 0;
 379 }
 380
 381 static atomic_t sleep_block = ATOMIC_INIT(0);
 382
 383 void omap2_block_sleep(void)
 384 {
 385         atomic_inc(&sleep_block);
 386 }
 387
 388 void omap2_allow_sleep(void)
 389 {
 390         int i;
 391
 392         i = atomic_dec_return(&sleep_block);
 393         BUG_ON(i < 0);
 394 }
 395
 396 static void omap2_enter_full_retention(void)
 397 {
 398         u32 l, sleep_time = 0;
 399
 400         /* There is 1 reference hold for all children of the oscillator
 401          * clock, the following will remove it. If no one else uses the
 402          * oscillator itself it will be disabled if/when we enter retention
 403          * mode.
 404          */
 405         clk_disable(osc_ck);
 406
 407         /* Clear old wake-up events */
 408         /* REVISIT: These write to reserved bits? */
 409         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 410         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 411         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 412
 413         /* Try to enter retention */
 414         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
 415                           MPU_MOD, PM_PWSTCTRL);
 416
 417         /* Workaround to kill USB */
 418         CONTROL_DEVCONF |= 0x00008000;
 419
 420         omap2_gpio_prepare_for_retention();
 421
 422         if (omap2_pm_debug) {
 423                 omap2_pm_dump(0, 0, 0);
 424                 sleep_time = omap2_read_32k_sync_counter();
 425         }
 426
 427         /* One last check for pending IRQs to avoid extra latency due
 428          * to sleeping unnecessarily. */
 429         if (omap2_irq_pending())
 430                 goto no_sleep;
 431
 432         serial_console_sleep(1);
 433         /* Jump to SRAM suspend code */
 434         omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 435 no_sleep:
 436         serial_console_sleep(0);
 437
 438         if (omap2_pm_debug) {
 439                 unsigned long long tmp;
 440                 u32 resume_time;
 441
 442                 resume_time = omap2_read_32k_sync_counter();
 443                 tmp = resume_time - sleep_time;
 444                 tmp *= 1000000;
 445                 omap2_pm_dump(0, 1, tmp / 32768);
 446         }
 447         omap2_gpio_resume_after_retention();
 448
 449         clk_enable(osc_ck);
 450
 451         /* clear CORE wake-up events */
 452         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 453         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 454
 455         /* wakeup domain events */
 456         l = prm_read_mod_reg(WKUP_MOD, PM_WKST);
 457         l &= 0x5;  /* bit 1: GPT1, bit5 GPIO */
 458         prm_write_mod_reg(l, WKUP_MOD, PM_WKST);
 459
 460         /* MPU domain wake events */
 461         l = prm_read_reg(OMAP24XX_PRCM_IRQSTATUS_MPU);
 462         if (l & 0x01)
 463                 prm_write_reg(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU);
 464         if (l & 0x20)
 465                 prm_write_reg(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU);
 466
 467         /* Mask future PRCM-to-MPU interrupts */
 468         prm_write_reg(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU);
 469 }
 470
 471 static int omap2_i2c_active(void)
 472 {
 473         u32 l;
 474
 475         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 476         return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 477 }
 478
 479 static int sti_console_enabled;
 480
 481 static int omap2_allow_mpu_retention(void)
 482 {
 483         u32 l;
 484
 485         if (atomic_read(&sleep_block))
 486                 return 0;
 487
 488         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 489         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 490         if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
 491                  OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
 492                  OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 493                 return 0;
 494         /* Check for UART3. */
 495         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 496         if (l & OMAP24XX_EN_UART3)
 497                 return 0;
 498         if (sti_console_enabled)
 499                 return 0;
 500
 501         return 1;
 502 }
 503
 504 static void omap2_enter_mpu_retention(void)
 505 {
 506         u32 sleep_time = 0;
 507         int only_idle = 0;
 508
 509         /* Putting MPU into the WFI state while a transfer is active
 510          * seems to cause the I2C block to timeout. Why? Good question. */
 511         if (omap2_i2c_active())
 512                 return;
 513
 514         /* The peripherals seem not to be able to wake up the MPU when
 515          * it is in retention mode. */
 516         if (omap2_allow_mpu_retention()) {
 517                 /* REVISIT: These write to reserved bits? */
 518                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 519                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 520                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 521
 522                 /* Try to enter MPU retention */
 523                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 524                                   OMAP_LOGICRETSTATE,
 525                                   MPU_MOD, PM_PWSTCTRL);
 526         } else {
 527                 /* Block MPU retention */
 528
 529                 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 530                 only_idle = 1;
 531         }
 532
 533         if (omap2_pm_debug) {
 534                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 535                 sleep_time = omap2_read_32k_sync_counter();
 536         }
 537
 538         omap2_sram_idle();
 539
 540         if (omap2_pm_debug) {
 541                 unsigned long long tmp;
 542                 u32 resume_time;
 543
 544                 resume_time = omap2_read_32k_sync_counter();
 545                 tmp = resume_time - sleep_time;
 546                 tmp *= 1000000;
 547                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 548         }
 549 }
 550
 551 static int omap2_can_sleep(void)
 552 {
 553         if (!enable_dyn_sleep)
 554                 return 0;
 555         if (omap2_fclks_active())
 556                 return 0;
 557         if (atomic_read(&sleep_block) > 0)
 558                 return 0;
 559         if (clk_get_usecount(osc_ck) > 1)
 560                 return 0;
 561         if (omap_dma_running())
 562                 return 0;
 563
 564         return 1;
 565 }
 566
 567 static void omap2_pm_idle(void)
 568 {
 569         local_irq_disable();
 570         local_fiq_disable();
 571
 572         if (!omap2_can_sleep()) {
 573                 /* timer_dyn_reprogram() takes about 100-200 us to complete.
 574                  * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
 575                  * transfer to complete), the increased latency is too much.
 576                  *
 577                  * omap2_block_sleep() and omap2_allow_sleep() can be used
 578                  * to indicate this.
 579                  */
 580                 if (atomic_read(&sleep_block) == 0) {
 581                         timer_dyn_reprogram();
 582                         if (omap2_irq_pending())
 583                                 goto out;
 584                 }
 585                 omap2_enter_mpu_retention();
 586                 goto out;
 587         }
 588
 589         /*
 590          * Since an interrupt may set up a timer, we don't want to
 591          * reprogram the hardware timer with interrupts enabled.
 592          * Re-enable interrupts only after returning from idle.
 593          */
 594         timer_dyn_reprogram();
 595
 596         if (omap2_irq_pending())
 597                 goto out;
 598
 599         omap2_enter_full_retention();
 600
 601 out:
 602         local_fiq_enable();
 603         local_irq_enable();
 604 }
 605
 606 static int omap2_pm_prepare(void)
 607 {
 608         /* We cannot sleep in idle until we have resumed */
 609         saved_idle = pm_idle;
 610         pm_idle = NULL;
 611
 612         return 0;
 613 }
 614
 615 static int omap2_pm_suspend(void)
 616 {
 617         u32 wken_wkup, mir1;
 618
 619         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 620         prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 621
 622         /* Mask GPT1 */
 623         mir1 = omap_readl(0x480fe0a4);
 624         omap_writel(1 << 5, 0x480fe0ac);
 625
 626         omap2_enter_full_retention();
 627
 628         omap_writel(mir1, 0x480fe0a4);
 629         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 630
 631         return 0;
 632 }
 633
 634 static int omap2_pm_enter(suspend_state_t state)
 635 {
 636         int ret = 0;
 637
 638         switch (state) {
 639         case PM_SUSPEND_STANDBY:
 640         case PM_SUSPEND_MEM:
 641                 ret = omap2_pm_suspend();
 642                 break;
 643         default:
 644                 ret = -EINVAL;
 645         }
 646
 647         return ret;
 648 }
 649
 650 static void omap2_pm_finish(void)
 651 {
 652         pm_idle = saved_idle;
 653 }
 654
 655 static struct platform_suspend_ops omap_pm_ops = {
 656         .prepare        = omap2_pm_prepare,
 657         .enter          = omap2_pm_enter,
 658         .finish         = omap2_pm_finish,
 659         .valid          = suspend_valid_only_mem,
 660 };
 661
 662 static void __init prcm_setup_regs(void)
 663 {
 664         u32 l;
 665
 666         /* Enable autoidle */
 667         prm_write_reg(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
 668
 669         /* Set all domain wakeup dependencies */
 670         prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP);
 671         prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
 672         prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 673         prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
 674         if (cpu_is_omap2430())
 675                 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
 676
 677         l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
 678         /* Enable retention for all memory blocks */
 679         l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
 680                 OMAP24XX_MEM1RETSTATE;
 681
 682         /* Set power state to RETENTION */
 683         l &= ~OMAP_POWERSTATE_MASK;
 684         l |= 0x01 << OMAP_POWERSTATE_SHIFT;
 685         prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
 686
 687         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 688                           OMAP_LOGICRETSTATE,
 689                           MPU_MOD, PM_PWSTCTRL);
 690
 691         /* Power down DSP and GFX */
 692         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 693                           OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 694         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 695                           GFX_MOD, PM_PWSTCTRL);
 696
 697         /* Enable clock auto control for all domains */
 698         cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL);
 699         cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 |
 700                          OMAP24XX_AUTOSTATE_L3,
 701                          CORE_MOD, CM_CLKSTCTRL);
 702         cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL);
 703         cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP,
 704                          OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 705
 706         /* Enable clock autoidle for all domains */
 707         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
 708                          OMAP24XX_AUTO_MAILBOXES |
 709                          OMAP24XX_AUTO_WDT4 |
 710                          OMAP2420_AUTO_WDT3 |
 711                          OMAP24XX_AUTO_MSPRO |
 712                          OMAP2420_AUTO_MMC |
 713                          OMAP24XX_AUTO_FAC |
 714                          OMAP2420_AUTO_EAC |
 715                          OMAP24XX_AUTO_HDQ |
 716                          OMAP24XX_AUTO_UART2 |
 717                          OMAP24XX_AUTO_UART1 |
 718                          OMAP24XX_AUTO_I2C2 |
 719                          OMAP24XX_AUTO_I2C1 |
 720                          OMAP24XX_AUTO_MCSPI2 |
 721                          OMAP24XX_AUTO_MCSPI1 |
 722                          OMAP24XX_AUTO_MCBSP2 |
 723                          OMAP24XX_AUTO_MCBSP1 |
 724                          OMAP24XX_AUTO_GPT12 |
 725                          OMAP24XX_AUTO_GPT11 |
 726                          OMAP24XX_AUTO_GPT10 |
 727                          OMAP24XX_AUTO_GPT9 |
 728                          OMAP24XX_AUTO_GPT8 |
 729                          OMAP24XX_AUTO_GPT7 |
 730                          OMAP24XX_AUTO_GPT6 |
 731                          OMAP24XX_AUTO_GPT5 |
 732                          OMAP24XX_AUTO_GPT4 |
 733                          OMAP24XX_AUTO_GPT3 |
 734                          OMAP24XX_AUTO_GPT2 |
 735                          OMAP2420_AUTO_VLYNQ |
 736                          OMAP24XX_AUTO_DSS,
 737                          CORE_MOD, CM_AUTOIDLE1);
 738         cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
 739                          OMAP24XX_AUTO_SSI |
 740                          OMAP24XX_AUTO_USB,
 741                          CORE_MOD, CM_AUTOIDLE2);
 742         cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
 743                          OMAP24XX_AUTO_GPMC |
 744                          OMAP24XX_AUTO_SDMA,
 745                          CORE_MOD, OMAP24XX_CM_AUTOIDLE3);
 746         cm_write_mod_reg(OMAP24XX_AUTO_PKA |
 747                          OMAP24XX_AUTO_AES |
 748                          OMAP24XX_AUTO_RNG |
 749                          OMAP24XX_AUTO_SHA |
 750                          OMAP24XX_AUTO_DES,
 751                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 752
 753         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 754
 755         /* Put DPLL and both APLLs into autoidle mode */
 756         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 757                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 758                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 759                          PLL_MOD, CM_AUTOIDLE);
 760
 761         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
 762                          OMAP24XX_AUTO_WDT1 |
 763                          OMAP24XX_AUTO_MPU_WDT |
 764                          OMAP24XX_AUTO_GPIOS |
 765                          OMAP24XX_AUTO_32KSYNC |
 766                          OMAP24XX_AUTO_GPT1,
 767                          WKUP_MOD, CM_AUTOIDLE);
 768
 769         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 770          * stabilisation */
 771         prm_write_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
 772
 773         /* Configure automatic voltage transition */
 774         prm_write_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
 775         prm_write_reg(OMAP24XX_AUTO_EXTVOLT |
 776                       (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 777                       OMAP24XX_MEMRETCTRL |
 778                       (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 779                       (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 780                       OMAP24XX_PRCM_VOLTCTRL);
 781
 782         /* Enable wake-up events */
 783         prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
 784                           WKUP_MOD, PM_WKEN);
 785 }
 786
 787 int __init omap2_pm_init(void)
 788 {
 789         u32 l;
 790
 791         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 792         l = prm_read_reg(OMAP24XX_PRCM_REVISION);
 793         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 794
 795         osc_ck = clk_get(NULL, "osc_ck");
 796         if (IS_ERR(osc_ck)) {
 797                 printk(KERN_ERR "could not get osc_ck\n");
 798                 return -ENODEV;
 799         }
 800
 801         if (cpu_is_omap242x()) {
 802                 emul_ck = clk_get(NULL, "emul_ck");
 803                 if (IS_ERR(emul_ck)) {
 804                         printk(KERN_ERR "could not get emul_ck\n");
 805                         clk_put(osc_ck);
 806                         return -ENODEV;
 807                 }
 808         }
 809
 810         prcm_setup_regs();
 811
 812         pm_init_serial_console();
 813
 814         /* Hack to prevent MPU retention when STI console is enabled. */
 815         {
 816                 const struct omap_sti_console_config *sti;
 817
 818                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 819                                       struct omap_sti_console_config);
 820                 if (sti != NULL && sti->enable)
 821                         sti_console_enabled = 1;
 822         }
 823
 824         /*
 825          * We copy the assembler sleep/wakeup routines to SRAM.
 826          * These routines need to be in SRAM as that's the only
 827          * memory the MPU can see when it wakes up.
 828          */
 829         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 830                                          omap24xx_idle_loop_suspend_sz);
 831
 832         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 833                                             omap24xx_cpu_suspend_sz);
 834
 835         /* Patch in the correct register addresses for multiboot */
 836         omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_power,
 837                            omap2_sram_suspend,
 838                            OMAP_SDRC_REGADDR(SDRC_POWER));
 839         omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_dlla_ctrl,
 840                            omap2_sram_suspend,
 841                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 842
 843         suspend_set_ops(&omap_pm_ops);
 844         pm_idle = omap2_pm_idle;
 845
 846         l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 847         if (l)
 848                 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
 849
 850         return 0;
 851 }
 852
 853 late_initcall(omap2_pm_init);