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[ARM] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4
authorPaul Walmsley <paul@pwsan.com>
Wed, 28 Jan 2009 19:08:14 +0000 (12:08 -0700)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Sun, 8 Feb 2009 17:50:33 +0000 (17:50 +0000)
commitb8168d1e3989bc141da6bba87ad49e218ff04658
tree7eabca71f38410867174acb06aa2e2013701ac47tree | snapshot
parentf0587b63c24e0c7539c6e77f1bfc68e6053608c7commit | diff
[ARM] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4

OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and
DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this
into the OMAP3 clock framework.

linux-omap source commit is 050684c18f2ea0b08fdd5233a0cd3c7f96e00a0e.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mach-omap2/clock34xx.h diff | blob | history
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