2 * OMAP3 clock framework
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
22 #include <mach/control.h>
26 #include "cm-regbits-34xx.h"
28 #include "prm-regbits-34xx.h"
30 static void omap3_dpll_recalc(struct clk *clk);
31 static void omap3_clkoutx2_recalc(struct clk *clk);
32 static void omap3_dpll_allow_idle(struct clk *clk);
33 static void omap3_dpll_deny_idle(struct clk *clk);
34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
35 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
36 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
38 /* Maximum DPLL multiplier, divider values for OMAP3 */
39 #define OMAP3_MAX_DPLL_MULT 2048
40 #define OMAP3_MAX_DPLL_DIV 128
43 * DPLL1 supplies clock to the MPU.
44 * DPLL2 supplies clock to the IVA2.
45 * DPLL3 supplies CORE domain clocks.
46 * DPLL4 supplies peripheral clocks.
47 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
50 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
51 #define DPLL_LOW_POWER_STOP 0x1
52 #define DPLL_LOW_POWER_BYPASS 0x5
53 #define DPLL_LOCKED 0x7
57 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
58 static struct clk omap_32k_fck = {
59 .name = "omap_32k_fck",
62 .flags = RATE_FIXED | RATE_PROPAGATES,
65 static struct clk secure_32k_fck = {
66 .name = "secure_32k_fck",
69 .flags = RATE_FIXED | RATE_PROPAGATES,
72 /* Virtual source clocks for osc_sys_ck */
73 static struct clk virt_12m_ck = {
74 .name = "virt_12m_ck",
77 .flags = RATE_FIXED | RATE_PROPAGATES,
80 static struct clk virt_13m_ck = {
81 .name = "virt_13m_ck",
84 .flags = RATE_FIXED | RATE_PROPAGATES,
87 static struct clk virt_16_8m_ck = {
88 .name = "virt_16_8m_ck",
91 .flags = RATE_FIXED | RATE_PROPAGATES,
94 static struct clk virt_19_2m_ck = {
95 .name = "virt_19_2m_ck",
98 .flags = RATE_FIXED | RATE_PROPAGATES,
101 static struct clk virt_26m_ck = {
102 .name = "virt_26m_ck",
105 .flags = RATE_FIXED | RATE_PROPAGATES,
108 static struct clk virt_38_4m_ck = {
109 .name = "virt_38_4m_ck",
112 .flags = RATE_FIXED | RATE_PROPAGATES,
115 static const struct clksel_rate osc_sys_12m_rates[] = {
116 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
120 static const struct clksel_rate osc_sys_13m_rates[] = {
121 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
125 static const struct clksel_rate osc_sys_16_8m_rates[] = {
126 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
130 static const struct clksel_rate osc_sys_19_2m_rates[] = {
131 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
135 static const struct clksel_rate osc_sys_26m_rates[] = {
136 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
140 static const struct clksel_rate osc_sys_38_4m_rates[] = {
141 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
145 static const struct clksel osc_sys_clksel[] = {
146 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
147 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
148 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
149 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
150 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
151 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
155 /* Oscillator clock */
156 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
157 static struct clk osc_sys_ck = {
158 .name = "osc_sys_ck",
160 .init = &omap2_init_clksel_parent,
161 .clksel_reg = OMAP3430_PRM_CLKSEL,
162 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
163 .clksel = osc_sys_clksel,
164 /* REVISIT: deal with autoextclkmode? */
165 .flags = RATE_FIXED | RATE_PROPAGATES,
166 .recalc = &omap2_clksel_recalc,
169 static const struct clksel_rate div2_rates[] = {
170 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
171 { .div = 2, .val = 2, .flags = RATE_IN_343X },
175 static const struct clksel sys_clksel[] = {
176 { .parent = &osc_sys_ck, .rates = div2_rates },
180 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
181 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
182 static struct clk sys_ck = {
185 .parent = &osc_sys_ck,
186 .init = &omap2_init_clksel_parent,
187 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
188 .clksel_mask = OMAP_SYSCLKDIV_MASK,
189 .clksel = sys_clksel,
190 .flags = RATE_PROPAGATES,
191 .recalc = &omap2_clksel_recalc,
194 static struct clk sys_altclk = {
195 .name = "sys_altclk",
197 .flags = RATE_PROPAGATES,
200 /* Optional external clock input for some McBSPs */
201 static struct clk mcbsp_clks = {
202 .name = "mcbsp_clks",
204 .flags = RATE_PROPAGATES,
207 /* PRM EXTERNAL CLOCK OUTPUT */
209 static struct clk sys_clkout1 = {
210 .name = "sys_clkout1",
211 .ops = &clkops_omap2_dflt,
212 .parent = &osc_sys_ck,
213 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
214 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
215 .recalc = &followparent_recalc,
222 static const struct clksel_rate dpll_bypass_rates[] = {
223 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
227 static const struct clksel_rate dpll_locked_rates[] = {
228 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
232 static const struct clksel_rate div16_dpll_rates[] = {
233 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
234 { .div = 2, .val = 2, .flags = RATE_IN_343X },
235 { .div = 3, .val = 3, .flags = RATE_IN_343X },
236 { .div = 4, .val = 4, .flags = RATE_IN_343X },
237 { .div = 5, .val = 5, .flags = RATE_IN_343X },
238 { .div = 6, .val = 6, .flags = RATE_IN_343X },
239 { .div = 7, .val = 7, .flags = RATE_IN_343X },
240 { .div = 8, .val = 8, .flags = RATE_IN_343X },
241 { .div = 9, .val = 9, .flags = RATE_IN_343X },
242 { .div = 10, .val = 10, .flags = RATE_IN_343X },
243 { .div = 11, .val = 11, .flags = RATE_IN_343X },
244 { .div = 12, .val = 12, .flags = RATE_IN_343X },
245 { .div = 13, .val = 13, .flags = RATE_IN_343X },
246 { .div = 14, .val = 14, .flags = RATE_IN_343X },
247 { .div = 15, .val = 15, .flags = RATE_IN_343X },
248 { .div = 16, .val = 16, .flags = RATE_IN_343X },
253 /* MPU clock source */
255 static struct dpll_data dpll1_dd = {
256 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
257 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
258 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
259 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
260 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
261 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
262 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
263 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
264 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
265 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
266 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
267 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
268 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
269 .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT,
270 .max_multiplier = OMAP3_MAX_DPLL_MULT,
271 .max_divider = OMAP3_MAX_DPLL_DIV,
272 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
275 static struct clk dpll1_ck = {
279 .dpll_data = &dpll1_dd,
280 .flags = RATE_PROPAGATES,
281 .round_rate = &omap2_dpll_round_rate,
282 .set_rate = &omap3_noncore_dpll_set_rate,
283 .clkdm_name = "dpll1_clkdm",
284 .recalc = &omap3_dpll_recalc,
288 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
289 * DPLL isn't bypassed.
291 static struct clk dpll1_x2_ck = {
292 .name = "dpll1_x2_ck",
295 .flags = RATE_PROPAGATES,
296 .clkdm_name = "dpll1_clkdm",
297 .recalc = &omap3_clkoutx2_recalc,
300 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
301 static const struct clksel div16_dpll1_x2m2_clksel[] = {
302 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
307 * Does not exist in the TRM - needed to separate the M2 divider from
308 * bypass selection in mpu_ck
310 static struct clk dpll1_x2m2_ck = {
311 .name = "dpll1_x2m2_ck",
313 .parent = &dpll1_x2_ck,
314 .init = &omap2_init_clksel_parent,
315 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
316 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
317 .clksel = div16_dpll1_x2m2_clksel,
318 .flags = RATE_PROPAGATES,
319 .clkdm_name = "dpll1_clkdm",
320 .recalc = &omap2_clksel_recalc,
324 /* IVA2 clock source */
327 static struct dpll_data dpll2_dd = {
328 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
329 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
330 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
331 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
332 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
333 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
334 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
335 (1 << DPLL_LOW_POWER_BYPASS),
336 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
337 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
338 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
339 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
340 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
341 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
342 .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT,
343 .max_multiplier = OMAP3_MAX_DPLL_MULT,
344 .max_divider = OMAP3_MAX_DPLL_DIV,
345 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
348 static struct clk dpll2_ck = {
350 .ops = &clkops_noncore_dpll_ops,
352 .dpll_data = &dpll2_dd,
353 .flags = RATE_PROPAGATES,
354 .round_rate = &omap2_dpll_round_rate,
355 .set_rate = &omap3_noncore_dpll_set_rate,
356 .clkdm_name = "dpll2_clkdm",
357 .recalc = &omap3_dpll_recalc,
360 static const struct clksel div16_dpll2_m2x2_clksel[] = {
361 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
366 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
367 * or CLKOUTX2. CLKOUT seems most plausible.
369 static struct clk dpll2_m2_ck = {
370 .name = "dpll2_m2_ck",
373 .init = &omap2_init_clksel_parent,
374 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
375 OMAP3430_CM_CLKSEL2_PLL),
376 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
377 .clksel = div16_dpll2_m2x2_clksel,
378 .flags = RATE_PROPAGATES,
379 .clkdm_name = "dpll2_clkdm",
380 .recalc = &omap2_clksel_recalc,
385 * Source clock for all interfaces and for some device fclks
386 * REVISIT: Also supports fast relock bypass - not included below
388 static struct dpll_data dpll3_dd = {
389 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
390 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
391 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
392 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
393 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
394 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
395 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
396 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
397 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
398 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
399 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
400 .max_multiplier = OMAP3_MAX_DPLL_MULT,
401 .max_divider = OMAP3_MAX_DPLL_DIV,
402 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
405 static struct clk dpll3_ck = {
409 .dpll_data = &dpll3_dd,
410 .flags = RATE_PROPAGATES,
411 .round_rate = &omap2_dpll_round_rate,
412 .clkdm_name = "dpll3_clkdm",
413 .recalc = &omap3_dpll_recalc,
417 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
418 * DPLL isn't bypassed
420 static struct clk dpll3_x2_ck = {
421 .name = "dpll3_x2_ck",
424 .flags = RATE_PROPAGATES,
425 .clkdm_name = "dpll3_clkdm",
426 .recalc = &omap3_clkoutx2_recalc,
429 static const struct clksel_rate div31_dpll3_rates[] = {
430 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
431 { .div = 2, .val = 2, .flags = RATE_IN_343X },
432 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
433 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
434 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
435 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
436 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
437 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
438 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
439 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
440 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
441 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
442 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
443 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
444 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
445 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
446 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
447 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
448 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
449 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
450 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
451 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
452 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
453 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
454 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
455 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
456 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
457 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
458 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
459 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
460 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
464 static const struct clksel div31_dpll3m2_clksel[] = {
465 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
471 * REVISIT: This DPLL output divider must be changed in SRAM, so until
472 * that code is ready, this should remain a 'read-only' clksel clock.
474 static struct clk dpll3_m2_ck = {
475 .name = "dpll3_m2_ck",
478 .init = &omap2_init_clksel_parent,
479 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
480 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
481 .clksel = div31_dpll3m2_clksel,
482 .flags = RATE_PROPAGATES,
483 .clkdm_name = "dpll3_clkdm",
484 .recalc = &omap2_clksel_recalc,
487 static const struct clksel core_ck_clksel[] = {
488 { .parent = &sys_ck, .rates = dpll_bypass_rates },
489 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
493 static struct clk core_ck = {
496 .init = &omap2_init_clksel_parent,
497 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
498 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
499 .clksel = core_ck_clksel,
500 .flags = RATE_PROPAGATES,
501 .recalc = &omap2_clksel_recalc,
504 static const struct clksel dpll3_m2x2_ck_clksel[] = {
505 { .parent = &sys_ck, .rates = dpll_bypass_rates },
506 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
510 static struct clk dpll3_m2x2_ck = {
511 .name = "dpll3_m2x2_ck",
513 .init = &omap2_init_clksel_parent,
514 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
515 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
516 .clksel = dpll3_m2x2_ck_clksel,
517 .flags = RATE_PROPAGATES,
518 .clkdm_name = "dpll3_clkdm",
519 .recalc = &omap2_clksel_recalc,
522 /* The PWRDN bit is apparently only available on 3430ES2 and above */
523 static const struct clksel div16_dpll3_clksel[] = {
524 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
528 /* This virtual clock is the source for dpll3_m3x2_ck */
529 static struct clk dpll3_m3_ck = {
530 .name = "dpll3_m3_ck",
533 .init = &omap2_init_clksel_parent,
534 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
535 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
536 .clksel = div16_dpll3_clksel,
537 .flags = RATE_PROPAGATES,
538 .clkdm_name = "dpll3_clkdm",
539 .recalc = &omap2_clksel_recalc,
542 /* The PWRDN bit is apparently only available on 3430ES2 and above */
543 static struct clk dpll3_m3x2_ck = {
544 .name = "dpll3_m3x2_ck",
545 .ops = &clkops_omap2_dflt_wait,
546 .parent = &dpll3_m3_ck,
547 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
548 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
549 .flags = RATE_PROPAGATES | INVERT_ENABLE,
550 .clkdm_name = "dpll3_clkdm",
551 .recalc = &omap3_clkoutx2_recalc,
554 static const struct clksel emu_core_alwon_ck_clksel[] = {
555 { .parent = &sys_ck, .rates = dpll_bypass_rates },
556 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
560 static struct clk emu_core_alwon_ck = {
561 .name = "emu_core_alwon_ck",
563 .parent = &dpll3_m3x2_ck,
564 .init = &omap2_init_clksel_parent,
565 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
566 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
567 .clksel = emu_core_alwon_ck_clksel,
568 .flags = RATE_PROPAGATES,
569 .clkdm_name = "dpll3_clkdm",
570 .recalc = &omap2_clksel_recalc,
574 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
576 static struct dpll_data dpll4_dd = {
577 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
578 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
579 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
580 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
581 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
582 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
583 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
584 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
585 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
586 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
587 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
588 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
589 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
590 .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT,
591 .max_multiplier = OMAP3_MAX_DPLL_MULT,
592 .max_divider = OMAP3_MAX_DPLL_DIV,
593 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
596 static struct clk dpll4_ck = {
598 .ops = &clkops_noncore_dpll_ops,
600 .dpll_data = &dpll4_dd,
601 .flags = RATE_PROPAGATES,
602 .round_rate = &omap2_dpll_round_rate,
603 .set_rate = &omap3_dpll4_set_rate,
604 .clkdm_name = "dpll4_clkdm",
605 .recalc = &omap3_dpll_recalc,
609 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
610 * DPLL isn't bypassed --
611 * XXX does this serve any downstream clocks?
613 static struct clk dpll4_x2_ck = {
614 .name = "dpll4_x2_ck",
617 .flags = RATE_PROPAGATES,
618 .clkdm_name = "dpll4_clkdm",
619 .recalc = &omap3_clkoutx2_recalc,
622 static const struct clksel div16_dpll4_clksel[] = {
623 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
627 /* This virtual clock is the source for dpll4_m2x2_ck */
628 static struct clk dpll4_m2_ck = {
629 .name = "dpll4_m2_ck",
632 .init = &omap2_init_clksel_parent,
633 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
634 .clksel_mask = OMAP3430_DIV_96M_MASK,
635 .clksel = div16_dpll4_clksel,
636 .flags = RATE_PROPAGATES,
637 .clkdm_name = "dpll4_clkdm",
638 .recalc = &omap2_clksel_recalc,
641 /* The PWRDN bit is apparently only available on 3430ES2 and above */
642 static struct clk dpll4_m2x2_ck = {
643 .name = "dpll4_m2x2_ck",
644 .ops = &clkops_omap2_dflt_wait,
645 .parent = &dpll4_m2_ck,
646 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
647 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
648 .flags = RATE_PROPAGATES | INVERT_ENABLE,
649 .clkdm_name = "dpll4_clkdm",
650 .recalc = &omap3_clkoutx2_recalc,
653 static const struct clksel omap_96m_alwon_fck_clksel[] = {
654 { .parent = &sys_ck, .rates = dpll_bypass_rates },
655 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
660 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
661 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
662 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
665 static struct clk omap_96m_alwon_fck = {
666 .name = "omap_96m_alwon_fck",
668 .parent = &dpll4_m2x2_ck,
669 .init = &omap2_init_clksel_parent,
670 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
671 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
672 .clksel = omap_96m_alwon_fck_clksel,
673 .flags = RATE_PROPAGATES,
674 .recalc = &omap2_clksel_recalc,
677 static struct clk cm_96m_fck = {
678 .name = "cm_96m_fck",
680 .parent = &omap_96m_alwon_fck,
681 .flags = RATE_PROPAGATES,
682 .recalc = &followparent_recalc,
685 static const struct clksel_rate omap_96m_dpll_rates[] = {
686 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
690 static const struct clksel_rate omap_96m_sys_rates[] = {
691 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
695 static const struct clksel omap_96m_fck_clksel[] = {
696 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
697 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
701 static struct clk omap_96m_fck = {
702 .name = "omap_96m_fck",
705 .init = &omap2_init_clksel_parent,
706 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
707 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
708 .clksel = omap_96m_fck_clksel,
709 .flags = RATE_PROPAGATES,
710 .recalc = &omap2_clksel_recalc,
713 /* This virtual clock is the source for dpll4_m3x2_ck */
714 static struct clk dpll4_m3_ck = {
715 .name = "dpll4_m3_ck",
718 .init = &omap2_init_clksel_parent,
719 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
720 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
721 .clksel = div16_dpll4_clksel,
722 .flags = RATE_PROPAGATES,
723 .clkdm_name = "dpll4_clkdm",
724 .recalc = &omap2_clksel_recalc,
727 /* The PWRDN bit is apparently only available on 3430ES2 and above */
728 static struct clk dpll4_m3x2_ck = {
729 .name = "dpll4_m3x2_ck",
730 .ops = &clkops_omap2_dflt_wait,
731 .parent = &dpll4_m3_ck,
732 .init = &omap2_init_clksel_parent,
733 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
734 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
735 .flags = RATE_PROPAGATES | INVERT_ENABLE,
736 .clkdm_name = "dpll4_clkdm",
737 .recalc = &omap3_clkoutx2_recalc,
740 static const struct clksel virt_omap_54m_fck_clksel[] = {
741 { .parent = &sys_ck, .rates = dpll_bypass_rates },
742 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
746 static struct clk virt_omap_54m_fck = {
747 .name = "virt_omap_54m_fck",
749 .parent = &dpll4_m3x2_ck,
750 .init = &omap2_init_clksel_parent,
751 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
752 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
753 .clksel = virt_omap_54m_fck_clksel,
754 .flags = RATE_PROPAGATES,
755 .recalc = &omap2_clksel_recalc,
758 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
759 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
763 static const struct clksel_rate omap_54m_alt_rates[] = {
764 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
768 static const struct clksel omap_54m_clksel[] = {
769 { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
770 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
774 static struct clk omap_54m_fck = {
775 .name = "omap_54m_fck",
777 .init = &omap2_init_clksel_parent,
778 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
779 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
780 .clksel = omap_54m_clksel,
781 .flags = RATE_PROPAGATES,
782 .recalc = &omap2_clksel_recalc,
785 static const struct clksel_rate omap_48m_cm96m_rates[] = {
786 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
790 static const struct clksel_rate omap_48m_alt_rates[] = {
791 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
795 static const struct clksel omap_48m_clksel[] = {
796 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
797 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
801 static struct clk omap_48m_fck = {
802 .name = "omap_48m_fck",
804 .init = &omap2_init_clksel_parent,
805 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
806 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
807 .clksel = omap_48m_clksel,
808 .flags = RATE_PROPAGATES,
809 .recalc = &omap2_clksel_recalc,
812 static struct clk omap_12m_fck = {
813 .name = "omap_12m_fck",
815 .parent = &omap_48m_fck,
817 .flags = RATE_PROPAGATES,
818 .recalc = &omap2_fixed_divisor_recalc,
821 /* This virstual clock is the source for dpll4_m4x2_ck */
822 static struct clk dpll4_m4_ck = {
823 .name = "dpll4_m4_ck",
826 .init = &omap2_init_clksel_parent,
827 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
828 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
829 .clksel = div16_dpll4_clksel,
830 .flags = RATE_PROPAGATES,
831 .clkdm_name = "dpll4_clkdm",
832 .recalc = &omap2_clksel_recalc,
833 .set_rate = &omap2_clksel_set_rate,
834 .round_rate = &omap2_clksel_round_rate,
837 /* The PWRDN bit is apparently only available on 3430ES2 and above */
838 static struct clk dpll4_m4x2_ck = {
839 .name = "dpll4_m4x2_ck",
840 .ops = &clkops_omap2_dflt_wait,
841 .parent = &dpll4_m4_ck,
842 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
843 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
844 .flags = RATE_PROPAGATES | INVERT_ENABLE,
845 .clkdm_name = "dpll4_clkdm",
846 .recalc = &omap3_clkoutx2_recalc,
849 /* This virtual clock is the source for dpll4_m5x2_ck */
850 static struct clk dpll4_m5_ck = {
851 .name = "dpll4_m5_ck",
854 .init = &omap2_init_clksel_parent,
855 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
856 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
857 .clksel = div16_dpll4_clksel,
858 .flags = RATE_PROPAGATES,
859 .clkdm_name = "dpll4_clkdm",
860 .recalc = &omap2_clksel_recalc,
863 /* The PWRDN bit is apparently only available on 3430ES2 and above */
864 static struct clk dpll4_m5x2_ck = {
865 .name = "dpll4_m5x2_ck",
866 .ops = &clkops_omap2_dflt_wait,
867 .parent = &dpll4_m5_ck,
868 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
869 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
870 .flags = RATE_PROPAGATES | INVERT_ENABLE,
871 .clkdm_name = "dpll4_clkdm",
872 .recalc = &omap3_clkoutx2_recalc,
875 /* This virtual clock is the source for dpll4_m6x2_ck */
876 static struct clk dpll4_m6_ck = {
877 .name = "dpll4_m6_ck",
880 .init = &omap2_init_clksel_parent,
881 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
882 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
883 .clksel = div16_dpll4_clksel,
884 .flags = RATE_PROPAGATES,
885 .clkdm_name = "dpll4_clkdm",
886 .recalc = &omap2_clksel_recalc,
889 /* The PWRDN bit is apparently only available on 3430ES2 and above */
890 static struct clk dpll4_m6x2_ck = {
891 .name = "dpll4_m6x2_ck",
892 .ops = &clkops_omap2_dflt_wait,
893 .parent = &dpll4_m6_ck,
894 .init = &omap2_init_clksel_parent,
895 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
896 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
897 .flags = RATE_PROPAGATES | INVERT_ENABLE,
898 .clkdm_name = "dpll4_clkdm",
899 .recalc = &omap3_clkoutx2_recalc,
902 static struct clk emu_per_alwon_ck = {
903 .name = "emu_per_alwon_ck",
905 .parent = &dpll4_m6x2_ck,
906 .flags = RATE_PROPAGATES,
907 .clkdm_name = "dpll4_clkdm",
908 .recalc = &followparent_recalc,
912 /* Supplies 120MHz clock, USIM source clock */
915 static struct dpll_data dpll5_dd = {
916 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
917 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
918 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
919 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
920 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
921 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
922 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
923 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
924 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
925 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
926 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
927 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
928 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
929 .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
930 .max_multiplier = OMAP3_MAX_DPLL_MULT,
931 .max_divider = OMAP3_MAX_DPLL_DIV,
932 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
935 static struct clk dpll5_ck = {
937 .ops = &clkops_noncore_dpll_ops,
939 .dpll_data = &dpll5_dd,
940 .flags = RATE_PROPAGATES,
941 .round_rate = &omap2_dpll_round_rate,
942 .set_rate = &omap3_noncore_dpll_set_rate,
943 .clkdm_name = "dpll5_clkdm",
944 .recalc = &omap3_dpll_recalc,
947 static const struct clksel div16_dpll5_clksel[] = {
948 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
952 static struct clk dpll5_m2_ck = {
953 .name = "dpll5_m2_ck",
956 .init = &omap2_init_clksel_parent,
957 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
958 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
959 .clksel = div16_dpll5_clksel,
960 .flags = RATE_PROPAGATES,
961 .clkdm_name = "dpll5_clkdm",
962 .recalc = &omap2_clksel_recalc,
965 static const struct clksel omap_120m_fck_clksel[] = {
966 { .parent = &sys_ck, .rates = dpll_bypass_rates },
967 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
971 static struct clk omap_120m_fck = {
972 .name = "omap_120m_fck",
974 .parent = &dpll5_m2_ck,
975 .init = &omap2_init_clksel_parent,
976 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
977 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
978 .clksel = omap_120m_fck_clksel,
979 .flags = RATE_PROPAGATES,
980 .recalc = &omap2_clksel_recalc,
983 /* CM EXTERNAL CLOCK OUTPUTS */
985 static const struct clksel_rate clkout2_src_core_rates[] = {
986 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
990 static const struct clksel_rate clkout2_src_sys_rates[] = {
991 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
995 static const struct clksel_rate clkout2_src_96m_rates[] = {
996 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1000 static const struct clksel_rate clkout2_src_54m_rates[] = {
1001 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1005 static const struct clksel clkout2_src_clksel[] = {
1006 { .parent = &core_ck, .rates = clkout2_src_core_rates },
1007 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
1008 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
1009 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
1013 static struct clk clkout2_src_ck = {
1014 .name = "clkout2_src_ck",
1015 .ops = &clkops_omap2_dflt,
1016 .init = &omap2_init_clksel_parent,
1017 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
1018 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
1019 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1020 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
1021 .clksel = clkout2_src_clksel,
1022 .flags = RATE_PROPAGATES,
1023 .clkdm_name = "core_clkdm",
1024 .recalc = &omap2_clksel_recalc,
1027 static const struct clksel_rate sys_clkout2_rates[] = {
1028 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1029 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1030 { .div = 4, .val = 2, .flags = RATE_IN_343X },
1031 { .div = 8, .val = 3, .flags = RATE_IN_343X },
1032 { .div = 16, .val = 4, .flags = RATE_IN_343X },
1036 static const struct clksel sys_clkout2_clksel[] = {
1037 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1041 static struct clk sys_clkout2 = {
1042 .name = "sys_clkout2",
1043 .ops = &clkops_null,
1044 .init = &omap2_init_clksel_parent,
1045 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1046 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1047 .clksel = sys_clkout2_clksel,
1048 .recalc = &omap2_clksel_recalc,
1051 /* CM OUTPUT CLOCKS */
1053 static struct clk corex2_fck = {
1054 .name = "corex2_fck",
1055 .ops = &clkops_null,
1056 .parent = &dpll3_m2x2_ck,
1057 .flags = RATE_PROPAGATES,
1058 .recalc = &followparent_recalc,
1061 /* DPLL power domain clock controls */
1063 static const struct clksel_rate div4_rates[] = {
1064 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1065 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1066 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1070 static const struct clksel div4_core_clksel[] = {
1071 { .parent = &core_ck, .rates = div4_rates },
1076 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1077 * may be inconsistent here?
1079 static struct clk dpll1_fck = {
1080 .name = "dpll1_fck",
1081 .ops = &clkops_null,
1083 .init = &omap2_init_clksel_parent,
1084 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1085 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1086 .clksel = div4_core_clksel,
1087 .flags = RATE_PROPAGATES,
1088 .recalc = &omap2_clksel_recalc,
1093 * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1094 * derives from the high-frequency bypass clock originating from DPLL3,
1095 * called 'dpll1_fck'
1097 static const struct clksel mpu_clksel[] = {
1098 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
1099 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1103 static struct clk mpu_ck = {
1105 .ops = &clkops_null,
1106 .parent = &dpll1_x2m2_ck,
1107 .init = &omap2_init_clksel_parent,
1108 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1109 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1110 .clksel = mpu_clksel,
1111 .flags = RATE_PROPAGATES,
1112 .clkdm_name = "mpu_clkdm",
1113 .recalc = &omap2_clksel_recalc,
1116 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1117 static const struct clksel_rate arm_fck_rates[] = {
1118 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1119 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1123 static const struct clksel arm_fck_clksel[] = {
1124 { .parent = &mpu_ck, .rates = arm_fck_rates },
1128 static struct clk arm_fck = {
1130 .ops = &clkops_null,
1132 .init = &omap2_init_clksel_parent,
1133 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1134 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1135 .clksel = arm_fck_clksel,
1136 .flags = RATE_PROPAGATES,
1137 .recalc = &omap2_clksel_recalc,
1140 /* XXX What about neon_clkdm ? */
1143 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1144 * although it is referenced - so this is a guess
1146 static struct clk emu_mpu_alwon_ck = {
1147 .name = "emu_mpu_alwon_ck",
1148 .ops = &clkops_null,
1150 .flags = RATE_PROPAGATES,
1151 .recalc = &followparent_recalc,
1154 static struct clk dpll2_fck = {
1155 .name = "dpll2_fck",
1156 .ops = &clkops_null,
1158 .init = &omap2_init_clksel_parent,
1159 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1160 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1161 .clksel = div4_core_clksel,
1162 .flags = RATE_PROPAGATES,
1163 .recalc = &omap2_clksel_recalc,
1168 * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1169 * derives from the high-frequency bypass clock originating from DPLL3,
1170 * called 'dpll2_fck'
1173 static const struct clksel iva2_clksel[] = {
1174 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1175 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1179 static struct clk iva2_ck = {
1181 .ops = &clkops_omap2_dflt_wait,
1182 .parent = &dpll2_m2_ck,
1183 .init = &omap2_init_clksel_parent,
1184 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1185 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1186 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1187 OMAP3430_CM_IDLEST_PLL),
1188 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1189 .clksel = iva2_clksel,
1190 .flags = RATE_PROPAGATES,
1191 .clkdm_name = "iva2_clkdm",
1192 .recalc = &omap2_clksel_recalc,
1195 /* Common interface clocks */
1197 static const struct clksel div2_core_clksel[] = {
1198 { .parent = &core_ck, .rates = div2_rates },
1202 static struct clk l3_ick = {
1204 .ops = &clkops_null,
1206 .init = &omap2_init_clksel_parent,
1207 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1208 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1209 .clksel = div2_core_clksel,
1210 .flags = RATE_PROPAGATES,
1211 .clkdm_name = "core_l3_clkdm",
1212 .recalc = &omap2_clksel_recalc,
1215 static const struct clksel div2_l3_clksel[] = {
1216 { .parent = &l3_ick, .rates = div2_rates },
1220 static struct clk l4_ick = {
1222 .ops = &clkops_null,
1224 .init = &omap2_init_clksel_parent,
1225 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1226 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1227 .clksel = div2_l3_clksel,
1228 .flags = RATE_PROPAGATES,
1229 .clkdm_name = "core_l4_clkdm",
1230 .recalc = &omap2_clksel_recalc,
1234 static const struct clksel div2_l4_clksel[] = {
1235 { .parent = &l4_ick, .rates = div2_rates },
1239 static struct clk rm_ick = {
1241 .ops = &clkops_null,
1243 .init = &omap2_init_clksel_parent,
1244 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1245 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1246 .clksel = div2_l4_clksel,
1247 .recalc = &omap2_clksel_recalc,
1250 /* GFX power domain */
1252 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1254 static const struct clksel gfx_l3_clksel[] = {
1255 { .parent = &l3_ick, .rates = gfx_l3_rates },
1259 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1260 static struct clk gfx_l3_ck = {
1261 .name = "gfx_l3_ck",
1262 .ops = &clkops_omap2_dflt_wait,
1264 .init = &omap2_init_clksel_parent,
1265 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1266 .enable_bit = OMAP_EN_GFX_SHIFT,
1267 .recalc = &followparent_recalc,
1270 static struct clk gfx_l3_fck = {
1271 .name = "gfx_l3_fck",
1272 .ops = &clkops_null,
1273 .parent = &gfx_l3_ck,
1274 .init = &omap2_init_clksel_parent,
1275 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1276 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1277 .clksel = gfx_l3_clksel,
1278 .flags = RATE_PROPAGATES,
1279 .clkdm_name = "gfx_3430es1_clkdm",
1280 .recalc = &omap2_clksel_recalc,
1283 static struct clk gfx_l3_ick = {
1284 .name = "gfx_l3_ick",
1285 .ops = &clkops_null,
1286 .parent = &gfx_l3_ck,
1287 .clkdm_name = "gfx_3430es1_clkdm",
1288 .recalc = &followparent_recalc,
1291 static struct clk gfx_cg1_ck = {
1292 .name = "gfx_cg1_ck",
1293 .ops = &clkops_omap2_dflt_wait,
1294 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1295 .init = &omap2_init_clk_clkdm,
1296 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1297 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1298 .clkdm_name = "gfx_3430es1_clkdm",
1299 .recalc = &followparent_recalc,
1302 static struct clk gfx_cg2_ck = {
1303 .name = "gfx_cg2_ck",
1304 .ops = &clkops_omap2_dflt_wait,
1305 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1306 .init = &omap2_init_clk_clkdm,
1307 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1308 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1309 .clkdm_name = "gfx_3430es1_clkdm",
1310 .recalc = &followparent_recalc,
1313 /* SGX power domain - 3430ES2 only */
1315 static const struct clksel_rate sgx_core_rates[] = {
1316 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1317 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1318 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1322 static const struct clksel_rate sgx_96m_rates[] = {
1323 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1327 static const struct clksel sgx_clksel[] = {
1328 { .parent = &core_ck, .rates = sgx_core_rates },
1329 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1333 static struct clk sgx_fck = {
1335 .ops = &clkops_omap2_dflt_wait,
1336 .init = &omap2_init_clksel_parent,
1337 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1338 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1339 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1340 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1341 .clksel = sgx_clksel,
1342 .clkdm_name = "sgx_clkdm",
1343 .recalc = &omap2_clksel_recalc,
1346 static struct clk sgx_ick = {
1348 .ops = &clkops_omap2_dflt_wait,
1350 .init = &omap2_init_clk_clkdm,
1351 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1352 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1353 .clkdm_name = "sgx_clkdm",
1354 .recalc = &followparent_recalc,
1357 /* CORE power domain */
1359 static struct clk d2d_26m_fck = {
1360 .name = "d2d_26m_fck",
1361 .ops = &clkops_omap2_dflt_wait,
1363 .init = &omap2_init_clk_clkdm,
1364 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1365 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1366 .clkdm_name = "d2d_clkdm",
1367 .recalc = &followparent_recalc,
1370 static const struct clksel omap343x_gpt_clksel[] = {
1371 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1372 { .parent = &sys_ck, .rates = gpt_sys_rates },
1376 static struct clk gpt10_fck = {
1377 .name = "gpt10_fck",
1378 .ops = &clkops_omap2_dflt_wait,
1380 .init = &omap2_init_clksel_parent,
1381 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1382 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1383 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1384 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1385 .clksel = omap343x_gpt_clksel,
1386 .clkdm_name = "core_l4_clkdm",
1387 .recalc = &omap2_clksel_recalc,
1390 static struct clk gpt11_fck = {
1391 .name = "gpt11_fck",
1392 .ops = &clkops_omap2_dflt_wait,
1394 .init = &omap2_init_clksel_parent,
1395 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1396 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1397 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1398 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1399 .clksel = omap343x_gpt_clksel,
1400 .clkdm_name = "core_l4_clkdm",
1401 .recalc = &omap2_clksel_recalc,
1404 static struct clk cpefuse_fck = {
1405 .name = "cpefuse_fck",
1406 .ops = &clkops_omap2_dflt,
1408 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1409 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1410 .recalc = &followparent_recalc,
1413 static struct clk ts_fck = {
1415 .ops = &clkops_omap2_dflt,
1416 .parent = &omap_32k_fck,
1417 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1418 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1419 .recalc = &followparent_recalc,
1422 static struct clk usbtll_fck = {
1423 .name = "usbtll_fck",
1424 .ops = &clkops_omap2_dflt,
1425 .parent = &omap_120m_fck,
1426 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1427 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1428 .recalc = &followparent_recalc,
1431 /* CORE 96M FCLK-derived clocks */
1433 static struct clk core_96m_fck = {
1434 .name = "core_96m_fck",
1435 .ops = &clkops_null,
1436 .parent = &omap_96m_fck,
1437 .flags = RATE_PROPAGATES,
1438 .clkdm_name = "core_l4_clkdm",
1439 .recalc = &followparent_recalc,
1442 static struct clk mmchs3_fck = {
1443 .name = "mmchs_fck",
1444 .ops = &clkops_omap2_dflt_wait,
1446 .parent = &core_96m_fck,
1447 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1448 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1449 .clkdm_name = "core_l4_clkdm",
1450 .recalc = &followparent_recalc,
1453 static struct clk mmchs2_fck = {
1454 .name = "mmchs_fck",
1455 .ops = &clkops_omap2_dflt_wait,
1457 .parent = &core_96m_fck,
1458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1459 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1460 .clkdm_name = "core_l4_clkdm",
1461 .recalc = &followparent_recalc,
1464 static struct clk mspro_fck = {
1465 .name = "mspro_fck",
1466 .ops = &clkops_omap2_dflt_wait,
1467 .parent = &core_96m_fck,
1468 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1469 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1470 .clkdm_name = "core_l4_clkdm",
1471 .recalc = &followparent_recalc,
1474 static struct clk mmchs1_fck = {
1475 .name = "mmchs_fck",
1476 .ops = &clkops_omap2_dflt_wait,
1477 .parent = &core_96m_fck,
1478 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1479 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1480 .clkdm_name = "core_l4_clkdm",
1481 .recalc = &followparent_recalc,
1484 static struct clk i2c3_fck = {
1486 .ops = &clkops_omap2_dflt_wait,
1488 .parent = &core_96m_fck,
1489 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1490 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1491 .clkdm_name = "core_l4_clkdm",
1492 .recalc = &followparent_recalc,
1495 static struct clk i2c2_fck = {
1497 .ops = &clkops_omap2_dflt_wait,
1499 .parent = &core_96m_fck,
1500 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1501 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1502 .clkdm_name = "core_l4_clkdm",
1503 .recalc = &followparent_recalc,
1506 static struct clk i2c1_fck = {
1508 .ops = &clkops_omap2_dflt_wait,
1510 .parent = &core_96m_fck,
1511 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1512 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1513 .clkdm_name = "core_l4_clkdm",
1514 .recalc = &followparent_recalc,
1518 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1519 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1521 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1522 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1526 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1527 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1531 static const struct clksel mcbsp_15_clksel[] = {
1532 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1533 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1537 static struct clk mcbsp5_fck = {
1538 .name = "mcbsp_fck",
1539 .ops = &clkops_omap2_dflt_wait,
1541 .init = &omap2_init_clksel_parent,
1542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1543 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1544 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1545 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1546 .clksel = mcbsp_15_clksel,
1547 .clkdm_name = "core_l4_clkdm",
1548 .recalc = &omap2_clksel_recalc,
1551 static struct clk mcbsp1_fck = {
1552 .name = "mcbsp_fck",
1553 .ops = &clkops_omap2_dflt_wait,
1555 .init = &omap2_init_clksel_parent,
1556 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1557 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1558 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1559 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1560 .clksel = mcbsp_15_clksel,
1561 .clkdm_name = "core_l4_clkdm",
1562 .recalc = &omap2_clksel_recalc,
1565 /* CORE_48M_FCK-derived clocks */
1567 static struct clk core_48m_fck = {
1568 .name = "core_48m_fck",
1569 .ops = &clkops_null,
1570 .parent = &omap_48m_fck,
1571 .flags = RATE_PROPAGATES,
1572 .clkdm_name = "core_l4_clkdm",
1573 .recalc = &followparent_recalc,
1576 static struct clk mcspi4_fck = {
1577 .name = "mcspi_fck",
1578 .ops = &clkops_omap2_dflt_wait,
1580 .parent = &core_48m_fck,
1581 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1582 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1583 .recalc = &followparent_recalc,
1586 static struct clk mcspi3_fck = {
1587 .name = "mcspi_fck",
1588 .ops = &clkops_omap2_dflt_wait,
1590 .parent = &core_48m_fck,
1591 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1592 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1593 .recalc = &followparent_recalc,
1596 static struct clk mcspi2_fck = {
1597 .name = "mcspi_fck",
1598 .ops = &clkops_omap2_dflt_wait,
1600 .parent = &core_48m_fck,
1601 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1602 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1603 .recalc = &followparent_recalc,
1606 static struct clk mcspi1_fck = {
1607 .name = "mcspi_fck",
1608 .ops = &clkops_omap2_dflt_wait,
1610 .parent = &core_48m_fck,
1611 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1612 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1613 .recalc = &followparent_recalc,
1616 static struct clk uart2_fck = {
1617 .name = "uart2_fck",
1618 .ops = &clkops_omap2_dflt_wait,
1619 .parent = &core_48m_fck,
1620 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1621 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1622 .recalc = &followparent_recalc,
1625 static struct clk uart1_fck = {
1626 .name = "uart1_fck",
1627 .ops = &clkops_omap2_dflt_wait,
1628 .parent = &core_48m_fck,
1629 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1630 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1631 .recalc = &followparent_recalc,
1634 static struct clk fshostusb_fck = {
1635 .name = "fshostusb_fck",
1636 .ops = &clkops_omap2_dflt_wait,
1637 .parent = &core_48m_fck,
1638 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1639 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1640 .recalc = &followparent_recalc,
1643 /* CORE_12M_FCK based clocks */
1645 static struct clk core_12m_fck = {
1646 .name = "core_12m_fck",
1647 .ops = &clkops_null,
1648 .parent = &omap_12m_fck,
1649 .flags = RATE_PROPAGATES,
1650 .clkdm_name = "core_l4_clkdm",
1651 .recalc = &followparent_recalc,
1654 static struct clk hdq_fck = {
1656 .ops = &clkops_omap2_dflt_wait,
1657 .parent = &core_12m_fck,
1658 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1659 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1660 .recalc = &followparent_recalc,
1663 /* DPLL3-derived clock */
1665 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1666 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1667 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1668 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1669 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1670 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1671 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1675 static const struct clksel ssi_ssr_clksel[] = {
1676 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1680 static struct clk ssi_ssr_fck = {
1681 .name = "ssi_ssr_fck",
1682 .ops = &clkops_omap2_dflt,
1683 .init = &omap2_init_clksel_parent,
1684 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1685 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1686 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1687 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1688 .clksel = ssi_ssr_clksel,
1689 .flags = RATE_PROPAGATES,
1690 .clkdm_name = "core_l4_clkdm",
1691 .recalc = &omap2_clksel_recalc,
1694 static struct clk ssi_sst_fck = {
1695 .name = "ssi_sst_fck",
1696 .ops = &clkops_null,
1697 .parent = &ssi_ssr_fck,
1699 .recalc = &omap2_fixed_divisor_recalc,
1704 /* CORE_L3_ICK based clocks */
1707 * XXX must add clk_enable/clk_disable for these if standard code won't
1710 static struct clk core_l3_ick = {
1711 .name = "core_l3_ick",
1712 .ops = &clkops_null,
1714 .init = &omap2_init_clk_clkdm,
1715 .flags = RATE_PROPAGATES,
1716 .clkdm_name = "core_l3_clkdm",
1717 .recalc = &followparent_recalc,
1720 static struct clk hsotgusb_ick = {
1721 .name = "hsotgusb_ick",
1722 .ops = &clkops_omap2_dflt_wait,
1723 .parent = &core_l3_ick,
1724 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1725 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1726 .clkdm_name = "core_l3_clkdm",
1727 .recalc = &followparent_recalc,
1730 static struct clk sdrc_ick = {
1732 .ops = &clkops_omap2_dflt_wait,
1733 .parent = &core_l3_ick,
1734 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1735 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1736 .flags = ENABLE_ON_INIT,
1737 .clkdm_name = "core_l3_clkdm",
1738 .recalc = &followparent_recalc,
1741 static struct clk gpmc_fck = {
1743 .ops = &clkops_null,
1744 .parent = &core_l3_ick,
1745 .flags = ENABLE_ON_INIT, /* huh? */
1746 .clkdm_name = "core_l3_clkdm",
1747 .recalc = &followparent_recalc,
1750 /* SECURITY_L3_ICK based clocks */
1752 static struct clk security_l3_ick = {
1753 .name = "security_l3_ick",
1754 .ops = &clkops_null,
1756 .flags = RATE_PROPAGATES,
1757 .recalc = &followparent_recalc,
1760 static struct clk pka_ick = {
1762 .ops = &clkops_omap2_dflt_wait,
1763 .parent = &security_l3_ick,
1764 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1765 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1766 .recalc = &followparent_recalc,
1769 /* CORE_L4_ICK based clocks */
1771 static struct clk core_l4_ick = {
1772 .name = "core_l4_ick",
1773 .ops = &clkops_null,
1775 .init = &omap2_init_clk_clkdm,
1776 .flags = RATE_PROPAGATES,
1777 .clkdm_name = "core_l4_clkdm",
1778 .recalc = &followparent_recalc,
1781 static struct clk usbtll_ick = {
1782 .name = "usbtll_ick",
1783 .ops = &clkops_omap2_dflt_wait,
1784 .parent = &core_l4_ick,
1785 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1786 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1787 .clkdm_name = "core_l4_clkdm",
1788 .recalc = &followparent_recalc,
1791 static struct clk mmchs3_ick = {
1792 .name = "mmchs_ick",
1793 .ops = &clkops_omap2_dflt_wait,
1795 .parent = &core_l4_ick,
1796 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1797 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1798 .clkdm_name = "core_l4_clkdm",
1799 .recalc = &followparent_recalc,
1802 /* Intersystem Communication Registers - chassis mode only */
1803 static struct clk icr_ick = {
1805 .ops = &clkops_omap2_dflt_wait,
1806 .parent = &core_l4_ick,
1807 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1808 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1809 .clkdm_name = "core_l4_clkdm",
1810 .recalc = &followparent_recalc,
1813 static struct clk aes2_ick = {
1815 .ops = &clkops_omap2_dflt_wait,
1816 .parent = &core_l4_ick,
1817 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1818 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1819 .clkdm_name = "core_l4_clkdm",
1820 .recalc = &followparent_recalc,
1823 static struct clk sha12_ick = {
1824 .name = "sha12_ick",
1825 .ops = &clkops_omap2_dflt_wait,
1826 .parent = &core_l4_ick,
1827 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1828 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1829 .clkdm_name = "core_l4_clkdm",
1830 .recalc = &followparent_recalc,
1833 static struct clk des2_ick = {
1835 .ops = &clkops_omap2_dflt_wait,
1836 .parent = &core_l4_ick,
1837 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1838 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1839 .clkdm_name = "core_l4_clkdm",
1840 .recalc = &followparent_recalc,
1843 static struct clk mmchs2_ick = {
1844 .name = "mmchs_ick",
1845 .ops = &clkops_omap2_dflt_wait,
1847 .parent = &core_l4_ick,
1848 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1849 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1850 .clkdm_name = "core_l4_clkdm",
1851 .recalc = &followparent_recalc,
1854 static struct clk mmchs1_ick = {
1855 .name = "mmchs_ick",
1856 .ops = &clkops_omap2_dflt_wait,
1857 .parent = &core_l4_ick,
1858 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1859 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1860 .clkdm_name = "core_l4_clkdm",
1861 .recalc = &followparent_recalc,
1864 static struct clk mspro_ick = {
1865 .name = "mspro_ick",
1866 .ops = &clkops_omap2_dflt_wait,
1867 .parent = &core_l4_ick,
1868 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1869 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1870 .clkdm_name = "core_l4_clkdm",
1871 .recalc = &followparent_recalc,
1874 static struct clk hdq_ick = {
1876 .ops = &clkops_omap2_dflt_wait,
1877 .parent = &core_l4_ick,
1878 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1879 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1880 .clkdm_name = "core_l4_clkdm",
1881 .recalc = &followparent_recalc,
1884 static struct clk mcspi4_ick = {
1885 .name = "mcspi_ick",
1886 .ops = &clkops_omap2_dflt_wait,
1888 .parent = &core_l4_ick,
1889 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1890 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1891 .clkdm_name = "core_l4_clkdm",
1892 .recalc = &followparent_recalc,
1895 static struct clk mcspi3_ick = {
1896 .name = "mcspi_ick",
1897 .ops = &clkops_omap2_dflt_wait,
1899 .parent = &core_l4_ick,
1900 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1901 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1902 .clkdm_name = "core_l4_clkdm",
1903 .recalc = &followparent_recalc,
1906 static struct clk mcspi2_ick = {
1907 .name = "mcspi_ick",
1908 .ops = &clkops_omap2_dflt_wait,
1910 .parent = &core_l4_ick,
1911 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1912 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1913 .clkdm_name = "core_l4_clkdm",
1914 .recalc = &followparent_recalc,
1917 static struct clk mcspi1_ick = {
1918 .name = "mcspi_ick",
1919 .ops = &clkops_omap2_dflt_wait,
1921 .parent = &core_l4_ick,
1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1924 .clkdm_name = "core_l4_clkdm",
1925 .recalc = &followparent_recalc,
1928 static struct clk i2c3_ick = {
1930 .ops = &clkops_omap2_dflt_wait,
1932 .parent = &core_l4_ick,
1933 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1934 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1935 .clkdm_name = "core_l4_clkdm",
1936 .recalc = &followparent_recalc,
1939 static struct clk i2c2_ick = {
1941 .ops = &clkops_omap2_dflt_wait,
1943 .parent = &core_l4_ick,
1944 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1945 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1946 .clkdm_name = "core_l4_clkdm",
1947 .recalc = &followparent_recalc,
1950 static struct clk i2c1_ick = {
1952 .ops = &clkops_omap2_dflt_wait,
1954 .parent = &core_l4_ick,
1955 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1956 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1957 .clkdm_name = "core_l4_clkdm",
1958 .recalc = &followparent_recalc,
1961 static struct clk uart2_ick = {
1962 .name = "uart2_ick",
1963 .ops = &clkops_omap2_dflt_wait,
1964 .parent = &core_l4_ick,
1965 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1966 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1967 .clkdm_name = "core_l4_clkdm",
1968 .recalc = &followparent_recalc,
1971 static struct clk uart1_ick = {
1972 .name = "uart1_ick",
1973 .ops = &clkops_omap2_dflt_wait,
1974 .parent = &core_l4_ick,
1975 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1976 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1977 .clkdm_name = "core_l4_clkdm",
1978 .recalc = &followparent_recalc,
1981 static struct clk gpt11_ick = {
1982 .name = "gpt11_ick",
1983 .ops = &clkops_omap2_dflt_wait,
1984 .parent = &core_l4_ick,
1985 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1986 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1987 .clkdm_name = "core_l4_clkdm",
1988 .recalc = &followparent_recalc,
1991 static struct clk gpt10_ick = {
1992 .name = "gpt10_ick",
1993 .ops = &clkops_omap2_dflt_wait,
1994 .parent = &core_l4_ick,
1995 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1996 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1997 .clkdm_name = "core_l4_clkdm",
1998 .recalc = &followparent_recalc,
2001 static struct clk mcbsp5_ick = {
2002 .name = "mcbsp_ick",
2003 .ops = &clkops_omap2_dflt_wait,
2005 .parent = &core_l4_ick,
2006 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2007 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2008 .clkdm_name = "core_l4_clkdm",
2009 .recalc = &followparent_recalc,
2012 static struct clk mcbsp1_ick = {
2013 .name = "mcbsp_ick",
2014 .ops = &clkops_omap2_dflt_wait,
2016 .parent = &core_l4_ick,
2017 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2018 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2019 .clkdm_name = "core_l4_clkdm",
2020 .recalc = &followparent_recalc,
2023 static struct clk fac_ick = {
2025 .ops = &clkops_omap2_dflt_wait,
2026 .parent = &core_l4_ick,
2027 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2028 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2029 .clkdm_name = "core_l4_clkdm",
2030 .recalc = &followparent_recalc,
2033 static struct clk mailboxes_ick = {
2034 .name = "mailboxes_ick",
2035 .ops = &clkops_omap2_dflt_wait,
2036 .parent = &core_l4_ick,
2037 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2038 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2039 .clkdm_name = "core_l4_clkdm",
2040 .recalc = &followparent_recalc,
2043 static struct clk omapctrl_ick = {
2044 .name = "omapctrl_ick",
2045 .ops = &clkops_omap2_dflt_wait,
2046 .parent = &core_l4_ick,
2047 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2048 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2049 .flags = ENABLE_ON_INIT,
2050 .recalc = &followparent_recalc,
2053 /* SSI_L4_ICK based clocks */
2055 static struct clk ssi_l4_ick = {
2056 .name = "ssi_l4_ick",
2057 .ops = &clkops_null,
2059 .flags = RATE_PROPAGATES,
2060 .clkdm_name = "core_l4_clkdm",
2061 .recalc = &followparent_recalc,
2064 static struct clk ssi_ick = {
2066 .ops = &clkops_omap2_dflt,
2067 .parent = &ssi_l4_ick,
2068 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2069 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2070 .clkdm_name = "core_l4_clkdm",
2071 .recalc = &followparent_recalc,
2074 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2075 * but l4_ick makes more sense to me */
2077 static const struct clksel usb_l4_clksel[] = {
2078 { .parent = &l4_ick, .rates = div2_rates },
2082 static struct clk usb_l4_ick = {
2083 .name = "usb_l4_ick",
2084 .ops = &clkops_omap2_dflt_wait,
2086 .init = &omap2_init_clksel_parent,
2087 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2088 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2089 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2090 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2091 .clksel = usb_l4_clksel,
2092 .recalc = &omap2_clksel_recalc,
2095 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2097 /* SECURITY_L4_ICK2 based clocks */
2099 static struct clk security_l4_ick2 = {
2100 .name = "security_l4_ick2",
2101 .ops = &clkops_null,
2103 .flags = RATE_PROPAGATES,
2104 .recalc = &followparent_recalc,
2107 static struct clk aes1_ick = {
2109 .ops = &clkops_omap2_dflt_wait,
2110 .parent = &security_l4_ick2,
2111 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2112 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2113 .recalc = &followparent_recalc,
2116 static struct clk rng_ick = {
2118 .ops = &clkops_omap2_dflt_wait,
2119 .parent = &security_l4_ick2,
2120 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2121 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2122 .recalc = &followparent_recalc,
2125 static struct clk sha11_ick = {
2126 .name = "sha11_ick",
2127 .ops = &clkops_omap2_dflt_wait,
2128 .parent = &security_l4_ick2,
2129 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2130 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2131 .recalc = &followparent_recalc,
2134 static struct clk des1_ick = {
2136 .ops = &clkops_omap2_dflt_wait,
2137 .parent = &security_l4_ick2,
2138 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2139 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2140 .recalc = &followparent_recalc,
2144 static const struct clksel dss1_alwon_fck_clksel[] = {
2145 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2146 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2150 static struct clk dss1_alwon_fck = {
2151 .name = "dss1_alwon_fck",
2152 .ops = &clkops_omap2_dflt,
2153 .parent = &dpll4_m4x2_ck,
2154 .init = &omap2_init_clksel_parent,
2155 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2156 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2157 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2158 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2159 .clksel = dss1_alwon_fck_clksel,
2160 .clkdm_name = "dss_clkdm",
2161 .recalc = &omap2_clksel_recalc,
2164 static struct clk dss_tv_fck = {
2165 .name = "dss_tv_fck",
2166 .ops = &clkops_omap2_dflt,
2167 .parent = &omap_54m_fck,
2168 .init = &omap2_init_clk_clkdm,
2169 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2170 .enable_bit = OMAP3430_EN_TV_SHIFT,
2171 .clkdm_name = "dss_clkdm",
2172 .recalc = &followparent_recalc,
2175 static struct clk dss_96m_fck = {
2176 .name = "dss_96m_fck",
2177 .ops = &clkops_omap2_dflt,
2178 .parent = &omap_96m_fck,
2179 .init = &omap2_init_clk_clkdm,
2180 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2181 .enable_bit = OMAP3430_EN_TV_SHIFT,
2182 .clkdm_name = "dss_clkdm",
2183 .recalc = &followparent_recalc,
2186 static struct clk dss2_alwon_fck = {
2187 .name = "dss2_alwon_fck",
2188 .ops = &clkops_omap2_dflt,
2190 .init = &omap2_init_clk_clkdm,
2191 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2192 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2193 .clkdm_name = "dss_clkdm",
2194 .recalc = &followparent_recalc,
2197 static struct clk dss_ick = {
2198 /* Handles both L3 and L4 clocks */
2200 .ops = &clkops_omap2_dflt,
2202 .init = &omap2_init_clk_clkdm,
2203 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2204 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2205 .clkdm_name = "dss_clkdm",
2206 .recalc = &followparent_recalc,
2211 static const struct clksel cam_mclk_clksel[] = {
2212 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2213 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2217 static struct clk cam_mclk = {
2219 .ops = &clkops_omap2_dflt_wait,
2220 .parent = &dpll4_m5x2_ck,
2221 .init = &omap2_init_clksel_parent,
2222 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2223 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2224 .clksel = cam_mclk_clksel,
2225 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2226 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2227 .clkdm_name = "cam_clkdm",
2228 .recalc = &omap2_clksel_recalc,
2231 static struct clk cam_ick = {
2232 /* Handles both L3 and L4 clocks */
2234 .ops = &clkops_omap2_dflt_wait,
2236 .init = &omap2_init_clk_clkdm,
2237 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2238 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2239 .clkdm_name = "cam_clkdm",
2240 .recalc = &followparent_recalc,
2243 static struct clk csi2_96m_fck = {
2244 .name = "csi2_96m_fck",
2245 .ops = &clkops_omap2_dflt_wait,
2246 .parent = &core_96m_fck,
2247 .init = &omap2_init_clk_clkdm,
2248 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2249 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2250 .clkdm_name = "cam_clkdm",
2251 .recalc = &followparent_recalc,
2254 /* USBHOST - 3430ES2 only */
2256 static struct clk usbhost_120m_fck = {
2257 .name = "usbhost_120m_fck",
2258 .ops = &clkops_omap2_dflt_wait,
2259 .parent = &omap_120m_fck,
2260 .init = &omap2_init_clk_clkdm,
2261 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2262 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2263 .clkdm_name = "usbhost_clkdm",
2264 .recalc = &followparent_recalc,
2267 static struct clk usbhost_48m_fck = {
2268 .name = "usbhost_48m_fck",
2269 .ops = &clkops_omap2_dflt_wait,
2270 .parent = &omap_48m_fck,
2271 .init = &omap2_init_clk_clkdm,
2272 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2273 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2274 .clkdm_name = "usbhost_clkdm",
2275 .recalc = &followparent_recalc,
2278 static struct clk usbhost_ick = {
2279 /* Handles both L3 and L4 clocks */
2280 .name = "usbhost_ick",
2281 .ops = &clkops_omap2_dflt_wait,
2283 .init = &omap2_init_clk_clkdm,
2284 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2285 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2286 .clkdm_name = "usbhost_clkdm",
2287 .recalc = &followparent_recalc,
2292 static const struct clksel_rate usim_96m_rates[] = {
2293 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2294 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2295 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2296 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2300 static const struct clksel_rate usim_120m_rates[] = {
2301 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2302 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2303 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2304 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2308 static const struct clksel usim_clksel[] = {
2309 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2310 { .parent = &omap_120m_fck, .rates = usim_120m_rates },
2311 { .parent = &sys_ck, .rates = div2_rates },
2316 static struct clk usim_fck = {
2318 .ops = &clkops_omap2_dflt_wait,
2319 .init = &omap2_init_clksel_parent,
2320 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2321 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2322 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2323 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2324 .clksel = usim_clksel,
2325 .recalc = &omap2_clksel_recalc,
2328 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2329 static struct clk gpt1_fck = {
2331 .ops = &clkops_omap2_dflt_wait,
2332 .init = &omap2_init_clksel_parent,
2333 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2334 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2335 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2336 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2337 .clksel = omap343x_gpt_clksel,
2338 .clkdm_name = "wkup_clkdm",
2339 .recalc = &omap2_clksel_recalc,
2342 static struct clk wkup_32k_fck = {
2343 .name = "wkup_32k_fck",
2344 .ops = &clkops_null,
2345 .init = &omap2_init_clk_clkdm,
2346 .parent = &omap_32k_fck,
2347 .flags = RATE_PROPAGATES,
2348 .clkdm_name = "wkup_clkdm",
2349 .recalc = &followparent_recalc,
2352 static struct clk gpio1_dbck = {
2353 .name = "gpio1_dbck",
2354 .ops = &clkops_omap2_dflt_wait,
2355 .parent = &wkup_32k_fck,
2356 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2357 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2358 .clkdm_name = "wkup_clkdm",
2359 .recalc = &followparent_recalc,
2362 static struct clk wdt2_fck = {
2364 .ops = &clkops_omap2_dflt_wait,
2365 .parent = &wkup_32k_fck,
2366 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2367 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2368 .clkdm_name = "wkup_clkdm",
2369 .recalc = &followparent_recalc,
2372 static struct clk wkup_l4_ick = {
2373 .name = "wkup_l4_ick",
2374 .ops = &clkops_null,
2376 .flags = RATE_PROPAGATES,
2377 .clkdm_name = "wkup_clkdm",
2378 .recalc = &followparent_recalc,
2382 /* Never specifically named in the TRM, so we have to infer a likely name */
2383 static struct clk usim_ick = {
2385 .ops = &clkops_omap2_dflt_wait,
2386 .parent = &wkup_l4_ick,
2387 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2388 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2389 .clkdm_name = "wkup_clkdm",
2390 .recalc = &followparent_recalc,
2393 static struct clk wdt2_ick = {
2395 .ops = &clkops_omap2_dflt_wait,
2396 .parent = &wkup_l4_ick,
2397 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2398 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2399 .clkdm_name = "wkup_clkdm",
2400 .recalc = &followparent_recalc,
2403 static struct clk wdt1_ick = {
2405 .ops = &clkops_omap2_dflt_wait,
2406 .parent = &wkup_l4_ick,
2407 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2408 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2409 .clkdm_name = "wkup_clkdm",
2410 .recalc = &followparent_recalc,
2413 static struct clk gpio1_ick = {
2414 .name = "gpio1_ick",
2415 .ops = &clkops_omap2_dflt_wait,
2416 .parent = &wkup_l4_ick,
2417 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2418 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2419 .clkdm_name = "wkup_clkdm",
2420 .recalc = &followparent_recalc,
2423 static struct clk omap_32ksync_ick = {
2424 .name = "omap_32ksync_ick",
2425 .ops = &clkops_omap2_dflt_wait,
2426 .parent = &wkup_l4_ick,
2427 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2428 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2429 .clkdm_name = "wkup_clkdm",
2430 .recalc = &followparent_recalc,
2433 /* XXX This clock no longer exists in 3430 TRM rev F */
2434 static struct clk gpt12_ick = {
2435 .name = "gpt12_ick",
2436 .ops = &clkops_omap2_dflt_wait,
2437 .parent = &wkup_l4_ick,
2438 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2439 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2440 .clkdm_name = "wkup_clkdm",
2441 .recalc = &followparent_recalc,
2444 static struct clk gpt1_ick = {
2446 .ops = &clkops_omap2_dflt_wait,
2447 .parent = &wkup_l4_ick,
2448 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2449 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2450 .clkdm_name = "wkup_clkdm",
2451 .recalc = &followparent_recalc,
2456 /* PER clock domain */
2458 static struct clk per_96m_fck = {
2459 .name = "per_96m_fck",
2460 .ops = &clkops_null,
2461 .parent = &omap_96m_alwon_fck,
2462 .init = &omap2_init_clk_clkdm,
2463 .flags = RATE_PROPAGATES,
2464 .clkdm_name = "per_clkdm",
2465 .recalc = &followparent_recalc,
2468 static struct clk per_48m_fck = {
2469 .name = "per_48m_fck",
2470 .ops = &clkops_null,
2471 .parent = &omap_48m_fck,
2472 .init = &omap2_init_clk_clkdm,
2473 .flags = RATE_PROPAGATES,
2474 .clkdm_name = "per_clkdm",
2475 .recalc = &followparent_recalc,
2478 static struct clk uart3_fck = {
2479 .name = "uart3_fck",
2480 .ops = &clkops_omap2_dflt_wait,
2481 .parent = &per_48m_fck,
2482 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2483 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2484 .clkdm_name = "per_clkdm",
2485 .recalc = &followparent_recalc,
2488 static struct clk gpt2_fck = {
2490 .ops = &clkops_omap2_dflt_wait,
2491 .init = &omap2_init_clksel_parent,
2492 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2493 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2494 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2495 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2496 .clksel = omap343x_gpt_clksel,
2497 .clkdm_name = "per_clkdm",
2498 .recalc = &omap2_clksel_recalc,
2501 static struct clk gpt3_fck = {
2503 .ops = &clkops_omap2_dflt_wait,
2504 .init = &omap2_init_clksel_parent,
2505 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2506 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2507 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2508 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2509 .clksel = omap343x_gpt_clksel,
2510 .clkdm_name = "per_clkdm",
2511 .recalc = &omap2_clksel_recalc,
2514 static struct clk gpt4_fck = {
2516 .ops = &clkops_omap2_dflt_wait,
2517 .init = &omap2_init_clksel_parent,
2518 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2519 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2520 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2521 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2522 .clksel = omap343x_gpt_clksel,
2523 .clkdm_name = "per_clkdm",
2524 .recalc = &omap2_clksel_recalc,
2527 static struct clk gpt5_fck = {
2529 .ops = &clkops_omap2_dflt_wait,
2530 .init = &omap2_init_clksel_parent,
2531 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2532 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2533 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2534 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2535 .clksel = omap343x_gpt_clksel,
2536 .clkdm_name = "per_clkdm",
2537 .recalc = &omap2_clksel_recalc,
2540 static struct clk gpt6_fck = {
2542 .ops = &clkops_omap2_dflt_wait,
2543 .init = &omap2_init_clksel_parent,
2544 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2545 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2546 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2547 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2548 .clksel = omap343x_gpt_clksel,
2549 .clkdm_name = "per_clkdm",
2550 .recalc = &omap2_clksel_recalc,
2553 static struct clk gpt7_fck = {
2555 .ops = &clkops_omap2_dflt_wait,
2556 .init = &omap2_init_clksel_parent,
2557 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2558 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2559 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2560 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2561 .clksel = omap343x_gpt_clksel,
2562 .clkdm_name = "per_clkdm",
2563 .recalc = &omap2_clksel_recalc,
2566 static struct clk gpt8_fck = {
2568 .ops = &clkops_omap2_dflt_wait,
2569 .init = &omap2_init_clksel_parent,
2570 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2571 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2572 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2573 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2574 .clksel = omap343x_gpt_clksel,
2575 .clkdm_name = "per_clkdm",
2576 .recalc = &omap2_clksel_recalc,
2579 static struct clk gpt9_fck = {
2581 .ops = &clkops_omap2_dflt_wait,
2582 .init = &omap2_init_clksel_parent,
2583 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2584 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2585 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2586 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2587 .clksel = omap343x_gpt_clksel,
2588 .clkdm_name = "per_clkdm",
2589 .recalc = &omap2_clksel_recalc,
2592 static struct clk per_32k_alwon_fck = {
2593 .name = "per_32k_alwon_fck",
2594 .ops = &clkops_null,
2595 .parent = &omap_32k_fck,
2596 .clkdm_name = "per_clkdm",
2597 .flags = RATE_PROPAGATES,
2598 .recalc = &followparent_recalc,
2601 static struct clk gpio6_dbck = {
2602 .name = "gpio6_dbck",
2603 .ops = &clkops_omap2_dflt_wait,
2604 .parent = &per_32k_alwon_fck,
2605 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2606 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2607 .clkdm_name = "per_clkdm",
2608 .recalc = &followparent_recalc,
2611 static struct clk gpio5_dbck = {
2612 .name = "gpio5_dbck",
2613 .ops = &clkops_omap2_dflt_wait,
2614 .parent = &per_32k_alwon_fck,
2615 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2616 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2617 .clkdm_name = "per_clkdm",
2618 .recalc = &followparent_recalc,
2621 static struct clk gpio4_dbck = {
2622 .name = "gpio4_dbck",
2623 .ops = &clkops_omap2_dflt_wait,
2624 .parent = &per_32k_alwon_fck,
2625 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2626 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2627 .clkdm_name = "per_clkdm",
2628 .recalc = &followparent_recalc,
2631 static struct clk gpio3_dbck = {
2632 .name = "gpio3_dbck",
2633 .ops = &clkops_omap2_dflt_wait,
2634 .parent = &per_32k_alwon_fck,
2635 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2636 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2637 .clkdm_name = "per_clkdm",
2638 .recalc = &followparent_recalc,
2641 static struct clk gpio2_dbck = {
2642 .name = "gpio2_dbck",
2643 .ops = &clkops_omap2_dflt_wait,
2644 .parent = &per_32k_alwon_fck,
2645 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2646 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2647 .clkdm_name = "per_clkdm",
2648 .recalc = &followparent_recalc,
2651 static struct clk wdt3_fck = {
2653 .ops = &clkops_omap2_dflt_wait,
2654 .parent = &per_32k_alwon_fck,
2655 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2656 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2657 .clkdm_name = "per_clkdm",
2658 .recalc = &followparent_recalc,
2661 static struct clk per_l4_ick = {
2662 .name = "per_l4_ick",
2663 .ops = &clkops_null,
2665 .flags = RATE_PROPAGATES,
2666 .clkdm_name = "per_clkdm",
2667 .recalc = &followparent_recalc,
2670 static struct clk gpio6_ick = {
2671 .name = "gpio6_ick",
2672 .ops = &clkops_omap2_dflt_wait,
2673 .parent = &per_l4_ick,
2674 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2675 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2676 .clkdm_name = "per_clkdm",
2677 .recalc = &followparent_recalc,
2680 static struct clk gpio5_ick = {
2681 .name = "gpio5_ick",
2682 .ops = &clkops_omap2_dflt_wait,
2683 .parent = &per_l4_ick,
2684 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2685 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2686 .clkdm_name = "per_clkdm",
2687 .recalc = &followparent_recalc,
2690 static struct clk gpio4_ick = {
2691 .name = "gpio4_ick",
2692 .ops = &clkops_omap2_dflt_wait,
2693 .parent = &per_l4_ick,
2694 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2695 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2696 .clkdm_name = "per_clkdm",
2697 .recalc = &followparent_recalc,
2700 static struct clk gpio3_ick = {
2701 .name = "gpio3_ick",
2702 .ops = &clkops_omap2_dflt_wait,
2703 .parent = &per_l4_ick,
2704 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2705 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2706 .clkdm_name = "per_clkdm",
2707 .recalc = &followparent_recalc,
2710 static struct clk gpio2_ick = {
2711 .name = "gpio2_ick",
2712 .ops = &clkops_omap2_dflt_wait,
2713 .parent = &per_l4_ick,
2714 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2715 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2716 .clkdm_name = "per_clkdm",
2717 .recalc = &followparent_recalc,
2720 static struct clk wdt3_ick = {
2722 .ops = &clkops_omap2_dflt_wait,
2723 .parent = &per_l4_ick,
2724 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2725 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2726 .clkdm_name = "per_clkdm",
2727 .recalc = &followparent_recalc,
2730 static struct clk uart3_ick = {
2731 .name = "uart3_ick",
2732 .ops = &clkops_omap2_dflt_wait,
2733 .parent = &per_l4_ick,
2734 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2735 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2736 .clkdm_name = "per_clkdm",
2737 .recalc = &followparent_recalc,
2740 static struct clk gpt9_ick = {
2742 .ops = &clkops_omap2_dflt_wait,
2743 .parent = &per_l4_ick,
2744 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2745 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2746 .clkdm_name = "per_clkdm",
2747 .recalc = &followparent_recalc,
2750 static struct clk gpt8_ick = {
2752 .ops = &clkops_omap2_dflt_wait,
2753 .parent = &per_l4_ick,
2754 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2755 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2756 .clkdm_name = "per_clkdm",
2757 .recalc = &followparent_recalc,
2760 static struct clk gpt7_ick = {
2762 .ops = &clkops_omap2_dflt_wait,
2763 .parent = &per_l4_ick,
2764 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2765 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2766 .clkdm_name = "per_clkdm",
2767 .recalc = &followparent_recalc,
2770 static struct clk gpt6_ick = {
2772 .ops = &clkops_omap2_dflt_wait,
2773 .parent = &per_l4_ick,
2774 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2775 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2776 .clkdm_name = "per_clkdm",
2777 .recalc = &followparent_recalc,
2780 static struct clk gpt5_ick = {
2782 .ops = &clkops_omap2_dflt_wait,
2783 .parent = &per_l4_ick,
2784 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2785 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2786 .clkdm_name = "per_clkdm",
2787 .recalc = &followparent_recalc,
2790 static struct clk gpt4_ick = {
2792 .ops = &clkops_omap2_dflt_wait,
2793 .parent = &per_l4_ick,
2794 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2795 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2796 .clkdm_name = "per_clkdm",
2797 .recalc = &followparent_recalc,
2800 static struct clk gpt3_ick = {
2802 .ops = &clkops_omap2_dflt_wait,
2803 .parent = &per_l4_ick,
2804 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2805 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2806 .clkdm_name = "per_clkdm",
2807 .recalc = &followparent_recalc,
2810 static struct clk gpt2_ick = {
2812 .ops = &clkops_omap2_dflt_wait,
2813 .parent = &per_l4_ick,
2814 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2815 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2816 .clkdm_name = "per_clkdm",
2817 .recalc = &followparent_recalc,
2820 static struct clk mcbsp2_ick = {
2821 .name = "mcbsp_ick",
2822 .ops = &clkops_omap2_dflt_wait,
2824 .parent = &per_l4_ick,
2825 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2826 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2827 .clkdm_name = "per_clkdm",
2828 .recalc = &followparent_recalc,
2831 static struct clk mcbsp3_ick = {
2832 .name = "mcbsp_ick",
2833 .ops = &clkops_omap2_dflt_wait,
2835 .parent = &per_l4_ick,
2836 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2837 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2838 .clkdm_name = "per_clkdm",
2839 .recalc = &followparent_recalc,
2842 static struct clk mcbsp4_ick = {
2843 .name = "mcbsp_ick",
2844 .ops = &clkops_omap2_dflt_wait,
2846 .parent = &per_l4_ick,
2847 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2848 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2849 .clkdm_name = "per_clkdm",
2850 .recalc = &followparent_recalc,
2853 static const struct clksel mcbsp_234_clksel[] = {
2854 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2855 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2859 static struct clk mcbsp2_fck = {
2860 .name = "mcbsp_fck",
2861 .ops = &clkops_omap2_dflt_wait,
2863 .init = &omap2_init_clksel_parent,
2864 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2865 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2866 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2867 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2868 .clksel = mcbsp_234_clksel,
2869 .clkdm_name = "per_clkdm",
2870 .recalc = &omap2_clksel_recalc,
2873 static struct clk mcbsp3_fck = {
2874 .name = "mcbsp_fck",
2875 .ops = &clkops_omap2_dflt_wait,
2877 .init = &omap2_init_clksel_parent,
2878 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2879 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2880 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2881 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2882 .clksel = mcbsp_234_clksel,
2883 .clkdm_name = "per_clkdm",
2884 .recalc = &omap2_clksel_recalc,
2887 static struct clk mcbsp4_fck = {
2888 .name = "mcbsp_fck",
2889 .ops = &clkops_omap2_dflt_wait,
2891 .init = &omap2_init_clksel_parent,
2892 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2893 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2894 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2895 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2896 .clksel = mcbsp_234_clksel,
2897 .clkdm_name = "per_clkdm",
2898 .recalc = &omap2_clksel_recalc,
2903 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2905 static const struct clksel_rate emu_src_sys_rates[] = {
2906 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2910 static const struct clksel_rate emu_src_core_rates[] = {
2911 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2915 static const struct clksel_rate emu_src_per_rates[] = {
2916 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2920 static const struct clksel_rate emu_src_mpu_rates[] = {
2921 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2925 static const struct clksel emu_src_clksel[] = {
2926 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2927 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2928 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2929 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2934 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2935 * to switch the source of some of the EMU clocks.
2936 * XXX Are there CLKEN bits for these EMU clks?
2938 static struct clk emu_src_ck = {
2939 .name = "emu_src_ck",
2940 .ops = &clkops_null,
2941 .init = &omap2_init_clksel_parent,
2942 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2943 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2944 .clksel = emu_src_clksel,
2945 .flags = RATE_PROPAGATES,
2946 .clkdm_name = "emu_clkdm",
2947 .recalc = &omap2_clksel_recalc,
2950 static const struct clksel_rate pclk_emu_rates[] = {
2951 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2952 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2953 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2954 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2958 static const struct clksel pclk_emu_clksel[] = {
2959 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2963 static struct clk pclk_fck = {
2965 .ops = &clkops_null,
2966 .init = &omap2_init_clksel_parent,
2967 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2968 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2969 .clksel = pclk_emu_clksel,
2970 .flags = RATE_PROPAGATES,
2971 .clkdm_name = "emu_clkdm",
2972 .recalc = &omap2_clksel_recalc,
2975 static const struct clksel_rate pclkx2_emu_rates[] = {
2976 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2977 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2978 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2982 static const struct clksel pclkx2_emu_clksel[] = {
2983 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2987 static struct clk pclkx2_fck = {
2988 .name = "pclkx2_fck",
2989 .ops = &clkops_null,
2990 .init = &omap2_init_clksel_parent,
2991 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2992 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2993 .clksel = pclkx2_emu_clksel,
2994 .flags = RATE_PROPAGATES,
2995 .clkdm_name = "emu_clkdm",
2996 .recalc = &omap2_clksel_recalc,
2999 static const struct clksel atclk_emu_clksel[] = {
3000 { .parent = &emu_src_ck, .rates = div2_rates },
3004 static struct clk atclk_fck = {
3005 .name = "atclk_fck",
3006 .ops = &clkops_null,
3007 .init = &omap2_init_clksel_parent,
3008 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3009 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3010 .clksel = atclk_emu_clksel,
3011 .flags = RATE_PROPAGATES,
3012 .clkdm_name = "emu_clkdm",
3013 .recalc = &omap2_clksel_recalc,
3016 static struct clk traceclk_src_fck = {
3017 .name = "traceclk_src_fck",
3018 .ops = &clkops_null,
3019 .init = &omap2_init_clksel_parent,
3020 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3021 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3022 .clksel = emu_src_clksel,
3023 .flags = RATE_PROPAGATES,
3024 .clkdm_name = "emu_clkdm",
3025 .recalc = &omap2_clksel_recalc,
3028 static const struct clksel_rate traceclk_rates[] = {
3029 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3030 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3031 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3035 static const struct clksel traceclk_clksel[] = {
3036 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3040 static struct clk traceclk_fck = {
3041 .name = "traceclk_fck",
3042 .ops = &clkops_null,
3043 .init = &omap2_init_clksel_parent,
3044 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3045 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3046 .clksel = traceclk_clksel,
3047 .clkdm_name = "emu_clkdm",
3048 .recalc = &omap2_clksel_recalc,
3053 /* SmartReflex fclk (VDD1) */
3054 static struct clk sr1_fck = {
3056 .ops = &clkops_omap2_dflt_wait,
3058 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3059 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3060 .flags = RATE_PROPAGATES,
3061 .recalc = &followparent_recalc,
3064 /* SmartReflex fclk (VDD2) */
3065 static struct clk sr2_fck = {
3067 .ops = &clkops_omap2_dflt_wait,
3069 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3070 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3071 .flags = RATE_PROPAGATES,
3072 .recalc = &followparent_recalc,
3075 static struct clk sr_l4_ick = {
3076 .name = "sr_l4_ick",
3077 .ops = &clkops_null, /* RMK: missing? */
3079 .clkdm_name = "core_l4_clkdm",
3080 .recalc = &followparent_recalc,
3083 /* SECURE_32K_FCK clocks */
3085 /* XXX This clock no longer exists in 3430 TRM rev F */
3086 static struct clk gpt12_fck = {
3087 .name = "gpt12_fck",
3088 .ops = &clkops_null,
3089 .parent = &secure_32k_fck,
3090 .recalc = &followparent_recalc,
3093 static struct clk wdt1_fck = {
3095 .ops = &clkops_null,
3096 .parent = &secure_32k_fck,
3097 .recalc = &followparent_recalc,