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(parent: 5c0ec88) | patch
OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4
authorPaul Walmsley <paul@pwsan.com>
Tue, 24 Jun 2008 07:12:35 +0000 (01:12 -0600)
committerTony Lindgren <tony@atomide.com>
Thu, 26 Jun 2008 13:50:41 +0000 (16:50 +0300)
commit050684c18f2ea0b08fdd5233a0cd3c7f96e00a0e
tree4798e46b82dcad0f13de109d0eefbb75d45903a2tree | snapshot
parent5c0ec88a2145cdf2f2c9cc5fae49635c4c2476c7commit | diff
OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4

OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and
DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this
into the OMAP3 clock framework.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/mach-omap2/clock34xx.h diff | blob | history
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