- /* Covers most of the cases - a few exceptions are below */
- other_bit = 1 << clk->enable_bit;
- idlest_bit = other_bit;
-
- /* 24xx: DSS and CAM have no idlest bits for their target agents */
- if (cpu_is_omap24xx() && clk->prcm_mod == CORE_MOD &&
- (clk->enable_reg == CM_FCLKEN1 || clk->enable_reg == CM_ICLKEN1)) {
-
- if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
- clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
- clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
- return;
-
- }
-
- /* REVISIT: What are the appropriate exclusions for 34XX? */
- if (cpu_is_omap34xx()) {
-
- /* SSI */
- if (clk->prcm_mod == CORE_MOD &&
- (clk->enable_reg == CM_FCLKEN1 ||
- clk->enable_reg == CM_ICLKEN1) &&
- clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
-
- if (system_rev == OMAP3430_REV_ES1_0)
- return;
-
- idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
- }
-
- /* DSS */
- if (clk->prcm_mod == OMAP3430_DSS_MOD) {
-
- /* 3430ES1 DSS has no target idlest bits */
- if (system_rev == OMAP3430_REV_ES1_0)
- return;
-
- /*
- * For 3430ES2+ DSS, only wait once (dss1_alwon_fclk,
- * dss_l3_iclk, dss_l4_iclk) are enabled
- */
- if (clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
- return;
-
- idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
- }
-
- /* USBHOST */
- if (system_rev > OMAP3430_REV_ES1_0 &&
- clk->prcm_mod == OMAP3430ES2_USBHOST_MOD) {
-
- /*
- * The 120MHz clock apparently has nothing to do with
- * USBHOST module accessibility
- */
- if (clk->enable_bit == OMAP3430ES2_EN_USBHOST2_SHIFT)
- return;
-
- idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT;
-
- }
- }
-
- /* Check if both functional and interface clocks are running. */