+/*
+ * Timings are taken from smsc-lan91c96-ms.pdf
+ */
+static int smc91x_init_gpmc(int cs)
+{
+ struct gpmc_timings t;
+ const int t2_r = 45; /* t2 in Figure 12.10 */
+ const int t2_w = 30; /* t2 in Figure 12.11 */
+ const int t3 = 15; /* t3 in Figure 12.10 */
+ const int t5_r = 0; /* t5 in Figure 12.10 */
+ const int t6_r = 45; /* t6 in Figure 12.10 */
+ const int t6_w = 0; /* t6 in Figure 12.11 */
+ const int t7_w = 15; /* t7 in Figure 12.11 */
+ const int t15 = 12; /* t15 in Figure 12.2 */
+ const int t20 = 185; /* t20 in Figure 12.2 */
+
+ memset(&t, 0, sizeof(t));
+
+ t.cs_on = t15;
+ t.cs_rd_off = t3 + t2_r + t5_r; /* Figure 12.10 */
+ t.cs_wr_off = t3 + t2_w + t6_w; /* Figure 12.11 */
+ t.adv_on = t3; /* Figure 12.10 */
+ t.adv_rd_off = t3 + t2_r; /* Figure 12.10 */
+ t.adv_wr_off = t3 + t2_w; /* Figure 12.11 */
+ t.oe_off = t3 + t2_r + t5_r; /* Figure 12.10 */
+ t.oe_on = t.oe_off - t6_r; /* Figure 12.10 */
+ t.we_off = t3 + t2_w + t6_w; /* Figure 12.11 */
+ t.we_on = t.we_off - t7_w; /* Figure 12.11 */
+ t.rd_cycle = t20; /* Figure 12.2 */
+ t.wr_cycle = t20; /* Figure 12.4 */
+ t.access = t3 + t2_r + t5_r; /* Figure 12.10 */
+ t.wr_access = t3 + t2_w + t6_w; /* Figure 12.11 */
+
+ gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, GPMC_CONFIG1_DEVICESIZE_16);
+
+ return gpmc_cs_set_timings(cs, &t);
+}
+