[ARM] 4392/2: Do not corrupt the SP register in compressed/head.S

ARMv7 support code requires a valid stack for saving/restoring
registers as the whole D-cache flushing function is more complex. This
patch ensures that the SP register is not corrupted.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 2568d311be215a7301bc752f4813a9e64e866999..23348e9561b92070406f4d40a7a5060190561e6e 100644 (file)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -247,7 +247,7 @@ not_relocated:      mov     r0, #0
                mov     r3, r7
                bl      decompress_kernel
 
-               add     r0, r0, #127
+               add     r0, r0, #127 + 128      @ alignment + stack
                bic     r0, r0, #127            @ align the kernel length
 /*
  * r0     = decompressed kernel length
@@ -269,6 +269,7 @@ not_relocated:      mov     r0, #0
                stmia   r1!, {r9 - r14}
                cmp     r2, r3
                blo     1b
+               add     sp, r1, #128            @ relocate the stack
 
                bl      cache_clean_flush
                add     pc, r5, r0              @ call relocation code
@@ -476,6 +477,7 @@ __common_mmu_cache_on:
  */
                .align  5
 reloc_start:   add     r9, r5, r0
+               sub     r9, r9, #128            @ do not copy the stack
                debug_reloc_start
                mov     r1, r4
 1:
@@ -486,6 +488,7 @@ reloc_start:        add     r9, r5, r0
 
                cmp     r5, r9
                blo     1b
+               add     sp, r1, #128            @ relocate the stack
                debug_reloc_end
 
 call_kernel:   bl      cache_clean_flush