{
u32 field_mask, field_val, validrate, new_div = 0;
void __iomem *div_addr;
+ u32 v;
validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
if (validrate != rate)
if (field_val == ~0)
return -EINVAL;
- cm_rmw_reg_bits(field_mask, field_val << __ffs(field_mask), div_addr);
+ v = __raw_readl(div_addr);
+ v &= ~field_mask;
+ v |= field_val << __ffs(field_mask);
+ __raw_writel(v, div_addr);
wmb();
static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
{
const struct dpll_data *dd;
+ u32 v;
dd = clk->dpll_data;
- cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask),
- dd->control_reg);
+ v = __raw_readl(dd->control_reg);
+ v &= ~dd->enable_mask;
+ v |= clken_bits << __ffs(dd->enable_mask);
+ __raw_writel(v, dd->control_reg);
}
/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
static void omap3_dpll_allow_idle(struct clk *clk)
{
const struct dpll_data *dd;
+ u32 v;
if (!clk || !clk->dpll_data)
return;
* by writing 0x5 instead of 0x1. Add some mechanism to
* optionally enter this mode.
*/
- cm_rmw_reg_bits(dd->autoidle_mask,
- DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask),
- dd->autoidle_reg);
+ v = __raw_readl(dd->autoidle_reg);
+ v &= ~dd->autoidle_mask;
+ v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
+ __raw_writel(v, dd->autoidle_reg);
}
/**
static void omap3_dpll_deny_idle(struct clk *clk)
{
const struct dpll_data *dd;
+ u32 v;
if (!clk || !clk->dpll_data)
return;
dd = clk->dpll_data;
- cm_rmw_reg_bits(dd->autoidle_mask,
- DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask),
- dd->autoidle_reg);
+ v = __raw_readl(dd->autoidle_reg);
+ v &= ~dd->autoidle_mask;
+ v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
+ __raw_writel(v, dd->autoidle_reg);
}
/* Clock control for DPLL outputs */
#define OMAP3430_CM_CLKOUT_CTRL \
OMAP34XX_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
-#ifndef __ASSEMBLER__
-
-/* Read-modify-write bits in a CM register */
-static inline u32 cm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *va)
-{
- u32 v;
-
- v = __raw_readl(va);
- v &= ~mask;
- v |= bits;
- __raw_writel(v, va);
-
- return v;
-}
-
-#endif
-
/*
* Module specific CM registers from CM_BASE + domain offset
* Use cm_{read,write}_mod_reg() with these registers.