[ARM] OMAP3 powerdomains: make USBTLL SAR only available on ES3.1 and beyond

Richard Woodruff writes that chip errata prevent USBTLL SAR from working
on OMAP3 ES levels before ES3.1:

http://marc.info/?l=linux-arm-kernel&m=123319614808833&w=2

Update the OMAP3 powerdomain structures appropriately.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
index 1329443f2cd517f022d370701ba3a00f234c92ba..691470ea4c6a860f6ca8cd7df3fd4659916e1c76 100644 (file)
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -171,7 +171,8 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
        &iva2_pwrdm,
        &mpu_34xx_pwrdm,
        &neon_pwrdm,
-       &core_34xx_pwrdm,
+       &core_34xx_pre_es3_1_pwrdm,
+       &core_34xx_es3_1_pwrdm,
        &cam_pwrdm,
        &dss_pwrdm,
        &per_pwrdm,

diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index 78acfce8bbdcaeaf0cad400376fac7a1b324cc09..4dcf94b800ab732c2aade542ad699c9d63eef180 100644 (file)
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -200,12 +200,33 @@ static struct powerdomain mpu_34xx_pwrdm = {
 };
 
 /* No wkdeps or sleepdeps for 34xx core apparently */
-static struct powerdomain core_34xx_pwrdm = {
+static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
        .name             = "core_pwrdm",
        .prcm_offs        = CORE_MOD,
-       .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+       .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
+                                          CHIP_IS_OMAP3430ES2 |
+                                          CHIP_IS_OMAP3430ES3_0),
+       .pwrsts           = PWRSTS_OFF_RET_ON,
+       .dep_bit          = OMAP3430_EN_CORE_SHIFT,
+       .banks            = 2,
+       .pwrsts_mem_ret   = {
+               [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
+               [1] = PWRSTS_OFF_RET,    /* MEM2RETSTATE */
+       },
+       .pwrsts_mem_on    = {
+               [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
+               [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
+       },
+};
+
+/* No wkdeps or sleepdeps for 34xx core apparently */
+static struct powerdomain core_34xx_es3_1_pwrdm = {
+       .name             = "core_pwrdm",
+       .prcm_offs        = CORE_MOD,
+       .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .dep_bit          = OMAP3430_EN_CORE_SHIFT,
+       .flags            = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
        .banks            = 2,
        .pwrsts_mem_ret   = {
                [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */