[BNX2]: Add write posting comment.

Add comment to explain why we cannot read back after chip reset
before delaying.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 00918602ba88a8d00a85c1d17fdf20fb2a7970f4..854d80c330ec8ab4449bddb23a1af1bf43927f0c 100644 (file)
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -3934,6 +3934,10 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
                /* Chip reset. */
                REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
 
+               /* Reading back any register after chip reset will hang the
+                * bus on 5706 A0 and A1.  The msleep below provides plenty
+                * of margin for write posting.
+                */
                if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
                    (CHIP_ID(bp) == CHIP_ID_5706_A1))
                        msleep(20);