[ARM] 4487/1: ns9xxx: complete definition of GPIO related registers

I changed the naming to be more obvious---unfortunately the HRM
doesn't specify these.

Moreover the numbering is changed to be zero indexed as this is more
natural.

Adjust all callers.

Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
index 6eee8084b613b5fdc43d36070f458b7cfa542ad8..925048e7adfe9c9d048a14cb9914562e8e11cc49 100644 (file)
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -91,7 +91,7 @@ void __init board_a9m9750dev_init_irq(void)
         * use GPIO 11, because GPIO 32 is used for the LCD
         */
        /* XXX: proper GPIO handling */
-       BBU_GC(2) &= ~0x2000;
+       BBU_GCONFb1(1) &= ~0x2000;
 
        for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
                set_irq_chip(i, &a9m9750dev_fpga_chip);
@@ -196,4 +196,3 @@ void __init board_a9m9750dev_init_machine(void)
        platform_add_devices(board_a9m9750dev_devices,
                        ARRAY_SIZE(board_a9m9750dev_devices));
 }
-

diff --git a/include/asm-arm/arch-ns9xxx/regs-bbu.h b/include/asm-arm/arch-ns9xxx/regs-bbu.h
index e26269546240320706d98e9c46d0a27cbb5c7add..7ee194dc6354708784a750b44a71ec6da92a9659 100644 (file)
--- a/include/asm-arm/arch-ns9xxx/regs-bbu.h
+++ b/include/asm-arm/arch-ns9xxx/regs-bbu.h
@@ -15,7 +15,31 @@
 
 /* BBus Utility */
 
-/* GPIO Configuration Register */
-#define BBU_GC(x)      __REG2(0x9060000c, (x))
+/* GPIO Configuration Registers block 1 */
+/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is
+ * at 0 for each block.  That is, BBU_GCONFb1(0) is GPIO Configuration Register
+ * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */
+#define BBU_GCONFb1(x) __REG2(0x90600010, (x))
+#define BBU_GCONFb2(x) __REG2(0x90600100, (x))
+
+#define BBU_GCONFx_DIR(m)      __REGBIT(3 + (((m) & 7) << 2))
+#define BBU_GCONFx_DIR_INPUT(m)        __REGVAL(BBU_GCONFx_DIR(m), 0)
+#define BBU_GCONFx_DIR_OUTPUT(m)       __REGVAL(BBU_GCONFx_DIR(m), 1)
+#define BBU_GCONFx_INV(m)      __REGBIT(2 + (((m) & 7) << 2))
+#define BBU_GCONFx_INV_NO(m)           __REGVAL(BBU_GCONFx_INV(m), 0)
+#define BBU_GCONFx_INV_YES(m)          __REGVAL(BBU_GCONFx_INV(m), 1)
+#define BBU_GCONFx_FUNC(m)     __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2)
+#define BBU_GCONFx_FUNC_0(m)           __REGVAL(BBU_GCONFx_FUNC(m), 0)
+#define BBU_GCONFx_FUNC_1(m)           __REGVAL(BBU_GCONFx_FUNC(m), 1)
+#define BBU_GCONFx_FUNC_2(m)           __REGVAL(BBU_GCONFx_FUNC(m), 2)
+#define BBU_GCONFx_FUNC_3(m)           __REGVAL(BBU_GCONFx_FUNC(m), 3)
+
+#define BBU_GCTRL1     __REG(0x90600030)
+#define BBU_GCTRL2     __REG(0x90600034)
+#define BBU_GCTRL3     __REG(0x90600120)
+
+#define BBU_GSTAT1     __REG(0x90600040)
+#define BBU_GSTAT2     __REG(0x90600044)
+#define BBU_GSTAT3     __REG(0x90600130)
 
 #endif /* ifndef __ASM_ARCH_REGSBBU_H */