{
int retval;
- retval = omap1_clk_use(&api_ck.clk);
+ retval = omap1_clk_enable(&api_ck.clk);
if (!retval) {
- retval = omap1_clk_enable(clk);
- omap1_clk_unuse(&api_ck.clk);
+ retval = omap1_clk_enable_generic(clk);
+ omap1_clk_disable(&api_ck.clk);
}
return retval;
static void omap1_clk_disable_dsp_domain(struct clk *clk)
{
- if (omap1_clk_use(&api_ck.clk) == 0) {
- omap1_clk_disable(clk);
- omap1_clk_unuse(&api_ck.clk);
+ if (omap1_clk_enable(&api_ck.clk) == 0) {
+ omap1_clk_disable_generic(clk);
+ omap1_clk_disable(&api_ck.clk);
}
}
int ret;
struct uart_clk *uclk;
- ret = omap1_clk_enable(clk);
+ ret = omap1_clk_enable_generic(clk);
if (ret == 0) {
/* Set smart idle acknowledgement mode */
uclk = (struct uart_clk *)clk;
uclk = (struct uart_clk *)clk;
omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
- omap1_clk_disable(clk);
+ omap1_clk_disable_generic(clk);
}
static void omap1_clk_allow_idle(struct clk *clk)
* Note that DSP_CKCTL virt addr = phys addr, so
* we must use __raw_readw() instead of omap_readw().
*/
- omap1_clk_use(&api_ck.clk);
+ omap1_clk_enable(&api_ck.clk);
dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
- omap1_clk_unuse(&api_ck.clk);
+ omap1_clk_disable(&api_ck.clk);
if (unlikely(clk->rate == clk->parent->rate / dsor))
return; /* No change, quick exit */
clk-> rate = 96000000 / dsor;
}
-static int omap1_clk_use(struct clk *clk)
+static int omap1_clk_enable(struct clk *clk)
{
int ret = 0;
if (clk->usecount++ == 0) {
if (likely(clk->parent)) {
- ret = omap1_clk_use(clk->parent);
+ ret = omap1_clk_enable(clk->parent);
if (unlikely(ret != 0)) {
clk->usecount--;
ret = clk->enable(clk);
if (unlikely(ret != 0) && clk->parent) {
- omap1_clk_unuse(clk->parent);
+ omap1_clk_disable(clk->parent);
clk->usecount--;
}
}
return ret;
}
-static void omap1_clk_unuse(struct clk *clk)
+static void omap1_clk_disable(struct clk *clk)
{
if (clk->usecount > 0 && !(--clk->usecount)) {
clk->disable(clk);
if (likely(clk->parent)) {
- omap1_clk_unuse(clk->parent);
+ omap1_clk_disable(clk->parent);
if (clk->flags & CLOCK_NO_IDLE_PARENT)
if (!cpu_is_omap24xx())
omap1_clk_allow_idle(clk->parent);
}
}
-static int omap1_clk_enable(struct clk *clk)
+static int omap1_clk_enable_generic(struct clk *clk)
{
__u16 regval16;
__u32 regval32;
return 0;
}
-static void omap1_clk_disable(struct clk *clk)
+static void omap1_clk_disable_generic(struct clk *clk)
{
__u16 regval16;
__u32 regval32;
#endif
static struct clk_functions omap1_clk_functions = {
- .clk_use = omap1_clk_use,
- .clk_unuse = omap1_clk_unuse,
+ .clk_enable = omap1_clk_enable,
+ .clk_disable = omap1_clk_disable,
.clk_round_rate = omap1_clk_round_rate,
.clk_set_rate = omap1_clk_set_rate,
};
* Only enable those clocks we will need, let the drivers
* enable other clocks as necessary
*/
- clk_use(&armper_ck.clk);
- clk_use(&armxor_ck.clk);
- clk_use(&armtim_ck.clk); /* This should be done by timer code */
+ clk_enable(&armper_ck.clk);
+ clk_enable(&armxor_ck.clk);
+ clk_enable(&armtim_ck.clk); /* This should be done by timer code */
if (cpu_is_omap1510())
clk_enable(&arm_gpio_ck);
#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
-static int omap1_clk_enable(struct clk * clk);
-static void omap1_clk_disable(struct clk * clk);
+static int omap1_clk_enable_generic(struct clk * clk);
+static void omap1_clk_disable_generic(struct clk * clk);
static void omap1_ckctl_recalc(struct clk * clk);
static void omap1_watchdog_recalc(struct clk * clk);
static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
static void omap1_init_ext_clk(struct clk * clk);
static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
-static int omap1_clk_use(struct clk *clk);
-static void omap1_clk_unuse(struct clk *clk);
+static int omap1_clk_enable(struct clk *clk);
+static void omap1_clk_disable(struct clk *clk);
struct mpu_rate {
unsigned long rate;
.rate = 12000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
ALWAYS_ENABLED,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk ck_dpll1 = {
.parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_PROPAGATES | ALWAYS_ENABLED,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct arm_idlect1_clk ck_dpll1out = {
.enable_reg = (void __iomem *)ARM_IDLECT2,
.enable_bit = EN_CKOUT_ARM,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
},
.idlect_shift = 12,
};
RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
.rate_offset = CKCTL_ARMDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct arm_idlect1_clk armper_ck = {
.enable_bit = EN_PERCK,
.rate_offset = CKCTL_PERDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
},
.idlect_shift = 2,
};
.enable_reg = (void __iomem *)ARM_IDLECT2,
.enable_bit = EN_GPIOCK,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct arm_idlect1_clk armxor_ck = {
.enable_reg = (void __iomem *)ARM_IDLECT2,
.enable_bit = EN_XORPCK,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
},
.idlect_shift = 1,
};
.enable_reg = (void __iomem *)ARM_IDLECT2,
.enable_bit = EN_TIMCK,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
},
.idlect_shift = 9,
};
.enable_reg = (void __iomem *)ARM_IDLECT2,
.enable_bit = EN_WDTCK,
.recalc = &omap1_watchdog_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
},
.idlect_shift = 0,
};
*
* 1510 version is in TC clocks.
*/
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk dsp_ck = {
.enable_bit = EN_DSPCK,
.rate_offset = CKCTL_DSPDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk dspmmu_ck = {
RATE_CKCTL | ALWAYS_ENABLED,
.rate_offset = CKCTL_DSPMMUDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk dspper_ck = {
CLOCK_IDLE_CONTROL,
.rate_offset = CKCTL_TCDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
},
.idlect_shift = 6,
};
*
* 16xx version is in MPU clocks.
*/
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk tipb_ck = {
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk l3_ocpi_ck = {
.enable_reg = (void __iomem *)ARM_IDLECT3,
.enable_bit = EN_OCPI_CK,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk tc1_ck = {
.enable_reg = (void __iomem *)ARM_IDLECT3,
.enable_bit = EN_TC1_CK,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk tc2_ck = {
.enable_reg = (void __iomem *)ARM_IDLECT3,
.enable_bit = EN_TC2_CK,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk dma_ck = {
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
ALWAYS_ENABLED,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk dma_lcdfree_ck = {
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct arm_idlect1_clk api_ck = {
.enable_reg = (void __iomem *)ARM_IDLECT2,
.enable_bit = EN_APICK,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
},
.idlect_shift = 8,
};
.enable_reg = (void __iomem *)ARM_IDLECT2,
.enable_bit = EN_LBCK,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
},
.idlect_shift = 4,
};
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk rhea2_ck = {
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
.recalc = &followparent_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk lcd_ck_16xx = {
.enable_bit = EN_LCDCK,
.rate_offset = CKCTL_LCDDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct arm_idlect1_clk lcd_ck_1510 = {
.enable_bit = EN_LCDCK,
.rate_offset = CKCTL_LCDDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
},
.idlect_shift = 3,
};
.enable_bit = 29, /* Chooses between 12MHz and 48MHz */
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct uart_clk uart1_16xx = {
.enable_bit = 30, /* Chooses between 12MHz and 48MHz */
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk uart3_1510 = {
.enable_bit = 31, /* Chooses between 12MHz and 48MHz */
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct uart_clk uart3_16xx = {
RATE_FIXED | ENABLE_REG_32BIT,
.enable_reg = (void __iomem *)ULPD_CLOCK_CTRL,
.enable_bit = USB_MCLK_EN_BIT,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk usb_hhc_ck1510 = {
RATE_FIXED | ENABLE_REG_32BIT,
.enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
.enable_bit = USB_HOST_HHC_UHOST_EN,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk usb_hhc_ck16xx = {
RATE_FIXED | ENABLE_REG_32BIT,
.enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
.enable_bit = 8 /* UHOST_EN */,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk usb_dc_ck = {
.flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
.enable_reg = (void __iomem *)SOFT_REQ_REG,
.enable_bit = 4,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk mclk_1510 = {
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.rate = 12000000,
.flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk mclk_16xx = {
.set_rate = &omap1_set_ext_clk_rate,
.round_rate = &omap1_round_ext_clk_rate,
.init = &omap1_init_ext_clk,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk bclk_1510 = {
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.rate = 12000000,
.flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk bclk_16xx = {
.set_rate = &omap1_set_ext_clk_rate,
.round_rate = &omap1_round_ext_clk_rate,
.init = &omap1_init_ext_clk,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk mmc1_ck = {
RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
.enable_bit = 23,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk mmc2_ck = {
RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
.enable_bit = 20,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk virtual_ck_mpu = {
.recalc = &followparent_recalc,
.set_rate = &omap1_select_table_rate,
.round_rate = &omap1_round_to_table_rate,
- .enable = &omap1_clk_enable,
- .disable = &omap1_clk_disable,
+ .enable = &omap1_clk_enable_generic,
+ .disable = &omap1_clk_disable_generic,
};
static struct clk * onchip_clks[] = {
if (IS_ERR(uart1_ck))
printk("Could not get uart1_ck\n");
else {
- clk_use(uart1_ck);
+ clk_enable(uart1_ck);
if (cpu_is_omap1510())
clk_set_rate(uart1_ck, 12000000);
}
if (IS_ERR(uart2_ck))
printk("Could not get uart2_ck\n");
else {
- clk_use(uart2_ck);
+ clk_enable(uart2_ck);
if (cpu_is_omap1510())
clk_set_rate(uart2_ck, 12000000);
else
if (IS_ERR(uart3_ck))
printk("Could not get uart3_ck\n");
else {
- clk_use(uart3_ck);
+ clk_enable(uart3_ck);
if (cpu_is_omap1510())
clk_set_rate(uart3_ck, 12000000);
}
/* Enables clock without considering parent dependencies or use count
* REVISIT: Maybe change this to use clk->enable like on omap1?
*/
-static int omap2_clk_enable(struct clk * clk)
+static int _omap2_clk_enable(struct clk * clk)
{
u32 regval32;
}
/* Disables clock without considering parent dependencies or use count */
-static void omap2_clk_disable(struct clk *clk)
+static void _omap2_clk_disable(struct clk *clk)
{
u32 regval32;
__raw_writel(regval32, clk->enable_reg);
}
-static int omap2_clk_use(struct clk *clk)
+static int omap2_clk_enable(struct clk *clk)
{
int ret = 0;
if (clk->usecount++ == 0) {
if (likely((u32)clk->parent))
- ret = omap2_clk_use(clk->parent);
+ ret = omap2_clk_enable(clk->parent);
if (unlikely(ret != 0)) {
clk->usecount--;
return ret;
}
- ret = omap2_clk_enable(clk);
+ ret = _omap2_clk_enable(clk);
if (unlikely(ret != 0) && clk->parent) {
- omap2_clk_unuse(clk->parent);
+ omap2_clk_disable(clk->parent);
clk->usecount--;
}
}
return ret;
}
-static void omap2_clk_unuse(struct clk *clk)
+static void omap2_clk_disable(struct clk *clk)
{
if (clk->usecount > 0 && !(--clk->usecount)) {
- omap2_clk_disable(clk);
+ _omap2_clk_disable(clk);
if (likely((u32)clk->parent))
- omap2_clk_unuse(clk->parent);
+ omap2_clk_disable(clk->parent);
}
}
reg = (void __iomem *)src_sel;
if (clk->usecount > 0)
- omap2_clk_disable(clk);
+ _omap2_clk_disable(clk);
/* Set new source value (previous dividers if any in effect) */
reg_val = __raw_readl(reg) & ~(field_mask << src_off);
__raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
if (clk->usecount > 0)
- omap2_clk_enable(clk);
+ _omap2_clk_enable(clk);
clk->parent = new_parent;
static struct clk_functions omap2_clk_functions = {
.clk_enable = omap2_clk_enable,
.clk_disable = omap2_clk_disable,
- .clk_use = omap2_clk_use,
- .clk_unuse = omap2_clk_unuse,
.clk_round_rate = omap2_clk_round_rate,
.clk_set_rate = omap2_clk_set_rate,
.clk_set_parent = omap2_clk_set_parent,
continue;
printk(KERN_INFO "Disabling unused clock \"%s\"\n", ck->name);
- omap2_clk_disable(ck);
+ _omap2_clk_disable(ck);
}
}
late_initcall(omap2_disable_unused_clocks);
* Only enable those clocks we will need, let the drivers
* enable other clocks as necessary
*/
- clk_use(&sync_32k_ick);
- clk_use(&omapctrl_ick);
+ clk_enable(&sync_32k_ick);
+ clk_enable(&omapctrl_ick);
if (cpu_is_omap2430())
- clk_use(&sdrc_ick);
+ clk_enable(&sdrc_ick);
return 0;
}
static void omap2_mpu_recalc(struct clk * clk);
static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
-static void omap2_clk_unuse(struct clk *clk);
+static void omap2_clk_disable(struct clk *clk);
static void omap2_sys_clk_recalc(struct clk * clk);
static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
static u32 omap2_clksel_get_divisor(struct clk *clk);
if (IS_ERR(uart1_ick))
printk("Could not get uart1_ick\n");
else {
- clk_use(uart1_ick);
+ clk_enable(uart1_ick);
}
uart1_fck = clk_get(NULL, "uart1_fck");
if (IS_ERR(uart1_fck))
printk("Could not get uart1_fck\n");
else {
- clk_use(uart1_fck);
+ clk_enable(uart1_fck);
}
break;
case 1:
if (IS_ERR(uart2_ick))
printk("Could not get uart2_ick\n");
else {
- clk_use(uart2_ick);
+ clk_enable(uart2_ick);
}
uart2_fck = clk_get(NULL, "uart2_fck");
if (IS_ERR(uart2_fck))
printk("Could not get uart2_fck\n");
else {
- clk_use(uart2_fck);
+ clk_enable(uart2_fck);
}
break;
case 2:
if (IS_ERR(uart3_ick))
printk("Could not get uart3_ick\n");
else {
- clk_use(uart3_ick);
+ clk_enable(uart3_ick);
}
uart3_fck = clk_get(NULL, "uart3_fck");
if (IS_ERR(uart3_fck))
printk("Could not get uart3_fck\n");
else {
- clk_use(uart3_fck);
+ clk_enable(uart3_fck);
}
break;
}
if (IS_ERR(sys_ck))
printk(KERN_ERR "Could not get sys_ck\n");
else {
- clk_use(sys_ck);
+ clk_enable(sys_ck);
tick_period = clk_get_rate(sys_ck) / 100;
clk_put(sys_ck);
}
int ret = 0;
spin_lock_irqsave(&clockfw_lock, flags);
- if (clk->enable)
- ret = clk->enable(clk);
- else if (arch_clock->clk_enable)
+ if (arch_clock->clk_enable)
ret = arch_clock->clk_enable(clk);
- else
- printk(KERN_ERR "Could not enable clock %s\n", clk->name);
spin_unlock_irqrestore(&clockfw_lock, flags);
return ret;
unsigned long flags;
spin_lock_irqsave(&clockfw_lock, flags);
- if (clk->disable)
- clk->disable(clk);
- else if (arch_clock->clk_disable)
+ if (arch_clock->clk_disable)
arch_clock->clk_disable(clk);
- else
- printk(KERN_ERR "Could not disable clock %s\n", clk->name);
spin_unlock_irqrestore(&clockfw_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
-int clk_use(struct clk *clk)
-{
- unsigned long flags;
- int ret = 0;
-
- spin_lock_irqsave(&clockfw_lock, flags);
- if (arch_clock->clk_use)
- ret = arch_clock->clk_use(clk);
- spin_unlock_irqrestore(&clockfw_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(clk_use);
-
-void clk_unuse(struct clk *clk)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&clockfw_lock, flags);
- if (arch_clock->clk_unuse)
- arch_clock->clk_unuse(clk);
- spin_unlock_irqrestore(&clockfw_lock, flags);
-}
-EXPORT_SYMBOL(clk_unuse);
-
int clk_get_usecount(struct clk *clk)
{
unsigned long flags;
unsigned char idle_text[GBL_IDLE_TEXT_SIZE] = GBL_IDLE_TEXT_INIT;
__dsp_reset();
- clk_use(api_ck_handle);
+ clk_enable(api_ck_handle);
#if 0
omap_writew(MPUI_DSP_BOOT_CONFIG_IDLE, MPUI_DSP_BOOT_CONFIG);
__dsp_run();
udelay(100); /* to make things stable */
- clk_unuse(api_ck_handle);
+ clk_disable(api_ck_handle);
}
static void dsp_cpu_idle(void)
unsigned char icrh, icrl;
__dsp_reset();
- clk_use(api_ck_handle);
+ clk_enable(api_ck_handle);
/*
* icr settings:
dsp_set_rstvect(idle_boot_base);
__dsp_run();
udelay(100); /* to make things stable */
- clk_unuse(api_ck_handle);
+ clk_disable(api_ck_handle);
}
void dsp_set_idle_boot_base(unsigned long adr, size_t size)
/*
* note: if we are in pm_suspend / pm_resume function,
- * we are out of clk_use() management.
+ * we are out of clk_enable() management.
*/
void omap_dsp_pm_suspend(void)
{
if (! init_done)
return;
+ /* DSP code may have turned this on, make sure it gets turned off */
+ clk_enable(dsp_ck_handle);
clk_disable(dsp_ck_handle);
/* Stop any DSP domain clocks */
save_dsp_idlect2 = __raw_readw(DSP_IDLECT2);
__raw_writew(0, DSP_IDLECT2);
omap_writew(save_arm_idlect2, ARM_IDLECT2);
+ clk_disable(api_ck_handle);
}
void omap_dsp_pm_resume(void)
clk_enable(api_ck_handle);
__raw_writew(save_dsp_idlect2, DSP_IDLECT2);
omap_writew(save_arm_idlect2, ARM_IDLECT2);
+ clk_disable(api_ck_handle);
/* Run DSP, if it was running */
if (cpustat.stat != CPUSTAT_RESET)
if (cpustat.req == CPUSTAT_RUN) {
if (cpustat.stat < CPUSTAT_RUN) {
__dsp_reset();
- clk_use(api_ck_handle);
+ clk_enable(api_ck_handle);
udelay(10);
__dsp_run();
cpustat.stat = CPUSTAT_RUN;
if (cpustat.stat == CPUSTAT_RUN) {
disable_irq(INT_DSP_MMU);
- clk_unuse(api_ck_handle);
+ clk_disable(api_ck_handle);
}
/*
int lbase, victim;
unsigned short cam_l_va_mask;
- clk_use(dsp_ck_handle);
+ clk_enable(dsp_ck_handle);
get_tlb_lock(&lbase, NULL);
for (victim = 0; victim < lbase; victim++) {
lbase++;
set_tlb_lock(lbase, lbase);
- clk_unuse(dsp_ck_handle);
+ clk_disable(dsp_ck_handle);
return 0;
}
int i;
int max_valid = 0;
- clk_use(dsp_ck_handle);
+ clk_enable(dsp_ck_handle);
get_tlb_lock(&lbase, NULL);
for (i = 0; i < lbase; i++) {
/* set new lock base */
set_tlb_lock(max_valid+1, max_valid+1);
- clk_unuse(dsp_ck_handle);
+ clk_disable(dsp_ck_handle);
return 0;
}
static void dsp_mmu_gflush(void)
{
- clk_use(dsp_ck_handle);
+ clk_enable(dsp_ck_handle);
__dsp_mmu_gflush();
set_tlb_lock(1, 1);
- clk_unuse(dsp_ck_handle);
+ clk_disable(dsp_ck_handle);
}
/*
unsigned long phys;
void *virt;
- clk_use(dsp_ck_handle);
+ clk_enable(dsp_ck_handle);
down_write(&exmap_sem);
dsp_mmu_disable(); /* clear all */
dsp_mmu_load_tlb(DSP_INIT_PAGE, phys, DSPMMU_CAM_L_SLST_4KB,
DSPMMU_CAM_L_P, DSPMMU_RAM_L_AP_FA);
up_write(&exmap_sem);
- clk_unuse(dsp_ck_handle);
+ clk_disable(dsp_ck_handle);
}
static void dsp_mmu_shutdown(void)
if (p >= size)
return 0;
- clk_use(api_ck_handle);
+ clk_enable(api_ck_handle);
read = count;
if (count > size - p)
read = size - p;
}
*ppos += read;
out:
- clk_unuse(api_ck_handle);
+ clk_disable(api_ck_handle);
return read;
}
if (p >= size)
return 0;
- clk_use(api_ck_handle);
+ clk_enable(api_ck_handle);
written = count;
if (count > size - p)
written = size - p;
}
*ppos += written;
out:
- clk_unuse(api_ck_handle);
+ clk_disable(api_ck_handle);
return written;
}
int lbase, victim;
int i;
- clk_use(dsp_ck_handle);
+ clk_enable(dsp_ck_handle);
down_read(&exmap_sem);
get_tlb_lock(&lbase, &victim);
set_tlb_lock(lbase, victim);
up_read(&exmap_sem);
- clk_unuse(dsp_ck_handle);
+ clk_disable(dsp_ck_handle);
return len;
}
if (IS_ERR(gpio_ick))
printk("Could not get arm_gpio_ck\n");
else
- clk_use(gpio_ick);
+ clk_enable(gpio_ick);
}
if (cpu_is_omap24xx()) {
gpio_ick = clk_get(NULL, "gpios_ick");
if (IS_ERR(gpio_ick))
printk("Could not get gpios_ick\n");
else
- clk_use(gpio_ick);
+ clk_enable(gpio_ick);
gpio_fck = clk_get(NULL, "gpios_fck");
if (IS_ERR(gpio_ick))
printk("Could not get gpios_fck\n");
else
- clk_use(gpio_fck);
+ clk_enable(gpio_fck);
}
#ifdef CONFIG_ARCH_OMAP15XX
{
if (cpu_is_omap1510() || cpu_is_omap16xx()) {
omap_dsp_request_mem();
- clk_use(mcbsp_dsp_ck);
- clk_use(mcbsp_api_ck);
+ clk_enable(mcbsp_dsp_ck);
+ clk_enable(mcbsp_api_ck);
/* enable 12MHz clock to mcbsp 1 & 3 */
- clk_use(mcbsp_dspxor_ck);
+ clk_enable(mcbsp_dspxor_ck);
/*
* DSP external peripheral reset
{
if (cpu_is_omap1510() || cpu_is_omap16xx()) {
omap_dsp_release_mem();
- clk_unuse(mcbsp_dspxor_ck);
- clk_unuse(mcbsp_dsp_ck);
- clk_unuse(mcbsp_api_ck);
+ clk_disable(mcbsp_dspxor_ck);
+ clk_disable(mcbsp_dsp_ck);
+ clk_disable(mcbsp_api_ck);
}
}
if (!cpu_is_omap16xx())
return -ENODEV;
- /* Make sure there's clock for OCPI */
- clk_enable(ocpi_ck);
-
/* Enable access for OHCI in OCPI */
val = omap_readl(OCPI_PROT);
val &= ~0xff;
if (IS_ERR(ocpi_ck))
return PTR_ERR(ocpi_ck);
- clk_use(ocpi_ck);
+ clk_enable(ocpi_ck);
ocpi_enable();
printk("OMAP OCPI interconnect driver loaded\n");
if (!cpu_is_omap16xx())
return;
- clk_unuse(ocpi_ck);
+ clk_disable(ocpi_ck);
clk_put(ocpi_ck);
}
if (IS_ERR(gpt1_ick))
printk(KERN_ERR "Could not get gpt1_ick\n");
else
- clk_use(gpt1_ick);
+ clk_enable(gpt1_ick);
gpt1_fck = clk_get(NULL, "gpt1_fck");
if (IS_ERR(gpt1_fck))
printk(KERN_ERR "Could not get gpt1_fck\n");
else
- clk_use(gpt1_fck);
+ clk_enable(gpt1_fck);
mdelay(100); /* Wait for clocks to stabilize */
printk(KERN_ERR "omap-rng.c: Could not get rng_ick\n");
return PTR_ERR(rng_ick);
}
- clk_use(rng_ick);
+ clk_enable(rng_ick);
}
printk("OMAP Random Number Generator ver. %02x\n",
return -EBUSY;
if (cpu_is_omap16xx()) {
- clk_use(armwdt_ck); /* Enable the clock */
+ clk_enable(armwdt_ck); /* Enable the clock */
}
if (cpu_is_omap24xx()) {
- clk_use(mpu_wdt_ick); /* Enable the interface clock */
- clk_use(mpu_wdt_fck); /* Enable the functional clock */
+ clk_enable(mpu_wdt_ick); /* Enable the interface clock */
+ clk_enable(mpu_wdt_fck); /* Enable the functional clock */
}
/* initialize prescaler */
omap_wdt_disable();
if (cpu_is_omap16xx()) {
- clk_unuse(armwdt_ck); /* Disable the clock */
+ clk_disable(armwdt_ck); /* Disable the clock */
clk_put(armwdt_ck);
armwdt_ck = NULL;
}
if (cpu_is_omap24xx()) {
- clk_unuse(mpu_wdt_ick); /* Disable the clock */
- clk_unuse(mpu_wdt_fck); /* Disable the clock */
+ clk_disable(mpu_wdt_ick); /* Disable the clock */
+ clk_disable(mpu_wdt_fck); /* Disable the clock */
clk_put(mpu_wdt_ick);
clk_put(mpu_wdt_fck);
mpu_wdt_ick = NULL;
{
if (cpu_is_omap24xx()) {
if (enable) {
- clk_use(omap_i2c_dev->iclk);
- clk_use(omap_i2c_dev->fclk);
+ clk_enable(omap_i2c_dev->iclk);
+ clk_enable(omap_i2c_dev->fclk);
} else {
- clk_unuse(omap_i2c_dev->iclk);
- clk_unuse(omap_i2c_dev->fclk);
+ clk_disable(omap_i2c_dev->iclk);
+ clk_disable(omap_i2c_dev->fclk);
}
}
}
if (host->data && !(host->data->flags & MMC_DATA_WRITE))
cmdreg |= 1 << 15;
- clk_use(host->fclk);
+ clk_enable(host->fclk);
OMAP_MMC_WRITE(host->base, CTO, 200);
OMAP_MMC_WRITE(host->base, ARGL, cmd->arg & 0xffff);
}
host->data = NULL;
host->sg_len = 0;
- clk_unuse(host->fclk);
+ clk_disable(host->fclk);
/* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
* dozens of requests until the card finishes writing data.
if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
DBG("MMC%d: End request, err %x\n", host->id, cmd->error);
host->mrq = NULL;
- clk_unuse(host->fclk);
+ clk_disable(host->fclk);
mmc_request_done(host->mmc, cmd->mrq);
}
}
}
host->hw_bus_mode = host->bus_mode;
- clk_use(host->fclk);
+ clk_enable(host->fclk);
/* On insanely high arm_per frequencies something sometimes
* goes somehow out of sync, and the POW bit is not being set,
while (0 == (OMAP_MMC_READ(host->base, STAT) & 1));
OMAP_MMC_WRITE(host->base, STAT, 1);
}
- clk_unuse(host->fclk);
+ clk_disable(host->fclk);
}
static int mmc_omap_get_ro(struct mmc_host *mmc)
host->iclk = clk_get(&pdev->dev, "mmc_ick");
if (IS_ERR(host->iclk))
goto out;
- clk_use(host->iclk);
+ clk_enable(host->iclk);
}
if (!cpu_is_omap24xx())
omap_nand_clk = clk_get(NULL, "armper_ck");
BUG_ON(omap_nand_clk == NULL);
- clk_use(omap_nand_clk);
+ clk_enable(omap_nand_clk);
l = nand_read_reg(NND_REVISION);
printk(KERN_INFO "omap-hw-nand: OMAP NAND Controller rev. %d.%d\n", l>>4, l & 0xf);
*/
static void __exit omap_nand_cleanup (void)
{
- clk_unuse(omap_nand_clk);
+ clk_disable(omap_nand_clk);
clk_put(omap_nand_clk);
nand_release(omap_mtd);
kfree(omap_mtd);
return;
if (enable) {
- clk_use(udc->dc_clk);
- clk_use(udc->hhc_clk);
+ clk_enable(udc->dc_clk);
+ clk_enable(udc->hhc_clk);
udelay(100);
} else {
- clk_unuse(udc->hhc_clk);
- clk_unuse(udc->dc_clk);
+ clk_disable(udc->hhc_clk);
+ clk_disable(udc->dc_clk);
}
}
hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
/* can't use omap_udc_enable_clock yet */
- clk_use(dc_clk);
- clk_use(hhc_clk);
+ clk_enable(dc_clk);
+ clk_enable(hhc_clk);
udelay(100);
}
if (cpu_is_omap16xx()) {
udc->dc_clk = dc_clk;
udc->hhc_clk = hhc_clk;
- clk_unuse(hhc_clk);
- clk_unuse(dc_clk);
+ clk_disable(hhc_clk);
+ clk_disable(dc_clk);
}
create_proc_file();
put_device(xceiv->dev);
if (cpu_is_omap16xx()) {
- clk_unuse(hhc_clk);
- clk_unuse(dc_clk);
+ clk_disable(hhc_clk);
+ clk_disable(dc_clk);
clk_put(hhc_clk);
clk_put(dc_clk);
}
static void omap_ohci_clock_power(int on)
{
if (on) {
- clk_use(usb_dc_ck);
- clk_use(usb_host_ck);
+ clk_enable(usb_dc_ck);
+ clk_enable(usb_host_ck);
/* guesstimate for T5 == 1x 32K clock + APLL lock time */
udelay(100);
} else {
- clk_unuse(usb_host_ck);
- clk_unuse(usb_dc_ck);
+ clk_disable(usb_host_ck);
+ clk_disable(usb_dc_ck);
}
}
static void enable_lcd_clocks(int enable)
{
if (enable) {
- clk_use(dispc.dss_ick);
- clk_use(dispc.dss1_fck);
+ clk_enable(dispc.dss_ick);
+ clk_enable(dispc.dss1_fck);
} else {
- clk_unuse(dispc.dss1_fck);
- clk_unuse(dispc.dss_ick);
+ clk_disable(dispc.dss1_fck);
+ clk_disable(dispc.dss_ick);
}
}
static void enable_digit_clocks(int enable)
{
if (enable)
- clk_use(dispc.dss_54m_fck);
+ clk_enable(dispc.dss_54m_fck);
else
- clk_unuse(dispc.dss_54m_fck);
+ clk_disable(dispc.dss_54m_fck);
}
static void omap_dispc_suspend(void)
pr_err("failed to adjust LCD rate\n");
goto fail1;
}
- clk_use(omap_lcdc.lcd_ck);
+ clk_enable(omap_lcdc.lcd_ck);
r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, "omap-lcdc",
omap_lcdc.fbdev);
fail3:
free_irq(OMAP_LCDC_IRQ, omap_lcdc.fbdev);
fail2:
- clk_unuse(omap_lcdc.lcd_ck);
+ clk_disable(omap_lcdc.lcd_ck);
fail1:
clk_put(omap_lcdc.lcd_ck);
fail0:
omap_lcdc.vram_virt, omap_lcdc.vram_phys);
omap_free_lcd_dma();
free_irq(OMAP_LCDC_IRQ, omap_lcdc.fbdev);
- clk_unuse(omap_lcdc.lcd_ck);
+ clk_disable(omap_lcdc.lcd_ck);
clk_put(omap_lcdc.lcd_ck);
}
struct clk_functions {
int (*clk_enable)(struct clk *clk);
void (*clk_disable)(struct clk *clk);
- int (*clk_use)(struct clk *clk);
- void (*clk_unuse)(struct clk *clk);
long (*clk_round_rate)(struct clk *clk, unsigned long rate);
int (*clk_set_rate)(struct clk *clk, unsigned long rate);
int (*clk_set_parent)(struct clk *clk, struct clk *parent);
return -ECANCELED;
}
- clk_use(aic23_mclk);
+ clk_enable(aic23_mclk);
printk(KERN_DEBUG
"MCLK = %d [%d], usecount = %d\n",
CODEC_CLOCK);
}
- clk_unuse(aic23_mclk);
+ clk_disable(aic23_mclk);
}
audio_aic23_write(POWER_DOWN_CONTROL_ADDR,
}
}
- clk_use( aic23_mclk );
+ clk_enable( aic23_mclk );
DPRINTK("MCLK = %d [%d], usecount = %d\n",(uint)clk_get_rate( aic23_mclk ),
CODEC_CLOCK, clk_get_usecount( aic23_mclk));
projects / linux-2.6-omap-h63xx.git / commitdiff