return -EINVAL;
spin_lock_irqsave(&retu_lock, flags);
+
+ if ((channel == 8) && retu_is_vilma) {
+ int scr = retu_read_reg(RETU_REG_ADCSCR);
+ int ch = (retu_read_reg(RETU_REG_ADCR) >> 10) & 0xf;
+ if (((scr & 0xff) != 0) && (ch != 8))
+ retu_write_reg (RETU_REG_ADCSCR, (scr & ~0xff));
+ }
+
/* Select the channel and read result */
retu_write_reg(RETU_REG_ADCR, channel << 10);
res = retu_read_reg(RETU_REG_ADCR) & 0x3ff;
+
+ if (retu_is_vilma)
+ retu_write_reg(RETU_REG_ADCR, (1 << 13));
+
/* Unlock retu */
spin_unlock_irqrestore(&retu_lock, flags);
#define RETU_REG_RTCHMAR 0x05 /* RTC hours and minutes alarm and time set register */
#define RETU_REG_RTCCALR 0x06 /* RTC calibration register */
#define RETU_REG_ADCR 0x08 /* ADC result */
+#define RETU_REG_ADCSCR 0x09 /* ADC sample ctrl */
#define RETU_REG_CC1 0x0d /* Common control register 1 */
#define RETU_REG_CC2 0x0e /* Common control register 2 */
#define RETU_REG_CTRL_CLR 0x0f /* Regulator clear register */