Extra omap code in linux-omap tree

[linux-2.6-omap-h63xx.git] / drivers / spi / omap2_mcspi.c

diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index d6d0c5d241ce1bcbcd9b68bc15caacbccb5f5be8..f2b4d329e1aa5f1c9e496597cd052da2c09e56f0 100644 (file)
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -59,37 +59,40 @@
 
 /* per-register bitmasks: */
 
-#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
-#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET        (1 << 1)
+#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE        BIT(4)
+#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP        BIT(2)
+#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
+#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET        BIT(1)
 
-#define OMAP2_MCSPI_SYSSTATUS_RESETDONE        (1 << 0)
+#define OMAP2_MCSPI_SYSSTATUS_RESETDONE        BIT(0)
 
-#define OMAP2_MCSPI_MODULCTRL_SINGLE   (1 << 0)
-#define OMAP2_MCSPI_MODULCTRL_MS       (1 << 2)
-#define OMAP2_MCSPI_MODULCTRL_STEST    (1 << 3)
+#define OMAP2_MCSPI_MODULCTRL_SINGLE   BIT(0)
+#define OMAP2_MCSPI_MODULCTRL_MS       BIT(2)
+#define OMAP2_MCSPI_MODULCTRL_STEST    BIT(3)
 
-#define OMAP2_MCSPI_CHCONF_PHA         (1 << 0)
-#define OMAP2_MCSPI_CHCONF_POL         (1 << 1)
+#define OMAP2_MCSPI_CHCONF_PHA         BIT(0)
+#define OMAP2_MCSPI_CHCONF_POL         BIT(1)
 #define OMAP2_MCSPI_CHCONF_CLKD_MASK   (0x0f << 2)
-#define OMAP2_MCSPI_CHCONF_EPOL                (1 << 6)
+#define OMAP2_MCSPI_CHCONF_EPOL                BIT(6)
 #define OMAP2_MCSPI_CHCONF_WL_MASK     (0x1f << 7)
-#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
-#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
+#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
+#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
 #define OMAP2_MCSPI_CHCONF_TRM_MASK    (0x03 << 12)
-#define OMAP2_MCSPI_CHCONF_DMAW                (1 << 14)
-#define OMAP2_MCSPI_CHCONF_DMAR                (1 << 15)
-#define OMAP2_MCSPI_CHCONF_DPE0                (1 << 16)
-#define OMAP2_MCSPI_CHCONF_DPE1                (1 << 17)
-#define OMAP2_MCSPI_CHCONF_IS          (1 << 18)
-#define OMAP2_MCSPI_CHCONF_TURBO       (1 << 19)
-#define OMAP2_MCSPI_CHCONF_FORCE       (1 << 20)
+#define OMAP2_MCSPI_CHCONF_DMAW                BIT(14)
+#define OMAP2_MCSPI_CHCONF_DMAR                BIT(15)
+#define OMAP2_MCSPI_CHCONF_DPE0                BIT(16)
+#define OMAP2_MCSPI_CHCONF_DPE1                BIT(17)
+#define OMAP2_MCSPI_CHCONF_IS          BIT(18)
+#define OMAP2_MCSPI_CHCONF_TURBO       BIT(19)
+#define OMAP2_MCSPI_CHCONF_FORCE       BIT(20)
 
-#define OMAP2_MCSPI_CHSTAT_RXS         (1 << 0)
-#define OMAP2_MCSPI_CHSTAT_TXS         (1 << 1)
-#define OMAP2_MCSPI_CHSTAT_EOT         (1 << 2)
+#define OMAP2_MCSPI_CHSTAT_RXS         BIT(0)
+#define OMAP2_MCSPI_CHSTAT_TXS         BIT(1)
+#define OMAP2_MCSPI_CHSTAT_EOT         BIT(2)
 
-#define OMAP2_MCSPI_CHCTRL_EN          (1 << 0)
+#define OMAP2_MCSPI_CHCTRL_EN          BIT(0)
 
+#define OMAP2_MCSPI_WAKEUPENABLE_WKEN  BIT(0)
 
 /* We have 2 DMA channels per CS, one for RX and one for TX */
 struct omap2_mcspi_dma {
@@ -884,8 +887,12 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
        } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
 
        mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
-                       /* (3 << 8) | (2 << 3) | */
-                       OMAP2_MCSPI_SYSCONFIG_AUTOIDLE);
+                       OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
+                       OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
+                       OMAP2_MCSPI_SYSCONFIG_SMARTIDLE);
+
+       mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
+                       OMAP2_MCSPI_WAKEUPENABLE_WKEN);
 
        omap2_mcspi_set_master_mode(master);