drivers/spi/omap2_mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrjölä <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/delay.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/io.h>
  35
  36 #include <linux/spi/spi.h>
  37
  38 #include <mach/dma.h>
  39 #include <mach/clock.h>
  40
  41
  42 #define OMAP2_MCSPI_MAX_FREQ            48000000
  43
  44 #define OMAP2_MCSPI_REVISION            0x00
  45 #define OMAP2_MCSPI_SYSCONFIG           0x10
  46 #define OMAP2_MCSPI_SYSSTATUS           0x14
  47 #define OMAP2_MCSPI_IRQSTATUS           0x18
  48 #define OMAP2_MCSPI_IRQENABLE           0x1c
  49 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  50 #define OMAP2_MCSPI_SYST                0x24
  51 #define OMAP2_MCSPI_MODULCTRL           0x28
  52
  53 /* per-channel banks, 0x14 bytes each, first is: */
  54 #define OMAP2_MCSPI_CHCONF0             0x2c
  55 #define OMAP2_MCSPI_CHSTAT0             0x30
  56 #define OMAP2_MCSPI_CHCTRL0             0x34
  57 #define OMAP2_MCSPI_TX0                 0x38
  58 #define OMAP2_MCSPI_RX0                 0x3c
  59
  60 /* per-register bitmasks: */
  61
  62 #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
  63 #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
  64 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE  BIT(0)
  65 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
  66
  67 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
  68
  69 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  70 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  71 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  72
  73 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  74 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  75 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  76 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  77 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  78 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  79 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  80 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  81 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  82 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  83 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  84 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  85 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  86 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  87 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  88
  89 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  90 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  91 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  92
  93 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  94
  95 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
  96
  97 /* We have 2 DMA channels per CS, one for RX and one for TX */
  98 struct omap2_mcspi_dma {
  99         int dma_tx_channel;
 100         int dma_rx_channel;
 101
 102         int dma_tx_sync_dev;
 103         int dma_rx_sync_dev;
 104
 105         struct completion dma_tx_completion;
 106         struct completion dma_rx_completion;
 107 };
 108
 109 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 110  * cache operations; better heuristics consider wordsize and bitrate.
 111  */
 112 #define DMA_MIN_BYTES                   8
 113
 114
 115 struct omap2_mcspi {
 116         struct work_struct      work;
 117         /* lock protects queue and registers */
 118         spinlock_t              lock;
 119         struct list_head        msg_queue;
 120         struct spi_master       *master;
 121         struct clk              *ick;
 122         struct clk              *fck;
 123         /* Virtual base address of the controller */
 124         void __iomem            *base;
 125         unsigned long           phys;
 126         /* SPI1 has 4 channels, while SPI2 has 2 */
 127         struct omap2_mcspi_dma  *dma_channels;
 128 };
 129
 130 struct omap2_mcspi_cs {
 131         void __iomem            *base;
 132         unsigned long           phys;
 133         int                     word_len;
 134 };
 135
 136 static struct workqueue_struct *omap2_mcspi_wq;
 137
 138 #define MOD_REG_BIT(val, mask, set) do { \
 139         if (set) \
 140                 val |= mask; \
 141         else \
 142                 val &= ~mask; \
 143 } while (0)
 144
 145 static inline void mcspi_write_reg(struct spi_master *master,
 146                 int idx, u32 val)
 147 {
 148         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 149
 150         __raw_writel(val, mcspi->base + idx);
 151 }
 152
 153 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 154 {
 155         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 156
 157         return __raw_readl(mcspi->base + idx);
 158 }
 159
 160 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 161                 int idx, u32 val)
 162 {
 163         struct omap2_mcspi_cs   *cs = spi->controller_state;
 164
 165         __raw_writel(val, cs->base +  idx);
 166 }
 167
 168 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 169 {
 170         struct omap2_mcspi_cs   *cs = spi->controller_state;
 171
 172         return __raw_readl(cs->base + idx);
 173 }
 174
 175 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 176                 int is_read, int enable)
 177 {
 178         u32 l, rw;
 179
 180         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 181
 182         if (is_read) /* 1 is read, 0 write */
 183                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 184         else
 185                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 186
 187         MOD_REG_BIT(l, rw, enable);
 188         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 189 }
 190
 191 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 192 {
 193         u32 l;
 194
 195         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
 196         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 197 }
 198
 199 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 200 {
 201         u32 l;
 202
 203         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 204         MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
 205         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 206 }
 207
 208 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 209 {
 210         u32 l;
 211
 212         /* setup when switching from (reset default) slave mode
 213          * to single-channel master mode
 214          */
 215         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 216         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
 217         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
 218         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
 219         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 220 }
 221
 222 static unsigned
 223 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 224 {
 225         struct omap2_mcspi      *mcspi;
 226         struct omap2_mcspi_cs   *cs = spi->controller_state;
 227         struct omap2_mcspi_dma  *mcspi_dma;
 228         unsigned int            count, c;
 229         unsigned long           base, tx_reg, rx_reg;
 230         int                     word_len, data_type, element_count;
 231         u8                      * rx;
 232         const u8                * tx;
 233
 234         mcspi = spi_master_get_devdata(spi->master);
 235         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 236
 237         count = xfer->len;
 238         c = count;
 239         word_len = cs->word_len;
 240
 241         base = cs->phys;
 242         tx_reg = base + OMAP2_MCSPI_TX0;
 243         rx_reg = base + OMAP2_MCSPI_RX0;
 244         rx = xfer->rx_buf;
 245         tx = xfer->tx_buf;
 246
 247         if (word_len <= 8) {
 248                 data_type = OMAP_DMA_DATA_TYPE_S8;
 249                 element_count = count;
 250         } else if (word_len <= 16) {
 251                 data_type = OMAP_DMA_DATA_TYPE_S16;
 252                 element_count = count >> 1;
 253         } else /* word_len <= 32 */ {
 254                 data_type = OMAP_DMA_DATA_TYPE_S32;
 255                 element_count = count >> 2;
 256         }
 257
 258         if (tx != NULL) {
 259                 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
 260                                 data_type, element_count, 1,
 261                                 OMAP_DMA_SYNC_ELEMENT,
 262                                 mcspi_dma->dma_tx_sync_dev, 0);
 263
 264                 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
 265                                 OMAP_DMA_AMODE_CONSTANT,
 266                                 tx_reg, 0, 0);
 267
 268                 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
 269                                 OMAP_DMA_AMODE_POST_INC,
 270                                 xfer->tx_dma, 0, 0);
 271         }
 272
 273         if (rx != NULL) {
 274                 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
 275                                 data_type, element_count, 1,
 276                                 OMAP_DMA_SYNC_ELEMENT,
 277                                 mcspi_dma->dma_rx_sync_dev, 1);
 278
 279                 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
 280                                 OMAP_DMA_AMODE_CONSTANT,
 281                                 rx_reg, 0, 0);
 282
 283                 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
 284                                 OMAP_DMA_AMODE_POST_INC,
 285                                 xfer->rx_dma, 0, 0);
 286         }
 287
 288         if (tx != NULL) {
 289                 omap_start_dma(mcspi_dma->dma_tx_channel);
 290                 omap2_mcspi_set_dma_req(spi, 0, 1);
 291         }
 292
 293         if (rx != NULL) {
 294                 omap_start_dma(mcspi_dma->dma_rx_channel);
 295                 omap2_mcspi_set_dma_req(spi, 1, 1);
 296         }
 297
 298         if (tx != NULL) {
 299                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 300                 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
 301         }
 302
 303         if (rx != NULL) {
 304                 wait_for_completion(&mcspi_dma->dma_rx_completion);
 305                 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
 306         }
 307         return count;
 308 }
 309
 310 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 311 {
 312         unsigned long timeout;
 313
 314         timeout = jiffies + msecs_to_jiffies(1000);
 315         while (!(__raw_readl(reg) & bit)) {
 316                 if (time_after(jiffies, timeout))
 317                         return -1;
 318                 cpu_relax();
 319         }
 320         return 0;
 321 }
 322
 323 static unsigned
 324 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 325 {
 326         struct omap2_mcspi      *mcspi;
 327         struct omap2_mcspi_cs   *cs = spi->controller_state;
 328         unsigned int            count, c;
 329         u32                     l;
 330         void __iomem            *base = cs->base;
 331         void __iomem            *tx_reg;
 332         void __iomem            *rx_reg;
 333         void __iomem            *chstat_reg;
 334         int                     word_len;
 335
 336         mcspi = spi_master_get_devdata(spi->master);
 337         count = xfer->len;
 338         c = count;
 339         word_len = cs->word_len;
 340
 341         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 342         l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 343
 344         /* We store the pre-calculated register addresses on stack to speed
 345          * up the transfer loop. */
 346         tx_reg          = base + OMAP2_MCSPI_TX0;
 347         rx_reg          = base + OMAP2_MCSPI_RX0;
 348         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 349
 350         if (word_len <= 8) {
 351                 u8              *rx;
 352                 const u8        *tx;
 353
 354                 rx = xfer->rx_buf;
 355                 tx = xfer->tx_buf;
 356
 357                 do {
 358                         c -= 1;
 359                         if (tx != NULL) {
 360                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 361                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 362                                         dev_err(&spi->dev, "TXS timed out\n");
 363                                         goto out;
 364                                 }
 365 #ifdef VERBOSE
 366                                 dev_dbg(&spi->dev, "write-%d %02x\n",
 367                                                 word_len, *tx);
 368 #endif
 369                                 __raw_writel(*tx++, tx_reg);
 370                         }
 371                         if (rx != NULL) {
 372                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 373                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 374                                         dev_err(&spi->dev, "RXS timed out\n");
 375                                         goto out;
 376                                 }
 377                                 /* prevent last RX_ONLY read from triggering
 378                                  * more word i/o: switch to rx+tx
 379                                  */
 380                                 if (c == 0 && tx == NULL)
 381                                         mcspi_write_cs_reg(spi,
 382                                                         OMAP2_MCSPI_CHCONF0, l);
 383                                 *rx++ = __raw_readl(rx_reg);
 384 #ifdef VERBOSE
 385                                 dev_dbg(&spi->dev, "read-%d %02x\n",
 386                                                 word_len, *(rx - 1));
 387 #endif
 388                         }
 389                 } while (c);
 390         } else if (word_len <= 16) {
 391                 u16             *rx;
 392                 const u16       *tx;
 393
 394                 rx = xfer->rx_buf;
 395                 tx = xfer->tx_buf;
 396                 do {
 397                         c -= 2;
 398                         if (tx != NULL) {
 399                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 400                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 401                                         dev_err(&spi->dev, "TXS timed out\n");
 402                                         goto out;
 403                                 }
 404 #ifdef VERBOSE
 405                                 dev_dbg(&spi->dev, "write-%d %04x\n",
 406                                                 word_len, *tx);
 407 #endif
 408                                 __raw_writel(*tx++, tx_reg);
 409                         }
 410                         if (rx != NULL) {
 411                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 412                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 413                                         dev_err(&spi->dev, "RXS timed out\n");
 414                                         goto out;
 415                                 }
 416                                 /* prevent last RX_ONLY read from triggering
 417                                  * more word i/o: switch to rx+tx
 418                                  */
 419                                 if (c == 0 && tx == NULL)
 420                                         mcspi_write_cs_reg(spi,
 421                                                         OMAP2_MCSPI_CHCONF0, l);
 422                                 *rx++ = __raw_readl(rx_reg);
 423 #ifdef VERBOSE
 424                                 dev_dbg(&spi->dev, "read-%d %04x\n",
 425                                                 word_len, *(rx - 1));
 426 #endif
 427                         }
 428                 } while (c);
 429         } else if (word_len <= 32) {
 430                 u32             *rx;
 431                 const u32       *tx;
 432
 433                 rx = xfer->rx_buf;
 434                 tx = xfer->tx_buf;
 435                 do {
 436                         c -= 4;
 437                         if (tx != NULL) {
 438                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 439                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 440                                         dev_err(&spi->dev, "TXS timed out\n");
 441                                         goto out;
 442                                 }
 443 #ifdef VERBOSE
 444                                 dev_dbg(&spi->dev, "write-%d %04x\n",
 445                                                 word_len, *tx);
 446 #endif
 447                                 __raw_writel(*tx++, tx_reg);
 448                         }
 449                         if (rx != NULL) {
 450                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 451                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 452                                         dev_err(&spi->dev, "RXS timed out\n");
 453                                         goto out;
 454                                 }
 455                                 /* prevent last RX_ONLY read from triggering
 456                                  * more word i/o: switch to rx+tx
 457                                  */
 458                                 if (c == 0 && tx == NULL)
 459                                         mcspi_write_cs_reg(spi,
 460                                                         OMAP2_MCSPI_CHCONF0, l);
 461                                 *rx++ = __raw_readl(rx_reg);
 462 #ifdef VERBOSE
 463                                 dev_dbg(&spi->dev, "read-%d %04x\n",
 464                                                 word_len, *(rx - 1));
 465 #endif
 466                         }
 467                 } while (c);
 468         }
 469
 470         /* for TX_ONLY mode, be sure all words have shifted out */
 471         if (xfer->rx_buf == NULL) {
 472                 if (mcspi_wait_for_reg_bit(chstat_reg,
 473                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 474                         dev_err(&spi->dev, "TXS timed out\n");
 475                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 476                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 477                         dev_err(&spi->dev, "EOT timed out\n");
 478         }
 479 out:
 480         return count - c;
 481 }
 482
 483 /* called only when no transfer is active to this device */
 484 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 485                 struct spi_transfer *t)
 486 {
 487         struct omap2_mcspi_cs *cs = spi->controller_state;
 488         struct omap2_mcspi *mcspi;
 489         u32 l = 0, div = 0;
 490         u8 word_len = spi->bits_per_word;
 491
 492         mcspi = spi_master_get_devdata(spi->master);
 493
 494         if (t != NULL && t->bits_per_word)
 495                 word_len = t->bits_per_word;
 496
 497         cs->word_len = word_len;
 498
 499         if (spi->max_speed_hz) {
 500                 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
 501                                         > spi->max_speed_hz)
 502                         div++;
 503         } else
 504                 div = 15;
 505
 506         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 507
 508         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 509          * REVISIT: this controller could support SPI_3WIRE mode.
 510          */
 511         l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
 512         l |= OMAP2_MCSPI_CHCONF_DPE0;
 513
 514         /* wordlength */
 515         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 516         l |= (word_len - 1) << 7;
 517
 518         /* set chipselect polarity; manage with FORCE */
 519         if (!(spi->mode & SPI_CS_HIGH))
 520                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 521         else
 522                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 523
 524         /* set clock divisor */
 525         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 526         l |= div << 2;
 527
 528         /* set SPI mode 0..3 */
 529         if (spi->mode & SPI_CPOL)
 530                 l |= OMAP2_MCSPI_CHCONF_POL;
 531         else
 532                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 533         if (spi->mode & SPI_CPHA)
 534                 l |= OMAP2_MCSPI_CHCONF_PHA;
 535         else
 536                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 537
 538         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 539
 540         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 541                         OMAP2_MCSPI_MAX_FREQ / (1 << div),
 542                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 543                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 544
 545         return 0;
 546 }
 547
 548 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
 549 {
 550         struct spi_device       *spi = data;
 551         struct omap2_mcspi      *mcspi;
 552         struct omap2_mcspi_dma  *mcspi_dma;
 553
 554         mcspi = spi_master_get_devdata(spi->master);
 555         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 556
 557         complete(&mcspi_dma->dma_rx_completion);
 558
 559         /* We must disable the DMA RX request */
 560         omap2_mcspi_set_dma_req(spi, 1, 0);
 561 }
 562
 563 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
 564 {
 565         struct spi_device       *spi = data;
 566         struct omap2_mcspi      *mcspi;
 567         struct omap2_mcspi_dma  *mcspi_dma;
 568
 569         mcspi = spi_master_get_devdata(spi->master);
 570         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 571
 572         complete(&mcspi_dma->dma_tx_completion);
 573
 574         /* We must disable the DMA TX request */
 575         omap2_mcspi_set_dma_req(spi, 0, 0);
 576 }
 577
 578 static int omap2_mcspi_request_dma(struct spi_device *spi)
 579 {
 580         struct spi_master       *master = spi->master;
 581         struct omap2_mcspi      *mcspi;
 582         struct omap2_mcspi_dma  *mcspi_dma;
 583
 584         mcspi = spi_master_get_devdata(master);
 585         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 586
 587         if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
 588                         omap2_mcspi_dma_rx_callback, spi,
 589                         &mcspi_dma->dma_rx_channel)) {
 590                 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
 591                 return -EAGAIN;
 592         }
 593
 594         if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
 595                         omap2_mcspi_dma_tx_callback, spi,
 596                         &mcspi_dma->dma_tx_channel)) {
 597                 omap_free_dma(mcspi_dma->dma_rx_channel);
 598                 mcspi_dma->dma_rx_channel = -1;
 599                 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
 600                 return -EAGAIN;
 601         }
 602
 603         init_completion(&mcspi_dma->dma_rx_completion);
 604         init_completion(&mcspi_dma->dma_tx_completion);
 605
 606         return 0;
 607 }
 608
 609 /* the spi->mode bits understood by this driver: */
 610 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
 611
 612 static int omap2_mcspi_setup(struct spi_device *spi)
 613 {
 614         int                     ret;
 615         struct omap2_mcspi      *mcspi;
 616         struct omap2_mcspi_dma  *mcspi_dma;
 617         struct omap2_mcspi_cs   *cs = spi->controller_state;
 618
 619         if (spi->mode & ~MODEBITS) {
 620                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 621                         spi->mode & ~MODEBITS);
 622                 return -EINVAL;
 623         }
 624
 625         if (spi->bits_per_word == 0)
 626                 spi->bits_per_word = 8;
 627         else if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 628                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 629                         spi->bits_per_word);
 630                 return -EINVAL;
 631         }
 632
 633         mcspi = spi_master_get_devdata(spi->master);
 634         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 635
 636         if (!cs) {
 637                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 638                 if (!cs)
 639                         return -ENOMEM;
 640                 cs->base = mcspi->base + spi->chip_select * 0x14;
 641                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
 642                 spi->controller_state = cs;
 643         }
 644
 645         if (mcspi_dma->dma_rx_channel == -1
 646                         || mcspi_dma->dma_tx_channel == -1) {
 647                 ret = omap2_mcspi_request_dma(spi);
 648                 if (ret < 0)
 649                         return ret;
 650         }
 651
 652         clk_enable(mcspi->ick);
 653         clk_enable(mcspi->fck);
 654         ret = omap2_mcspi_setup_transfer(spi, NULL);
 655         clk_disable(mcspi->fck);
 656         clk_disable(mcspi->ick);
 657
 658         return ret;
 659 }
 660
 661 static void omap2_mcspi_cleanup(struct spi_device *spi)
 662 {
 663         struct omap2_mcspi      *mcspi;
 664         struct omap2_mcspi_dma  *mcspi_dma;
 665
 666         mcspi = spi_master_get_devdata(spi->master);
 667         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 668
 669         kfree(spi->controller_state);
 670
 671         if (mcspi_dma->dma_rx_channel != -1) {
 672                 omap_free_dma(mcspi_dma->dma_rx_channel);
 673                 mcspi_dma->dma_rx_channel = -1;
 674         }
 675         if (mcspi_dma->dma_tx_channel != -1) {
 676                 omap_free_dma(mcspi_dma->dma_tx_channel);
 677                 mcspi_dma->dma_tx_channel = -1;
 678         }
 679 }
 680
 681 static void omap2_mcspi_work(struct work_struct *work)
 682 {
 683         struct omap2_mcspi      *mcspi;
 684
 685         mcspi = container_of(work, struct omap2_mcspi, work);
 686         spin_lock_irq(&mcspi->lock);
 687
 688         clk_enable(mcspi->ick);
 689         clk_enable(mcspi->fck);
 690
 691         /* We only enable one channel at a time -- the one whose message is
 692          * at the head of the queue -- although this controller would gladly
 693          * arbitrate among multiple channels.  This corresponds to "single
 694          * channel" master mode.  As a side effect, we need to manage the
 695          * chipselect with the FORCE bit ... CS != channel enable.
 696          */
 697         while (!list_empty(&mcspi->msg_queue)) {
 698                 struct spi_message              *m;
 699                 struct spi_device               *spi;
 700                 struct spi_transfer             *t = NULL;
 701                 int                             cs_active = 0;
 702                 struct omap2_mcspi_cs           *cs;
 703                 int                             par_override = 0;
 704                 int                             status = 0;
 705                 u32                             chconf;
 706
 707                 m = container_of(mcspi->msg_queue.next, struct spi_message,
 708                                  queue);
 709
 710                 list_del_init(&m->queue);
 711                 spin_unlock_irq(&mcspi->lock);
 712
 713                 spi = m->spi;
 714                 cs = spi->controller_state;
 715
 716                 omap2_mcspi_set_enable(spi, 1);
 717                 list_for_each_entry(t, &m->transfers, transfer_list) {
 718                         if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 719                                 status = -EINVAL;
 720                                 break;
 721                         }
 722                         if (par_override || t->speed_hz || t->bits_per_word) {
 723                                 par_override = 1;
 724                                 status = omap2_mcspi_setup_transfer(spi, t);
 725                                 if (status < 0)
 726                                         break;
 727                                 if (!t->speed_hz && !t->bits_per_word)
 728                                         par_override = 0;
 729                         }
 730
 731                         if (!cs_active) {
 732                                 omap2_mcspi_force_cs(spi, 1);
 733                                 cs_active = 1;
 734                         }
 735
 736                         chconf = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 737                         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 738                         if (t->tx_buf == NULL)
 739                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
 740                         else if (t->rx_buf == NULL)
 741                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
 742                         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, chconf);
 743
 744                         if (t->len) {
 745                                 unsigned        count;
 746
 747                                 /* RX_ONLY mode needs dummy data in TX reg */
 748                                 if (t->tx_buf == NULL)
 749                                         __raw_writel(0, cs->base
 750                                                         + OMAP2_MCSPI_TX0);
 751
 752                                 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
 753                                         count = omap2_mcspi_txrx_dma(spi, t);
 754                                 else
 755                                         count = omap2_mcspi_txrx_pio(spi, t);
 756                                 m->actual_length += count;
 757
 758                                 if (count != t->len) {
 759                                         status = -EIO;
 760                                         break;
 761                                 }
 762                         }
 763
 764                         if (t->delay_usecs)
 765                                 udelay(t->delay_usecs);
 766
 767                         /* ignore the "leave it on after last xfer" hint */
 768                         if (t->cs_change) {
 769                                 omap2_mcspi_force_cs(spi, 0);
 770                                 cs_active = 0;
 771                         }
 772                 }
 773
 774                 /* Restore defaults if they were overriden */
 775                 if (par_override) {
 776                         par_override = 0;
 777                         status = omap2_mcspi_setup_transfer(spi, NULL);
 778                 }
 779
 780                 if (cs_active)
 781                         omap2_mcspi_force_cs(spi, 0);
 782
 783                 omap2_mcspi_set_enable(spi, 0);
 784
 785                 m->status = status;
 786                 m->complete(m->context);
 787
 788                 spin_lock_irq(&mcspi->lock);
 789         }
 790
 791         clk_disable(mcspi->fck);
 792         clk_disable(mcspi->ick);
 793
 794         spin_unlock_irq(&mcspi->lock);
 795 }
 796
 797 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
 798 {
 799         struct omap2_mcspi      *mcspi;
 800         unsigned long           flags;
 801         struct spi_transfer     *t;
 802
 803         m->actual_length = 0;
 804         m->status = 0;
 805
 806         /* reject invalid messages and transfers */
 807         if (list_empty(&m->transfers) || !m->complete)
 808                 return -EINVAL;
 809         list_for_each_entry(t, &m->transfers, transfer_list) {
 810                 const void      *tx_buf = t->tx_buf;
 811                 void            *rx_buf = t->rx_buf;
 812                 unsigned        len = t->len;
 813
 814                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
 815                                 || (len && !(rx_buf || tx_buf))
 816                                 || (t->bits_per_word &&
 817                                         (  t->bits_per_word < 4
 818                                         || t->bits_per_word > 32))) {
 819                         dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
 820                                         t->speed_hz,
 821                                         len,
 822                                         tx_buf ? "tx" : "",
 823                                         rx_buf ? "rx" : "",
 824                                         t->bits_per_word);
 825                         return -EINVAL;
 826                 }
 827                 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
 828                         dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
 829                                         t->speed_hz,
 830                                         OMAP2_MCSPI_MAX_FREQ/(1<<16));
 831                         return -EINVAL;
 832                 }
 833
 834                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
 835                         continue;
 836
 837                 /* Do DMA mapping "early" for better error reporting and
 838                  * dcache use.  Note that if dma_unmap_single() ever starts
 839                  * to do real work on ARM, we'd need to clean up mappings
 840                  * for previous transfers on *ALL* exits of this loop...
 841                  */
 842                 if (tx_buf != NULL) {
 843                         t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
 844                                         len, DMA_TO_DEVICE);
 845                         if (dma_mapping_error(&spi->dev, t->tx_dma)) {
 846                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
 847                                                 'T', len);
 848                                 return -EINVAL;
 849                         }
 850                 }
 851                 if (rx_buf != NULL) {
 852                         t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
 853                                         DMA_FROM_DEVICE);
 854                         if (dma_mapping_error(&spi->dev, t->rx_dma)) {
 855                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
 856                                                 'R', len);
 857                                 if (tx_buf != NULL)
 858                                         dma_unmap_single(NULL, t->tx_dma,
 859                                                         len, DMA_TO_DEVICE);
 860                                 return -EINVAL;
 861                         }
 862                 }
 863         }
 864
 865         mcspi = spi_master_get_devdata(spi->master);
 866
 867         spin_lock_irqsave(&mcspi->lock, flags);
 868         list_add_tail(&m->queue, &mcspi->msg_queue);
 869         queue_work(omap2_mcspi_wq, &mcspi->work);
 870         spin_unlock_irqrestore(&mcspi->lock, flags);
 871
 872         return 0;
 873 }
 874
 875 static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
 876 {
 877         struct spi_master       *master = mcspi->master;
 878         u32                     tmp;
 879
 880         clk_enable(mcspi->ick);
 881         clk_enable(mcspi->fck);
 882
 883         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
 884                         OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
 885         do {
 886                 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
 887         } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
 888
 889         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
 890                         OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
 891                         OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
 892                         OMAP2_MCSPI_SYSCONFIG_SMARTIDLE);
 893
 894         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
 895                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
 896
 897         omap2_mcspi_set_master_mode(master);
 898
 899         clk_disable(mcspi->fck);
 900         clk_disable(mcspi->ick);
 901         return 0;
 902 }
 903
 904 static u8 __initdata spi1_rxdma_id [] = {
 905         OMAP24XX_DMA_SPI1_RX0,
 906         OMAP24XX_DMA_SPI1_RX1,
 907         OMAP24XX_DMA_SPI1_RX2,
 908         OMAP24XX_DMA_SPI1_RX3,
 909 };
 910
 911 static u8 __initdata spi1_txdma_id [] = {
 912         OMAP24XX_DMA_SPI1_TX0,
 913         OMAP24XX_DMA_SPI1_TX1,
 914         OMAP24XX_DMA_SPI1_TX2,
 915         OMAP24XX_DMA_SPI1_TX3,
 916 };
 917
 918 static u8 __initdata spi2_rxdma_id[] = {
 919         OMAP24XX_DMA_SPI2_RX0,
 920         OMAP24XX_DMA_SPI2_RX1,
 921 };
 922
 923 static u8 __initdata spi2_txdma_id[] = {
 924         OMAP24XX_DMA_SPI2_TX0,
 925         OMAP24XX_DMA_SPI2_TX1,
 926 };
 927
 928 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
 929 static u8 __initdata spi3_rxdma_id[] = {
 930         OMAP24XX_DMA_SPI3_RX0,
 931         OMAP24XX_DMA_SPI3_RX1,
 932 };
 933
 934 static u8 __initdata spi3_txdma_id[] = {
 935         OMAP24XX_DMA_SPI3_TX0,
 936         OMAP24XX_DMA_SPI3_TX1,
 937 };
 938 #endif
 939
 940 #ifdef CONFIG_ARCH_OMAP3
 941 static u8 __initdata spi4_rxdma_id[] = {
 942         OMAP34XX_DMA_SPI4_RX0,
 943 };
 944
 945 static u8 __initdata spi4_txdma_id[] = {
 946         OMAP34XX_DMA_SPI4_TX0,
 947 };
 948 #endif
 949
 950 static int __init omap2_mcspi_probe(struct platform_device *pdev)
 951 {
 952         struct spi_master       *master;
 953         struct omap2_mcspi      *mcspi;
 954         struct resource         *r;
 955         int                     status = 0, i;
 956         const u8                *rxdma_id, *txdma_id;
 957         unsigned                num_chipselect;
 958
 959         switch (pdev->id) {
 960         case 1:
 961                 rxdma_id = spi1_rxdma_id;
 962                 txdma_id = spi1_txdma_id;
 963                 num_chipselect = 4;
 964                 break;
 965         case 2:
 966                 rxdma_id = spi2_rxdma_id;
 967                 txdma_id = spi2_txdma_id;
 968                 num_chipselect = 2;
 969                 break;
 970 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
 971         case 3:
 972                 rxdma_id = spi3_rxdma_id;
 973                 txdma_id = spi3_txdma_id;
 974                 num_chipselect = 2;
 975                 break;
 976 #endif
 977 #ifdef CONFIG_ARCH_OMAP3
 978         case 4:
 979                 rxdma_id = spi4_rxdma_id;
 980                 txdma_id = spi4_txdma_id;
 981                 num_chipselect = 1;
 982                 break;
 983 #endif
 984         default:
 985                 return -EINVAL;
 986         }
 987
 988         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
 989         if (master == NULL) {
 990                 dev_dbg(&pdev->dev, "master allocation failed\n");
 991                 return -ENOMEM;
 992         }
 993
 994         if (pdev->id != -1)
 995                 master->bus_num = pdev->id;
 996
 997         master->setup = omap2_mcspi_setup;
 998         master->transfer = omap2_mcspi_transfer;
 999         master->cleanup = omap2_mcspi_cleanup;
1000         master->num_chipselect = num_chipselect;
1001
1002         dev_set_drvdata(&pdev->dev, master);
1003
1004         mcspi = spi_master_get_devdata(master);
1005         mcspi->master = master;
1006
1007         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1008         if (r == NULL) {
1009                 status = -ENODEV;
1010                 goto err1;
1011         }
1012         if (!request_mem_region(r->start, (r->end - r->start) + 1,
1013                         dev_name(&pdev->dev))) {
1014                 status = -EBUSY;
1015                 goto err1;
1016         }
1017
1018         mcspi->phys = r->start;
1019         mcspi->base = ioremap(r->start, r->end - r->start + 1);
1020         if (!mcspi->base) {
1021                 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1022                 status = -ENOMEM;
1023                 goto err1aa;
1024         }
1025
1026         INIT_WORK(&mcspi->work, omap2_mcspi_work);
1027
1028         spin_lock_init(&mcspi->lock);
1029         INIT_LIST_HEAD(&mcspi->msg_queue);
1030
1031         mcspi->ick = clk_get(&pdev->dev, "ick");
1032         if (IS_ERR(mcspi->ick)) {
1033                 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1034                 status = PTR_ERR(mcspi->ick);
1035                 goto err1a;
1036         }
1037         mcspi->fck = clk_get(&pdev->dev, "fck");
1038         if (IS_ERR(mcspi->fck)) {
1039                 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1040                 status = PTR_ERR(mcspi->fck);
1041                 goto err2;
1042         }
1043
1044         mcspi->dma_channels = kcalloc(master->num_chipselect,
1045                         sizeof(struct omap2_mcspi_dma),
1046                         GFP_KERNEL);
1047
1048         if (mcspi->dma_channels == NULL)
1049                 goto err3;
1050
1051         for (i = 0; i < num_chipselect; i++) {
1052                 mcspi->dma_channels[i].dma_rx_channel = -1;
1053                 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1054                 mcspi->dma_channels[i].dma_tx_channel = -1;
1055                 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1056         }
1057
1058         if (omap2_mcspi_reset(mcspi) < 0)
1059                 goto err4;
1060
1061         status = spi_register_master(master);
1062         if (status < 0)
1063                 goto err4;
1064
1065         return status;
1066
1067 err4:
1068         kfree(mcspi->dma_channels);
1069 err3:
1070         clk_put(mcspi->fck);
1071 err2:
1072         clk_put(mcspi->ick);
1073 err1a:
1074         iounmap(mcspi->base);
1075 err1aa:
1076         release_mem_region(r->start, (r->end - r->start) + 1);
1077 err1:
1078         spi_master_put(master);
1079         return status;
1080 }
1081
1082 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1083 {
1084         struct spi_master       *master;
1085         struct omap2_mcspi      *mcspi;
1086         struct omap2_mcspi_dma  *dma_channels;
1087         struct resource         *r;
1088         void __iomem *base;
1089
1090         master = dev_get_drvdata(&pdev->dev);
1091         mcspi = spi_master_get_devdata(master);
1092         dma_channels = mcspi->dma_channels;
1093
1094         clk_put(mcspi->fck);
1095         clk_put(mcspi->ick);
1096
1097         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1098         release_mem_region(r->start, (r->end - r->start) + 1);
1099
1100         base = mcspi->base;
1101         spi_unregister_master(master);
1102         iounmap(base);
1103         kfree(dma_channels);
1104
1105         return 0;
1106 }
1107
1108 /* work with hotplug and coldplug */
1109 MODULE_ALIAS("platform:omap2_mcspi");
1110
1111 static struct platform_driver omap2_mcspi_driver = {
1112         .driver = {
1113                 .name =         "omap2_mcspi",
1114                 .owner =        THIS_MODULE,
1115         },
1116         .remove =       __exit_p(omap2_mcspi_remove),
1117 };
1118
1119
1120 static int __init omap2_mcspi_init(void)
1121 {
1122         omap2_mcspi_wq = create_singlethread_workqueue(
1123                                 omap2_mcspi_driver.driver.name);
1124         if (omap2_mcspi_wq == NULL)
1125                 return -1;
1126         return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1127 }
1128 subsys_initcall(omap2_mcspi_init);
1129
1130 static void __exit omap2_mcspi_exit(void)
1131 {
1132         platform_driver_unregister(&omap2_mcspi_driver);
1133
1134         destroy_workqueue(omap2_mcspi_wq);
1135 }
1136 module_exit(omap2_mcspi_exit);
1137
1138 MODULE_LICENSE("GPL");