sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/device.h>
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/initval.h>
  31 #include <sound/soc.h>
  32
  33 #include <mach/control.h>
  34 #include <mach/dma.h>
  35 #include <mach/mcbsp.h>
  36 #include "omap-mcbsp.h"
  37 #include "omap-pcm.h"
  38
  39 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_44100 | \
  40                                  SNDRV_PCM_RATE_48000 | \
  41                                  SNDRV_PCM_RATE_KNOT)
  42
  43 struct omap_mcbsp_data {
  44         unsigned int                    bus_id;
  45         struct omap_mcbsp_reg_cfg       regs;
  46         /*
  47          * Flags indicating is the bus already activated and configured by
  48          * another substream
  49          */
  50         int                             active;
  51         int                             configured;
  52 };
  53
  54 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
  55
  56 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
  57
  58 /*
  59  * Stream DMA parameters. DMA request line and port address are set runtime
  60  * since they are different between OMAP1 and later OMAPs
  61  */
  62 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2] = {
  63 {
  64         { .name         = "I2S PCM Stereo out", },
  65         { .name         = "I2S PCM Stereo in", },
  66 },
  67 };
  68
  69 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  70 static const int omap1_dma_reqs[][2] = {
  71         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
  72         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
  73         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
  74 };
  75 static const unsigned long omap1_mcbsp_port[][2] = {
  76         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  77           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  78         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  79           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  80         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
  81           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
  82 };
  83 #else
  84 static const int omap1_dma_reqs[][2] = {};
  85 static const unsigned long omap1_mcbsp_port[][2] = {};
  86 #endif
  87
  88 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  89 static const int omap24xx_dma_reqs[][2] = {
  90         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
  91         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
  92 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
  93         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
  94         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
  95         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
  96 #endif
  97 };
  98 #else
  99 static const int omap24xx_dma_reqs[][2] = {};
 100 #endif
 101
 102 #if defined(CONFIG_ARCH_OMAP2420)
 103 static const unsigned long omap2420_mcbsp_port[][2] = {
 104         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
 105           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
 106         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
 107           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
 108 };
 109 #else
 110 static const unsigned long omap2420_mcbsp_port[][2] = {};
 111 #endif
 112
 113 #if defined(CONFIG_ARCH_OMAP2430)
 114 static const unsigned long omap2430_mcbsp_port[][2] = {
 115         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 116           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 117         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 118           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 119         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 120           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 121         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 122           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 123         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 124           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 125 };
 126 #else
 127 static const unsigned long omap2430_mcbsp_port[][2] = {};
 128 #endif
 129
 130 #if defined(CONFIG_ARCH_OMAP34XX)
 131 static const unsigned long omap34xx_mcbsp_port[][2] = {
 132         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 133           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 134         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 135           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 136         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 137           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 138         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 139           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 140         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 141           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 142 };
 143 #else
 144 static const unsigned long omap34xx_mcbsp_port[][2] = {};
 145 #endif
 146
 147 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream)
 148 {
 149         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 150         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 151         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 152         int err = 0;
 153
 154         if (!cpu_dai->active)
 155                 err = omap_mcbsp_request(mcbsp_data->bus_id);
 156
 157         return err;
 158 }
 159
 160 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream)
 161 {
 162         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 163         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 164         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 165
 166         if (!cpu_dai->active) {
 167                 omap_mcbsp_free(mcbsp_data->bus_id);
 168                 mcbsp_data->configured = 0;
 169         }
 170 }
 171
 172 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd)
 173 {
 174         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 175         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 176         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 177         int err = 0;
 178
 179         switch (cmd) {
 180         case SNDRV_PCM_TRIGGER_START:
 181         case SNDRV_PCM_TRIGGER_RESUME:
 182         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 183                 if (!mcbsp_data->active++)
 184                         omap_mcbsp_start(mcbsp_data->bus_id);
 185                 break;
 186
 187         case SNDRV_PCM_TRIGGER_STOP:
 188         case SNDRV_PCM_TRIGGER_SUSPEND:
 189         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 190                 if (!--mcbsp_data->active)
 191                         omap_mcbsp_stop(mcbsp_data->bus_id);
 192                 break;
 193         default:
 194                 err = -EINVAL;
 195         }
 196
 197         return err;
 198 }
 199
 200 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 201                                     struct snd_pcm_hw_params *params)
 202 {
 203         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 204         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 205         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 206         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 207         int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
 208         unsigned long port;
 209
 210         if (cpu_class_is_omap1()) {
 211                 dma = omap1_dma_reqs[bus_id][substream->stream];
 212                 port = omap1_mcbsp_port[bus_id][substream->stream];
 213         } else if (cpu_is_omap2420()) {
 214                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 215                 port = omap2420_mcbsp_port[bus_id][substream->stream];
 216         } else if (cpu_is_omap2430()) {
 217                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 218                 port = omap2430_mcbsp_port[bus_id][substream->stream];
 219         } else if (cpu_is_omap343x()) {
 220                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 221                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
 222         } else {
 223                 return -ENODEV;
 224         }
 225         omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
 226         omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
 227         cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
 228
 229         if (mcbsp_data->configured) {
 230                 /* McBSP already configured by another stream */
 231                 return 0;
 232         }
 233
 234         switch (params_channels(params)) {
 235         case 2:
 236                 /* Set 1 word per (McBPSP) frame and use dual-phase frames */
 237                 regs->rcr2      |= RFRLEN2(1 - 1) | RPHASE;
 238                 regs->rcr1      |= RFRLEN1(1 - 1);
 239                 regs->xcr2      |= XFRLEN2(1 - 1) | XPHASE;
 240                 regs->xcr1      |= XFRLEN1(1 - 1);
 241                 break;
 242         default:
 243                 /* Unsupported number of channels */
 244                 return -EINVAL;
 245         }
 246
 247         switch (params_format(params)) {
 248         case SNDRV_PCM_FORMAT_S16_LE:
 249                 /* Set word lengths */
 250                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 251                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 252                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 253                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 254                 /* Set FS period and length in terms of bit clock periods */
 255                 regs->srgr2     |= FPER(16 * 2 - 1);
 256                 regs->srgr1     |= FWID(16 - 1);
 257                 break;
 258         default:
 259                 /* Unsupported PCM format */
 260                 return -EINVAL;
 261         }
 262
 263         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
 264         mcbsp_data->configured = 1;
 265
 266         return 0;
 267 }
 268
 269 /*
 270  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 271  * cache is initialized here
 272  */
 273 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 274                                       unsigned int fmt)
 275 {
 276         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 277         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 278
 279         if (mcbsp_data->configured)
 280                 return 0;
 281
 282         memset(regs, 0, sizeof(*regs));
 283         /* Generic McBSP register settings */
 284         regs->spcr2     |= XINTM(3) | FREE;
 285         regs->spcr1     |= RINTM(3);
 286         regs->rcr2      |= RFIG;
 287         regs->xcr2      |= XFIG;
 288
 289         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 290         case SND_SOC_DAIFMT_I2S:
 291                 /* 1-bit data delay */
 292                 regs->rcr2      |= RDATDLY(1);
 293                 regs->xcr2      |= XDATDLY(1);
 294                 break;
 295         default:
 296                 /* Unsupported data format */
 297                 return -EINVAL;
 298         }
 299
 300         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 301         case SND_SOC_DAIFMT_CBS_CFS:
 302                 /* McBSP master. Set FS and bit clocks as outputs */
 303                 regs->pcr0      |= FSXM | FSRM |
 304                                    CLKXM | CLKRM;
 305                 /* Sample rate generator drives the FS */
 306                 regs->srgr2     |= FSGM;
 307                 break;
 308         case SND_SOC_DAIFMT_CBM_CFM:
 309                 /* McBSP slave */
 310                 break;
 311         default:
 312                 /* Unsupported master/slave configuration */
 313                 return -EINVAL;
 314         }
 315
 316         /* Set bit clock (CLKX/CLKR) and FS polarities */
 317         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 318         case SND_SOC_DAIFMT_NB_NF:
 319                 /*
 320                  * Normal BCLK + FS.
 321                  * FS active low. TX data driven on falling edge of bit clock
 322                  * and RX data sampled on rising edge of bit clock.
 323                  */
 324                 regs->pcr0      |= FSXP | FSRP |
 325                                    CLKXP | CLKRP;
 326                 break;
 327         case SND_SOC_DAIFMT_NB_IF:
 328                 regs->pcr0      |= CLKXP | CLKRP;
 329                 break;
 330         case SND_SOC_DAIFMT_IB_NF:
 331                 regs->pcr0      |= FSXP | FSRP;
 332                 break;
 333         case SND_SOC_DAIFMT_IB_IF:
 334                 break;
 335         default:
 336                 return -EINVAL;
 337         }
 338
 339         return 0;
 340 }
 341
 342 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 343                                      int div_id, int div)
 344 {
 345         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 346         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 347
 348         if (div_id != OMAP_MCBSP_CLKGDV)
 349                 return -ENODEV;
 350
 351         regs->srgr1     |= CLKGDV(div - 1);
 352
 353         return 0;
 354 }
 355
 356 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
 357                                        int clk_id)
 358 {
 359         int sel_bit;
 360         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
 361
 362         if (cpu_class_is_omap1()) {
 363                 /* OMAP1's can use only external source clock */
 364                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
 365                         return -EINVAL;
 366                 else
 367                         return 0;
 368         }
 369
 370         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
 371                 return -EINVAL;
 372
 373         if (cpu_is_omap343x())
 374                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
 375
 376         switch (mcbsp_data->bus_id) {
 377         case 0:
 378                 reg = OMAP2_CONTROL_DEVCONF0;
 379                 sel_bit = 2;
 380                 break;
 381         case 1:
 382                 reg = OMAP2_CONTROL_DEVCONF0;
 383                 sel_bit = 6;
 384                 break;
 385         case 2:
 386                 reg = reg_devconf1;
 387                 sel_bit = 0;
 388                 break;
 389         case 3:
 390                 reg = reg_devconf1;
 391                 sel_bit = 2;
 392                 break;
 393         case 4:
 394                 reg = reg_devconf1;
 395                 sel_bit = 4;
 396                 break;
 397         default:
 398                 return -EINVAL;
 399         }
 400
 401         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
 402                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 403         else
 404                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 405
 406         return 0;
 407 }
 408
 409 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 410                                          int clk_id, unsigned int freq,
 411                                          int dir)
 412 {
 413         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 414         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 415         int err = 0;
 416
 417         switch (clk_id) {
 418         case OMAP_MCBSP_SYSCLK_CLK:
 419                 regs->srgr2     |= CLKSM;
 420                 break;
 421         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 422         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 423                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
 424                 break;
 425
 426         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 427                 regs->srgr2     |= CLKSM;
 428         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 429                 regs->pcr0      |= SCLKME;
 430                 break;
 431         default:
 432                 err = -ENODEV;
 433         }
 434
 435         return err;
 436 }
 437
 438 struct snd_soc_dai omap_mcbsp_dai[NUM_LINKS] = {
 439 {
 440         .name = "omap-mcbsp-dai",
 441         .id = 0,
 442         .type = SND_SOC_DAI_I2S,
 443         .playback = {
 444                 .channels_min = 2,
 445                 .channels_max = 2,
 446                 .rates = OMAP_MCBSP_RATES,
 447                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 448         },
 449         .capture = {
 450                 .channels_min = 2,
 451                 .channels_max = 2,
 452                 .rates = OMAP_MCBSP_RATES,
 453                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 454         },
 455         .ops = {
 456                 .startup = omap_mcbsp_dai_startup,
 457                 .shutdown = omap_mcbsp_dai_shutdown,
 458                 .trigger = omap_mcbsp_dai_trigger,
 459                 .hw_params = omap_mcbsp_dai_hw_params,
 460         },
 461         .dai_ops = {
 462                 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
 463                 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
 464                 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
 465         },
 466         .private_data = &mcbsp_data[0].bus_id,
 467 },
 468 };
 469 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
 470
 471 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
 472 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 473 MODULE_LICENSE("GPL");