drivers/usb/host/ehci-omap.c

   1 /*
   2  * ehci-omap.c - driver for USBHOST on OMAP 34xx processor
   3  *
   4  * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller
   5  * Tested on OMAP3430 ES2.0 SDP
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  *      Author: Vikram Pandita <vikram.pandita@ti.com>
   9  *
  10  * Based on "ehci-fsl.c" and "ehci-au1xxx.c" ehci glue layers
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25  *
  26  */
  27
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <mach/gpio.h>
  31
  32 #include "ehci-omap.h"
  33
  34
  35 #ifdef CONFIG_OMAP_EHCI_PHY_MODE
  36 /* EHCI connected to External PHY */
  37
  38 /* External USB connectivity board: 750-2083-001
  39  * Connected to OMAP3430 SDP
  40  * The board has Port1 and Port2 connected to ISP1504 in 12-pin ULPI mode
  41  */
  42
  43 /* ISSUE1:
  44  *      ISP1504 for input clocking mode needs special reset handling
  45  *      Hold the PHY in reset by asserting RESET_N signal
  46  *      Then start the 60Mhz clock input to PHY
  47  *      Release the reset after a delay -
  48  *              to get the PHY state machine in working state
  49  */
  50 #define EXTERNAL_PHY_RESET
  51 #define EXT_PHY_RESET_GPIO_PORT1        (57)
  52 #define EXT_PHY_RESET_GPIO_PORT2        (61)
  53 #define EXT_PHY_RESET_DELAY             (10)
  54
  55 /* ISSUE2:
  56  * USBHOST supports External charge pump PHYs only
  57  * Use the VBUS from Port1 to power VBUS of Port2 externally
  58  * So use Port2 as the working ULPI port
  59  */
  60 #define VBUS_INTERNAL_CHARGEPUMP_HACK
  61
  62 #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
  63
  64 /*-------------------------------------------------------------------------*/
  65
  66 /* Define USBHOST clocks for clock management */
  67 struct ehci_omap_clock_defs {
  68         struct clk      *usbhost_ick_clk;
  69         struct clk      *usbhost2_120m_fck_clk;
  70         struct clk      *usbhost1_48m_fck_clk;
  71         struct clk      *usbtll_fck_clk;
  72         struct clk      *usbtll_ick_clk;
  73 };
  74
  75 /* Clock names as per clock framework: May change so keep as #defs */
  76 #define USBHOST_ICKL            "usbhost_ick"
  77 #define USBHOST_120M_FCLK       "usbhost_120m_fck"
  78 #define USBHOST_48M_FCLK        "usbhost_48m_fck"
  79 #define USBHOST_TLL_ICKL        "usbtll_ick"
  80 #define USBHOST_TLL_FCLK        "usbtll_fck"
  81 /*-------------------------------------------------------------------------*/
  82
  83
  84 #ifndef CONFIG_OMAP_EHCI_PHY_MODE
  85
  86 static void omap_usb_utmi_init(struct usb_hcd *hcd, u8 tll_channel_mask)
  87 {
  88         int i;
  89
  90         /* Use UTMI Ports of TLL */
  91         omap_writel((1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)|
  92                         (1<<OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN_SHIFT)|
  93                         (1<<OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN_SHIFT)|
  94                         (1<<OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN_SHIFT)|
  95                         (0<<OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN_SHIFT),
  96                                                 OMAP_UHH_HOSTCONFIG);
  97         /* Enusre bit is set */
  98         while (!(omap_readl(OMAP_UHH_HOSTCONFIG)
  99                         & (1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)))
 100                 cpu_relax();
 101
 102         dev_dbg(hcd->self.controller, "\nEntered UTMI MODE: success\n");
 103
 104         /* Program the 3 TLL channels upfront */
 105
 106         for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
 107
 108                 /* Disable AutoIdle */
 109                 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
 110                             ~(1<<OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE_SHIFT),
 111                             OMAP_TLL_CHANNEL_CONF(i));
 112                 /* Disable BitStuffing */
 113                 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
 114                             ~(1<<OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF_SHIFT),
 115                             OMAP_TLL_CHANNEL_CONF(i));
 116                 /* SDR Mode */
 117                 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
 118                             ~(1<<OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE_SHIFT),
 119                             OMAP_TLL_CHANNEL_CONF(i));
 120
 121         }
 122
 123         /* Program Common TLL register */
 124         omap_writel((1 << OMAP_TLL_SHARED_CONF_FCLK_IS_ON_SHIFT) |
 125                         (1 << OMAP_TLL_SHARED_CONF_USB_DIVRATION_SHIFT) |
 126                         (0 << OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN_SHIFT) |
 127                         (0 << OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN_SHFT),
 128                                 OMAP_TLL_SHARED_CONF);
 129
 130         /* Enable channels now */
 131         for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
 132
 133                 /* Enable only the channel that is needed */
 134                 if (!(tll_channel_mask & 1<<i))
 135                         continue;
 136
 137                 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) |
 138                             (1<<OMAP_TLL_CHANNEL_CONF_CHANEN_SHIFT),
 139                             OMAP_TLL_CHANNEL_CONF(i));
 140
 141                 omap_writeb(0xBE, OMAP_TLL_ULPI_SCRATCH_REGISTER(i));
 142                 dev_dbg(hcd->self.controller, "\nULPI_SCRATCH_REG[ch=%d]"
 143                         "= 0x%02x\n",
 144                         i+1, omap_readb(OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
 145         }
 146 }
 147
 148 #else
 149 # define omap_usb_utmi_init(x, y)       0
 150 #endif
 151
 152
 153 /* omap_start_ehc
 154  *      - Start the TI USBHOST controller
 155  */
 156 static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
 157 {
 158         struct ehci_omap_clock_defs *ehci_clocks;
 159
 160         dev_dbg(hcd->self.controller, "starting TI EHCI USB Controller\n");
 161
 162         ehci_clocks = (struct ehci_omap_clock_defs *)(
 163                                 ((char *)hcd_to_ehci(hcd)) +
 164                                         sizeof(struct ehci_hcd));
 165
 166         /* Start DPLL5 Programming:
 167          * Clock Framework is not doing this now:
 168          * This will be done in clock framework later
 169          */
 170         /* Enable DPLL 5 : Based on Input of 13Mhz*/
 171         cm_write_mod_reg((12 << OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT)|
 172                         (120 << OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT),
 173                         PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
 174
 175         cm_write_mod_reg(1 << OMAP3430ES2_DIV_120M_SHIFT,
 176                         PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
 177
 178         cm_write_mod_reg((7 << OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT) |
 179                         (7 << OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT),
 180                         PLL_MOD, OMAP3430ES2_CM_CLKEN2);
 181
 182         while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST2) &
 183                                 OMAP3430ES2_ST_PERIPH2_CLK_MASK))
 184                 dev_dbg(hcd->self.controller,
 185                         "idlest2 = 0x%x\n",
 186                         cm_read_mod_reg(PLL_MOD, CM_IDLEST2));
 187         /* End DPLL5 programming */
 188
 189
 190         /* PRCM settings for USBHOST:
 191          * Interface clk un-related to domain transition
 192          */
 193         cm_write_mod_reg(0 << OMAP3430ES2_AUTO_USBHOST_SHIFT,
 194                                 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 195
 196         /* Disable sleep dependency with MPU and IVA */
 197         cm_write_mod_reg((0 << OMAP3430ES2_EN_MPU_SHIFT) |
 198                                 (0 << OMAP3430ES2_EN_IVA2_SHIFT),
 199                                 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 200
 201         /* Disable Automatic transition of clock */
 202         cm_write_mod_reg(0 << OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT,
 203                                 OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
 204
 205         /* Enable Clocks for USBHOST */
 206         ehci_clocks->usbhost_ick_clk = clk_get(&dev->dev,
 207                                                 USBHOST_ICKL);
 208         if (IS_ERR(ehci_clocks->usbhost_ick_clk))
 209                 return PTR_ERR(ehci_clocks->usbhost_ick_clk);
 210         clk_enable(ehci_clocks->usbhost_ick_clk);
 211
 212
 213         ehci_clocks->usbhost2_120m_fck_clk = clk_get(&dev->dev,
 214                                                         USBHOST_120M_FCLK);
 215         if (IS_ERR(ehci_clocks->usbhost2_120m_fck_clk))
 216                 return PTR_ERR(ehci_clocks->usbhost2_120m_fck_clk);
 217         clk_enable(ehci_clocks->usbhost2_120m_fck_clk);
 218
 219         ehci_clocks->usbhost1_48m_fck_clk = clk_get(&dev->dev,
 220                                                 USBHOST_48M_FCLK);
 221         if (IS_ERR(ehci_clocks->usbhost1_48m_fck_clk))
 222                 return PTR_ERR(ehci_clocks->usbhost1_48m_fck_clk);
 223         clk_enable(ehci_clocks->usbhost1_48m_fck_clk);
 224
 225
 226 #ifdef EXTERNAL_PHY_RESET
 227         /* Refer: ISSUE1 */
 228         gpio_request(EXT_PHY_RESET_GPIO_PORT1, "USB1 PHY reset");
 229         gpio_direction_output(EXT_PHY_RESET_GPIO_PORT1, 0);
 230         gpio_request(EXT_PHY_RESET_GPIO_PORT2, "USB2 PHY reset");
 231         gpio_direction_output(EXT_PHY_RESET_GPIO_PORT2, 0);
 232         /* Hold the PHY in RESET for enough time till DIR is high */
 233         udelay(EXT_PHY_RESET_DELAY);
 234 #endif
 235
 236         /* Configure TLL for 60Mhz clk for ULPI */
 237         ehci_clocks->usbtll_fck_clk = clk_get(&dev->dev, USBHOST_TLL_FCLK);
 238         if (IS_ERR(ehci_clocks->usbtll_fck_clk))
 239                 return PTR_ERR(ehci_clocks->usbtll_fck_clk);
 240         clk_enable(ehci_clocks->usbtll_fck_clk);
 241
 242         ehci_clocks->usbtll_ick_clk = clk_get(&dev->dev, USBHOST_TLL_ICKL);
 243         if (IS_ERR(ehci_clocks->usbtll_ick_clk))
 244                 return PTR_ERR(ehci_clocks->usbtll_ick_clk);
 245         clk_enable(ehci_clocks->usbtll_ick_clk);
 246
 247         /* Disable Auto Idle of USBTLL */
 248         cm_write_mod_reg((0 << OMAP3430ES2_AUTO_USBTLL_SHIFT),
 249                                 CORE_MOD, CM_AUTOIDLE3);
 250
 251         /* Wait for TLL to be Active */
 252         while ((cm_read_mod_reg(CORE_MOD, OMAP2430_CM_IDLEST3)
 253                         & (1 << OMAP3430ES2_ST_USBTLL_SHIFT)))
 254                 cpu_relax();
 255
 256         /* perform TLL soft reset, and wait until reset is complete */
 257         omap_writel(1 << OMAP_USBTLL_SYSCONFIG_SOFTRESET_SHIFT,
 258                         OMAP_USBTLL_SYSCONFIG);
 259         /* Wait for TLL reset to complete */
 260         while (!(omap_readl(OMAP_USBTLL_SYSSTATUS)
 261                         & (1 << OMAP_USBTLL_SYSSTATUS_RESETDONE_SHIFT)))
 262                 cpu_relax();
 263
 264         dev_dbg(hcd->self.controller, "TLL RESET DONE\n");
 265
 266         /* (1<<3) = no idle mode only for initial debugging */
 267         omap_writel((1 << OMAP_USBTLL_SYSCONFIG_ENAWAKEUP_SHIFT) |
 268                         (1 << OMAP_USBTLL_SYSCONFIG_SIDLEMODE_SHIFT) |
 269                         (1 << OMAP_USBTLL_SYSCONFIG_CACTIVITY_SHIFT),
 270                         OMAP_USBTLL_SYSCONFIG);
 271
 272
 273         /* Put UHH in NoIdle/NoStandby mode */
 274         omap_writel((0 << OMAP_UHH_SYSCONFIG_AUTOIDLE_SHIFT) |
 275                         (1 << OMAP_UHH_SYSCONFIG_ENAWAKEUP_SHIFT) |
 276                         (1 << OMAP_UHH_SYSCONFIG_SIDLEMODE_SHIFT) |
 277                         (1 << OMAP_UHH_SYSCONFIG_CACTIVITY_SHIFT) |
 278                         (1 << OMAP_UHH_SYSCONFIG_MIDLEMODE_SHIFT),
 279                         OMAP_UHH_SYSCONFIG);
 280
 281 #ifdef CONFIG_OMAP_EHCI_PHY_MODE
 282         /* Bypass the TLL module for PHY mode operation */
 283         omap_writel((0 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)|
 284                         (1<<OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN_SHIFT)|
 285                         (1<<OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN_SHIFT)|
 286                         (1<<OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN_SHIFT)|
 287                         (0<<OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN_SHIFT),
 288                                                 OMAP_UHH_HOSTCONFIG);
 289         /* Ensure that BYPASS is set */
 290         while (omap_readl(OMAP_UHH_HOSTCONFIG)
 291                         & (1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT))
 292                 cpu_relax();
 293
 294         dev_dbg(hcd->self.controller, "Entered ULPI PHY MODE: success\n");
 295
 296 #else
 297         /* Enable UTMI mode for all 3 TLL channels */
 298         omap_usb_utmi_init(hcd,
 299                 OMAP_TLL_CHANNEL_1_EN_MASK |
 300                 OMAP_TLL_CHANNEL_2_EN_MASK |
 301                 OMAP_TLL_CHANNEL_3_EN_MASK
 302                 );
 303 #endif
 304
 305 #ifdef EXTERNAL_PHY_RESET
 306         /* Refer ISSUE1:
 307          * Hold the PHY in RESET for enough time till PHY is settled and ready
 308          */
 309         udelay(EXT_PHY_RESET_DELAY);
 310         gpio_set_value(EXT_PHY_RESET_GPIO_PORT1, 1);
 311         gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 1);
 312 #endif
 313
 314 #ifdef VBUS_INTERNAL_CHARGEPUMP_HACK
 315         /* Refer ISSUE2: LINK assumes external charge pump */
 316
 317         /* use Port1 VBUS to charge externally Port2:
 318          *      So for PHY mode operation use Port2 only
 319          */
 320         omap_writel((0xA << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* OTG ctrl reg*/
 321                         (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
 322                         (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
 323                         (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
 324                         (0x26),
 325                         EHCI_INSNREG05_ULPI);
 326
 327         while (!(omap_readl(EHCI_INSNREG05_ULPI)
 328                         & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)))
 329                 cpu_relax();
 330
 331 #endif
 332
 333         return 0;
 334 }
 335
 336 /*-------------------------------------------------------------------------*/
 337
 338 static void omap_stop_ehc(struct platform_device *dev, struct usb_hcd *hcd)
 339 {
 340         struct ehci_omap_clock_defs *ehci_clocks;
 341
 342         ehci_clocks = (struct ehci_omap_clock_defs *)
 343                         (((char *)hcd_to_ehci(hcd)) + sizeof(struct ehci_hcd));
 344
 345         dev_dbg(hcd->self.controller, "stopping TI EHCI USB Controller\n");
 346
 347         /* Reset OMAP modules for insmod/rmmod to work */
 348         omap_writel((1<<1), OMAP_UHH_SYSCONFIG);
 349         while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<0)))
 350                 cpu_relax();
 351         while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<1)))
 352                 cpu_relax();
 353         while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<2)))
 354                 cpu_relax();
 355         dev_dbg(hcd->self.controller,
 356                 "UHH RESET DONE OMAP_UHH_SYSSTATUS %x !!\n",
 357                         omap_readl(OMAP_UHH_SYSSTATUS));
 358
 359         omap_writel((1<<1), OMAP_USBTLL_SYSCONFIG);
 360         while (!(omap_readl(OMAP_USBTLL_SYSSTATUS) & (1<<0)))
 361                 cpu_relax();
 362         dev_dbg(hcd->self.controller, "TLL RESET DONE\n");
 363
 364         if (ehci_clocks->usbtll_fck_clk != NULL) {
 365                 clk_disable(ehci_clocks->usbtll_fck_clk);
 366                 clk_put(ehci_clocks->usbtll_fck_clk);
 367                 ehci_clocks->usbtll_fck_clk = NULL;
 368         }
 369
 370         if (ehci_clocks->usbhost_ick_clk != NULL) {
 371                 clk_disable(ehci_clocks->usbhost_ick_clk);
 372                 clk_put(ehci_clocks->usbhost_ick_clk);
 373                 ehci_clocks->usbhost_ick_clk = NULL;
 374         }
 375
 376         if (ehci_clocks->usbhost1_48m_fck_clk != NULL) {
 377                 clk_disable(ehci_clocks->usbhost1_48m_fck_clk);
 378                 clk_put(ehci_clocks->usbhost1_48m_fck_clk);
 379                 ehci_clocks->usbhost1_48m_fck_clk = NULL;
 380         }
 381
 382         if (ehci_clocks->usbhost2_120m_fck_clk != NULL) {
 383                 clk_disable(ehci_clocks->usbhost2_120m_fck_clk);
 384                 clk_put(ehci_clocks->usbhost2_120m_fck_clk);
 385                 ehci_clocks->usbhost2_120m_fck_clk = NULL;
 386         }
 387
 388         if (ehci_clocks->usbtll_ick_clk != NULL) {
 389                 clk_disable(ehci_clocks->usbtll_ick_clk);
 390                 clk_put(ehci_clocks->usbtll_ick_clk);
 391                 ehci_clocks->usbtll_ick_clk = NULL;
 392         }
 393
 394
 395 #ifdef EXTERNAL_PHY_RESET
 396         gpio_free(EXT_PHY_RESET_GPIO_PORT1);
 397         gpio_free(EXT_PHY_RESET_GPIO_PORT2);
 398 #endif
 399
 400         dev_dbg(hcd->self.controller,
 401                 "Clock to USB host has been disabled\n");
 402 }
 403
 404 static const struct hc_driver ehci_omap_hc_driver;
 405
 406 /*-------------------------------------------------------------------------*/
 407 /* configure so an HC device and id are always provided */
 408 /* always called with process context; sleeping is OK */
 409
 410 /**
 411  * ehci_hcd_omap_drv_probe - initialize TI-based HCDs
 412  * Context: !in_interrupt()
 413  *
 414  * Allocates basic resources for this USB host controller, and
 415  * then invokes the start() method for the HCD associated with it
 416  * through the hotplug entry's driver_data.
 417  *
 418  */
 419 static int ehci_hcd_omap_drv_probe(struct platform_device *dev)
 420 {
 421         int retval = 0;
 422         struct usb_hcd *hcd;
 423         struct ehci_hcd *ehci;
 424
 425         dev_dbg(&dev->dev, "ehci_hcd_omap_drv_probe()\n");
 426
 427         if (usb_disabled())
 428                 return -ENODEV;
 429
 430         if (dev->resource[1].flags != IORESOURCE_IRQ) {
 431                 dev_dbg(&dev->dev, "resource[1] is not IORESOURCE_IRQ\n");
 432                 retval = -ENOMEM;
 433         }
 434
 435         hcd = usb_create_hcd(&ehci_omap_hc_driver, &dev->dev,
 436                         dev_name(&dev->dev));
 437         if (!hcd)
 438                 return -ENOMEM;
 439
 440         retval = omap_start_ehc(dev, hcd);
 441         if (retval)
 442                 return retval;
 443
 444         hcd->rsrc_start = 0;
 445         hcd->rsrc_len = 0;
 446         hcd->rsrc_start = dev->resource[0].start;
 447         hcd->rsrc_len = dev->resource[0].end - dev->resource[0].start + 1;
 448
 449         hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
 450         if (!hcd->regs) {
 451                 dev_err(&dev->dev, "ioremap failed\n");
 452                 return -ENOMEM;
 453         }
 454
 455         ehci = hcd_to_ehci(hcd);
 456         ehci->caps = hcd->regs;
 457
 458         ehci->sbrn = 0x20;
 459
 460         ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
 461         /* cache this readonly data; minimize chip reads */
 462         ehci->hcs_params = readl(&ehci->caps->hcs_params);
 463
 464         /* SET 1 micro-frame Interrupt interval */
 465         writel(readl(&ehci->regs->command) | (1<<16), &ehci->regs->command);
 466
 467         retval = usb_add_hcd(hcd, dev->resource[1].start,
 468                                 IRQF_DISABLED | IRQF_SHARED);
 469         if (retval == 0)
 470                 return retval;
 471
 472         dev_dbg(hcd->self.controller, "ERR: add_hcd\n");
 473         omap_stop_ehc(dev, hcd);
 474         iounmap(hcd->regs);
 475         usb_put_hcd(hcd);
 476
 477         return retval;
 478 }
 479
 480 /*-------------------------------------------------------------------------*/
 481
 482 /* may be called without controller electrically present */
 483 /* may be called with controller, bus, and devices active */
 484
 485 /**
 486  * ehci_hcd_omap_drv_remove - shutdown processing for EHCI HCDs
 487  * @dev: USB Host Controller being removed
 488  * Context: !in_interrupt()
 489  *
 490  * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking
 491  * the HCD's stop() method.  It is always called from a thread
 492  * context, normally "rmmod", "apmd", or something similar.
 493  *
 494  */
 495 static int ehci_hcd_omap_drv_remove(struct platform_device *dev)
 496 {
 497         struct usb_hcd *hcd = platform_get_drvdata(dev);
 498
 499         dev_dbg(&dev->dev, "ehci_hcd_omap_drv_remove()\n");
 500
 501         iounmap(hcd->regs);
 502         usb_remove_hcd(hcd);
 503         usb_put_hcd(hcd);
 504         omap_stop_ehc(dev, hcd);
 505
 506         return 0;
 507 }
 508
 509 /*-------------------------------------------------------------------------*/
 510 #ifdef CONFIG_PM
 511 static int omap_ehci_bus_suspend(struct usb_hcd *hcd)
 512 {
 513         return ehci_bus_suspend(hcd);
 514 }
 515
 516 static int omap_ehci_bus_resume(struct usb_hcd *hcd)
 517 {
 518         return ehci_bus_resume(hcd);
 519 }
 520 #endif
 521 /*-------------------------------------------------------------------------*/
 522
 523 static const struct hc_driver ehci_omap_hc_driver = {
 524         .description = hcd_name,
 525         .product_desc = "OMAP-EHCI Host Controller",
 526         .hcd_priv_size = sizeof(struct ehci_hcd)
 527                                 + sizeof(struct ehci_omap_clock_defs),
 528
 529         /*
 530          * generic hardware linkage
 531          */
 532         .irq = ehci_irq,
 533         .flags = HCD_MEMORY | HCD_USB2,
 534
 535         /*
 536          * basic lifecycle operations
 537          */
 538         .reset = ehci_init,
 539         .start = ehci_run,
 540         .stop = ehci_stop,
 541         .shutdown = ehci_shutdown,
 542
 543         /*
 544          * managing i/o requests and associated device resources
 545          */
 546         .urb_enqueue = ehci_urb_enqueue,
 547         .urb_dequeue = ehci_urb_dequeue,
 548         .endpoint_disable = ehci_endpoint_disable,
 549
 550         /*
 551          * scheduling support
 552          */
 553         .get_frame_number = ehci_get_frame,
 554
 555         /*
 556          * root hub support
 557          */
 558         .hub_status_data = ehci_hub_status_data,
 559         .hub_control = ehci_hub_control,
 560 #ifdef  CONFIG_PM
 561         .bus_suspend = omap_ehci_bus_suspend,
 562         .bus_resume = omap_ehci_bus_resume,
 563 #endif
 564 };
 565
 566 /*-------------------------------------------------------------------------*/
 567 MODULE_ALIAS("platform:omap-ehci");
 568 static struct platform_driver ehci_hcd_omap_driver = {
 569         .probe = ehci_hcd_omap_drv_probe,
 570         .remove = ehci_hcd_omap_drv_remove,
 571         .shutdown = usb_hcd_platform_shutdown,
 572         /*.suspend      = ehci_hcd_omap_drv_suspend, */
 573         /*.resume       = ehci_hcd_omap_drv_resume, */
 574         .driver = {
 575                 .name = "ehci-omap",
 576                 .bus = &platform_bus_type
 577         }
 578 };