2 * ehci-omap.c - driver for USBHOST on OMAP 34xx processor
4 * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller
5 * Tested on OMAP3430 ES2.0 SDP
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Author: Vikram Pandita <vikram.pandita@ti.com>
10 * Based on "ehci-fsl.c" and "ehci-au1xxx.c" ehci glue layers
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <mach/gpio.h>
32 #include "ehci-omap.h"
35 #ifdef CONFIG_OMAP_EHCI_PHY_MODE
36 /* EHCI connected to External PHY */
38 /* External USB connectivity board: 750-2083-001
39 * Connected to OMAP3430 SDP
40 * The board has Port1 and Port2 connected to ISP1504 in 12-pin ULPI mode
44 * ISP1504 for input clocking mode needs special reset handling
45 * Hold the PHY in reset by asserting RESET_N signal
46 * Then start the 60Mhz clock input to PHY
47 * Release the reset after a delay -
48 * to get the PHY state machine in working state
50 #define EXTERNAL_PHY_RESET
51 #define EXT_PHY_RESET_GPIO_PORT1 (57)
52 #define EXT_PHY_RESET_GPIO_PORT2 (61)
53 #define EXT_PHY_RESET_DELAY (10)
56 * USBHOST supports External charge pump PHYs only
57 * Use the VBUS from Port1 to power VBUS of Port2 externally
58 * So use Port2 as the working ULPI port
60 #define VBUS_INTERNAL_CHARGEPUMP_HACK
62 #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
64 /*-------------------------------------------------------------------------*/
66 /* Define USBHOST clocks for clock management */
67 struct ehci_omap_clock_defs {
68 struct clk *usbhost_ick_clk;
69 struct clk *usbhost2_120m_fck_clk;
70 struct clk *usbhost1_48m_fck_clk;
71 struct clk *usbtll_fck_clk;
72 struct clk *usbtll_ick_clk;
75 /* Clock names as per clock framework: May change so keep as #defs */
76 #define USBHOST_ICKL "usbhost_ick"
77 #define USBHOST_120M_FCLK "usbhost_120m_fck"
78 #define USBHOST_48M_FCLK "usbhost_48m_fck"
79 #define USBHOST_TLL_ICKL "usbtll_ick"
80 #define USBHOST_TLL_FCLK "usbtll_fck"
81 /*-------------------------------------------------------------------------*/
84 #ifndef CONFIG_OMAP_EHCI_PHY_MODE
86 static void omap_usb_utmi_init(struct usb_hcd *hcd, u8 tll_channel_mask)
90 /* Use UTMI Ports of TLL */
91 omap_writel((1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)|
92 (1<<OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN_SHIFT)|
93 (1<<OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN_SHIFT)|
94 (1<<OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN_SHIFT)|
95 (0<<OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN_SHIFT),
97 /* Enusre bit is set */
98 while (!(omap_readl(OMAP_UHH_HOSTCONFIG)
99 & (1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)))
102 dev_dbg(hcd->self.controller, "\nEntered UTMI MODE: success\n");
104 /* Program the 3 TLL channels upfront */
106 for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
108 /* Disable AutoIdle */
109 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
110 ~(1<<OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE_SHIFT),
111 OMAP_TLL_CHANNEL_CONF(i));
112 /* Disable BitStuffing */
113 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
114 ~(1<<OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF_SHIFT),
115 OMAP_TLL_CHANNEL_CONF(i));
117 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
118 ~(1<<OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE_SHIFT),
119 OMAP_TLL_CHANNEL_CONF(i));
123 /* Program Common TLL register */
124 omap_writel((1 << OMAP_TLL_SHARED_CONF_FCLK_IS_ON_SHIFT) |
125 (1 << OMAP_TLL_SHARED_CONF_USB_DIVRATION_SHIFT) |
126 (0 << OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN_SHIFT) |
127 (0 << OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN_SHFT),
128 OMAP_TLL_SHARED_CONF);
130 /* Enable channels now */
131 for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
133 /* Enable only the channel that is needed */
134 if (!(tll_channel_mask & 1<<i))
137 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) |
138 (1<<OMAP_TLL_CHANNEL_CONF_CHANEN_SHIFT),
139 OMAP_TLL_CHANNEL_CONF(i));
141 omap_writeb(0xBE, OMAP_TLL_ULPI_SCRATCH_REGISTER(i));
142 dev_dbg(hcd->self.controller, "\nULPI_SCRATCH_REG[ch=%d]"
144 i+1, omap_readb(OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
149 # define omap_usb_utmi_init(x, y) 0
154 * - Start the TI USBHOST controller
156 static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
158 struct ehci_omap_clock_defs *ehci_clocks;
160 dev_dbg(hcd->self.controller, "starting TI EHCI USB Controller\n");
162 ehci_clocks = (struct ehci_omap_clock_defs *)(
163 ((char *)hcd_to_ehci(hcd)) +
164 sizeof(struct ehci_hcd));
166 /* Start DPLL5 Programming:
167 * Clock Framework is not doing this now:
168 * This will be done in clock framework later
170 /* Enable DPLL 5 : Based on Input of 13Mhz*/
171 cm_write_mod_reg((12 << OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT)|
172 (120 << OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT),
173 PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
175 cm_write_mod_reg(1 << OMAP3430ES2_DIV_120M_SHIFT,
176 PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
178 cm_write_mod_reg((7 << OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT) |
179 (7 << OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT),
180 PLL_MOD, OMAP3430ES2_CM_CLKEN2);
182 while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST2) &
183 OMAP3430ES2_ST_PERIPH2_CLK_MASK))
184 dev_dbg(hcd->self.controller,
186 cm_read_mod_reg(PLL_MOD, CM_IDLEST2));
187 /* End DPLL5 programming */
190 /* PRCM settings for USBHOST:
191 * Interface clk un-related to domain transition
193 cm_write_mod_reg(0 << OMAP3430ES2_AUTO_USBHOST_SHIFT,
194 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
196 /* Disable sleep dependency with MPU and IVA */
197 cm_write_mod_reg((0 << OMAP3430ES2_EN_MPU_SHIFT) |
198 (0 << OMAP3430ES2_EN_IVA2_SHIFT),
199 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
201 /* Disable Automatic transition of clock */
202 cm_write_mod_reg(0 << OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT,
203 OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
205 /* Enable Clocks for USBHOST */
206 ehci_clocks->usbhost_ick_clk = clk_get(&dev->dev,
208 if (IS_ERR(ehci_clocks->usbhost_ick_clk))
209 return PTR_ERR(ehci_clocks->usbhost_ick_clk);
210 clk_enable(ehci_clocks->usbhost_ick_clk);
213 ehci_clocks->usbhost2_120m_fck_clk = clk_get(&dev->dev,
215 if (IS_ERR(ehci_clocks->usbhost2_120m_fck_clk))
216 return PTR_ERR(ehci_clocks->usbhost2_120m_fck_clk);
217 clk_enable(ehci_clocks->usbhost2_120m_fck_clk);
219 ehci_clocks->usbhost1_48m_fck_clk = clk_get(&dev->dev,
221 if (IS_ERR(ehci_clocks->usbhost1_48m_fck_clk))
222 return PTR_ERR(ehci_clocks->usbhost1_48m_fck_clk);
223 clk_enable(ehci_clocks->usbhost1_48m_fck_clk);
226 #ifdef EXTERNAL_PHY_RESET
228 omap_request_gpio(EXT_PHY_RESET_GPIO_PORT1);
229 omap_set_gpio_direction(EXT_PHY_RESET_GPIO_PORT1, 0);
230 omap_request_gpio(EXT_PHY_RESET_GPIO_PORT2);
231 omap_set_gpio_direction(EXT_PHY_RESET_GPIO_PORT2, 0);
232 omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT1, 0);
233 omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT2, 0);
234 /* Hold the PHY in RESET for enough time till DIR is high */
235 udelay(EXT_PHY_RESET_DELAY);
238 /* Configure TLL for 60Mhz clk for ULPI */
239 ehci_clocks->usbtll_fck_clk = clk_get(&dev->dev, USBHOST_TLL_FCLK);
240 if (IS_ERR(ehci_clocks->usbtll_fck_clk))
241 return PTR_ERR(ehci_clocks->usbtll_fck_clk);
242 clk_enable(ehci_clocks->usbtll_fck_clk);
244 ehci_clocks->usbtll_ick_clk = clk_get(&dev->dev, USBHOST_TLL_ICKL);
245 if (IS_ERR(ehci_clocks->usbtll_ick_clk))
246 return PTR_ERR(ehci_clocks->usbtll_ick_clk);
247 clk_enable(ehci_clocks->usbtll_ick_clk);
249 /* Disable Auto Idle of USBTLL */
250 cm_write_mod_reg((0 << OMAP3430ES2_AUTO_USBTLL_SHIFT),
251 CORE_MOD, CM_AUTOIDLE3);
253 /* Wait for TLL to be Active */
254 while ((cm_read_mod_reg(CORE_MOD, OMAP2430_CM_IDLEST3)
255 & (1 << OMAP3430ES2_ST_USBTLL_SHIFT)))
258 /* perform TLL soft reset, and wait until reset is complete */
259 omap_writel(1 << OMAP_USBTLL_SYSCONFIG_SOFTRESET_SHIFT,
260 OMAP_USBTLL_SYSCONFIG);
261 /* Wait for TLL reset to complete */
262 while (!(omap_readl(OMAP_USBTLL_SYSSTATUS)
263 & (1 << OMAP_USBTLL_SYSSTATUS_RESETDONE_SHIFT)))
266 dev_dbg(hcd->self.controller, "TLL RESET DONE\n");
268 /* (1<<3) = no idle mode only for initial debugging */
269 omap_writel((1 << OMAP_USBTLL_SYSCONFIG_ENAWAKEUP_SHIFT) |
270 (1 << OMAP_USBTLL_SYSCONFIG_SIDLEMODE_SHIFT) |
271 (1 << OMAP_USBTLL_SYSCONFIG_CACTIVITY_SHIFT),
272 OMAP_USBTLL_SYSCONFIG);
275 /* Put UHH in NoIdle/NoStandby mode */
276 omap_writel((0 << OMAP_UHH_SYSCONFIG_AUTOIDLE_SHIFT) |
277 (1 << OMAP_UHH_SYSCONFIG_ENAWAKEUP_SHIFT) |
278 (1 << OMAP_UHH_SYSCONFIG_SIDLEMODE_SHIFT) |
279 (1 << OMAP_UHH_SYSCONFIG_CACTIVITY_SHIFT) |
280 (1 << OMAP_UHH_SYSCONFIG_MIDLEMODE_SHIFT),
283 #ifdef CONFIG_OMAP_EHCI_PHY_MODE
284 /* Bypass the TLL module for PHY mode operation */
285 omap_writel((0 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)|
286 (1<<OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN_SHIFT)|
287 (1<<OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN_SHIFT)|
288 (1<<OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN_SHIFT)|
289 (0<<OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN_SHIFT),
290 OMAP_UHH_HOSTCONFIG);
291 /* Ensure that BYPASS is set */
292 while (omap_readl(OMAP_UHH_HOSTCONFIG)
293 & (1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT))
296 dev_dbg(hcd->self.controller, "Entered ULPI PHY MODE: success\n");
299 /* Enable UTMI mode for all 3 TLL channels */
300 omap_usb_utmi_init(hcd,
301 OMAP_TLL_CHANNEL_1_EN_MASK |
302 OMAP_TLL_CHANNEL_2_EN_MASK |
303 OMAP_TLL_CHANNEL_3_EN_MASK
307 #ifdef EXTERNAL_PHY_RESET
309 * Hold the PHY in RESET for enough time till PHY is settled and ready
311 udelay(EXT_PHY_RESET_DELAY);
312 omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT1, 1);
313 omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT2, 1);
316 #ifdef VBUS_INTERNAL_CHARGEPUMP_HACK
317 /* Refer ISSUE2: LINK assumes external charge pump */
319 /* use Port1 VBUS to charge externally Port2:
320 * So for PHY mode operation use Port2 only
322 omap_writel((0xA << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* OTG ctrl reg*/
323 (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/* Write */
324 (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
325 (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
327 EHCI_INSNREG05_ULPI);
329 while (!(omap_readl(EHCI_INSNREG05_ULPI)
330 & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)))
338 /*-------------------------------------------------------------------------*/
340 static void omap_stop_ehc(struct platform_device *dev, struct usb_hcd *hcd)
342 struct ehci_omap_clock_defs *ehci_clocks;
344 ehci_clocks = (struct ehci_omap_clock_defs *)
345 (((char *)hcd_to_ehci(hcd)) + sizeof(struct ehci_hcd));
347 dev_dbg(hcd->self.controller, "stopping TI EHCI USB Controller\n");
349 /* Reset OMAP modules for insmod/rmmod to work */
350 omap_writel((1<<1), OMAP_UHH_SYSCONFIG);
351 while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<0)))
353 while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<1)))
355 while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<2)))
357 dev_dbg(hcd->self.controller,
358 "UHH RESET DONE OMAP_UHH_SYSSTATUS %x !!\n",
359 omap_readl(OMAP_UHH_SYSSTATUS));
361 omap_writel((1<<1), OMAP_USBTLL_SYSCONFIG);
362 while (!(omap_readl(OMAP_USBTLL_SYSSTATUS) & (1<<0)))
364 dev_dbg(hcd->self.controller, "TLL RESET DONE\n");
366 if (ehci_clocks->usbtll_fck_clk != NULL) {
367 clk_disable(ehci_clocks->usbtll_fck_clk);
368 clk_put(ehci_clocks->usbtll_fck_clk);
369 ehci_clocks->usbtll_fck_clk = NULL;
372 if (ehci_clocks->usbhost_ick_clk != NULL) {
373 clk_disable(ehci_clocks->usbhost_ick_clk);
374 clk_put(ehci_clocks->usbhost_ick_clk);
375 ehci_clocks->usbhost_ick_clk = NULL;
378 if (ehci_clocks->usbhost1_48m_fck_clk != NULL) {
379 clk_disable(ehci_clocks->usbhost1_48m_fck_clk);
380 clk_put(ehci_clocks->usbhost1_48m_fck_clk);
381 ehci_clocks->usbhost1_48m_fck_clk = NULL;
384 if (ehci_clocks->usbhost2_120m_fck_clk != NULL) {
385 clk_disable(ehci_clocks->usbhost2_120m_fck_clk);
386 clk_put(ehci_clocks->usbhost2_120m_fck_clk);
387 ehci_clocks->usbhost2_120m_fck_clk = NULL;
390 if (ehci_clocks->usbtll_ick_clk != NULL) {
391 clk_disable(ehci_clocks->usbtll_ick_clk);
392 clk_put(ehci_clocks->usbtll_ick_clk);
393 ehci_clocks->usbtll_ick_clk = NULL;
397 #ifdef EXTERNAL_PHY_RESET
398 omap_free_gpio(EXT_PHY_RESET_GPIO_PORT1);
399 omap_free_gpio(EXT_PHY_RESET_GPIO_PORT2);
402 dev_dbg(hcd->self.controller,
403 "Clock to USB host has been disabled\n");
406 static const struct hc_driver ehci_omap_hc_driver;
408 /*-------------------------------------------------------------------------*/
409 /* configure so an HC device and id are always provided */
410 /* always called with process context; sleeping is OK */
413 * ehci_hcd_omap_drv_probe - initialize TI-based HCDs
414 * Context: !in_interrupt()
416 * Allocates basic resources for this USB host controller, and
417 * then invokes the start() method for the HCD associated with it
418 * through the hotplug entry's driver_data.
421 static int ehci_hcd_omap_drv_probe(struct platform_device *dev)
425 struct ehci_hcd *ehci;
427 dev_dbg(&dev->dev, "ehci_hcd_omap_drv_probe()\n");
432 if (dev->resource[1].flags != IORESOURCE_IRQ) {
433 dev_dbg(&dev->dev, "resource[1] is not IORESOURCE_IRQ\n");
437 hcd = usb_create_hcd(&ehci_omap_hc_driver, &dev->dev, dev->dev.bus_id);
441 retval = omap_start_ehc(dev, hcd);
447 hcd->rsrc_start = dev->resource[0].start;
448 hcd->rsrc_len = dev->resource[0].end - dev->resource[0].start + 1;
450 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
452 dev_err(&dev->dev, "ioremap failed\n");
456 ehci = hcd_to_ehci(hcd);
457 ehci->caps = hcd->regs;
461 ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
462 /* cache this readonly data; minimize chip reads */
463 ehci->hcs_params = readl(&ehci->caps->hcs_params);
465 /* SET 1 micro-frame Interrupt interval */
466 writel(readl(&ehci->regs->command) | (1<<16), &ehci->regs->command);
468 retval = usb_add_hcd(hcd, dev->resource[1].start,
469 IRQF_DISABLED | IRQF_SHARED);
473 dev_dbg(hcd->self.controller, "ERR: add_hcd\n");
474 omap_stop_ehc(dev, hcd);
481 /*-------------------------------------------------------------------------*/
483 /* may be called without controller electrically present */
484 /* may be called with controller, bus, and devices active */
487 * ehci_hcd_omap_drv_remove - shutdown processing for EHCI HCDs
488 * @dev: USB Host Controller being removed
489 * Context: !in_interrupt()
491 * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking
492 * the HCD's stop() method. It is always called from a thread
493 * context, normally "rmmod", "apmd", or something similar.
496 static int ehci_hcd_omap_drv_remove(struct platform_device *dev)
498 struct usb_hcd *hcd = platform_get_drvdata(dev);
500 dev_dbg(&dev->dev, "ehci_hcd_omap_drv_remove()\n");
505 omap_stop_ehc(dev, hcd);
510 /*-------------------------------------------------------------------------*/
512 static int omap_ehci_bus_suspend(struct usb_hcd *hcd)
514 return ehci_bus_suspend(hcd);
517 static int omap_ehci_bus_resume(struct usb_hcd *hcd)
519 return ehci_bus_resume(hcd);
522 /*-------------------------------------------------------------------------*/
524 static const struct hc_driver ehci_omap_hc_driver = {
525 .description = hcd_name,
526 .product_desc = "OMAP-EHCI Host Controller",
527 .hcd_priv_size = sizeof(struct ehci_hcd)
528 + sizeof(struct ehci_omap_clock_defs),
531 * generic hardware linkage
534 .flags = HCD_MEMORY | HCD_USB2,
537 * basic lifecycle operations
542 .shutdown = ehci_shutdown,
545 * managing i/o requests and associated device resources
547 .urb_enqueue = ehci_urb_enqueue,
548 .urb_dequeue = ehci_urb_dequeue,
549 .endpoint_disable = ehci_endpoint_disable,
554 .get_frame_number = ehci_get_frame,
559 .hub_status_data = ehci_hub_status_data,
560 .hub_control = ehci_hub_control,
562 .bus_suspend = omap_ehci_bus_suspend,
563 .bus_resume = omap_ehci_bus_resume,
567 /*-------------------------------------------------------------------------*/
568 MODULE_ALIAS("platform:omap-ehci");
569 static struct platform_driver ehci_hcd_omap_driver = {
570 .probe = ehci_hcd_omap_drv_probe,
571 .remove = ehci_hcd_omap_drv_remove,
572 .shutdown = usb_hcd_platform_shutdown,
573 /*.suspend = ehci_hcd_omap_drv_suspend, */
574 /*.resume = ehci_hcd_omap_drv_resume, */
577 .bus = &platform_bus_type