drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #undef  DEBUG
  23 #undef  VERBOSE
  24
  25 #include <linux/config.h>
  26 #include <linux/module.h>
  27 #include <linux/kernel.h>
  28 #include <linux/ioport.h>
  29 #include <linux/types.h>
  30 #include <linux/errno.h>
  31 #include <linux/delay.h>
  32 #include <linux/sched.h>
  33 #include <linux/slab.h>
  34 #include <linux/init.h>
  35 #include <linux/timer.h>
  36 #include <linux/list.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/proc_fs.h>
  39 #include <linux/mm.h>
  40 #include <linux/moduleparam.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/usb_ch9.h>
  43 #include <linux/usb_gadget.h>
  44 #include <linux/usb_otg.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/clk.h>
  47
  48 #include <asm/byteorder.h>
  49 #include <asm/io.h>
  50 #include <asm/irq.h>
  51 #include <asm/system.h>
  52 #include <asm/unaligned.h>
  53 #include <asm/mach-types.h>
  54
  55 #include <asm/arch/dma.h>
  56 #include <asm/arch/usb.h>
  57
  58 #include "omap_udc.h"
  59
  60 #undef  USB_TRACE
  61
  62 /* bulk DMA seems to be behaving for both IN and OUT */
  63 #define USE_DMA
  64
  65 /* ISO too */
  66 #define USE_ISO
  67
  68 #define DRIVER_DESC     "OMAP UDC driver"
  69 #define DRIVER_VERSION  "4 October 2004"
  70
  71 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  72
  73
  74 /*
  75  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  76  * D+ pullup to allow enumeration.  That's too early for the gadget
  77  * framework to use from usb_endpoint_enable(), which happens after
  78  * enumeration as part of activating an interface.  (But if we add an
  79  * optional new "UDC not yet running" state to the gadget driver model,
  80  * even just during driver binding, the endpoint autoconfig logic is the
  81  * natural spot to manufacture new endpoints.)
  82  *
  83  * So instead of using endpoint enable calls to control the hardware setup,
  84  * this driver defines a "fifo mode" parameter.  It's used during driver
  85  * initialization to choose among a set of pre-defined endpoint configs.
  86  * See omap_udc_setup() for available modes, or to add others.  That code
  87  * lives in an init section, so use this driver as a module if you need
  88  * to change the fifo mode after the kernel boots.
  89  *
  90  * Gadget drivers normally ignore endpoints they don't care about, and
  91  * won't include them in configuration descriptors.  That means only
  92  * misbehaving hosts would even notice they exist.
  93  */
  94 #ifdef  USE_ISO
  95 static unsigned fifo_mode = 3;
  96 #else
  97 static unsigned fifo_mode = 0;
  98 #endif
  99
 100 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 101  * boot parameter "omap_udc:fifo_mode=42"
 102  */
 103 module_param (fifo_mode, uint, 0);
 104 MODULE_PARM_DESC (fifo_mode, "endpoint setup (0 == default)");
 105
 106 #ifdef  USE_DMA
 107 static unsigned use_dma = 1;
 108
 109 /* "modprobe omap_udc use_dma=y", or else as a kernel
 110  * boot parameter "omap_udc:use_dma=y"
 111  */
 112 module_param (use_dma, bool, 0);
 113 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 114 #else   /* !USE_DMA */
 115
 116 /* save a bit of code */
 117 #define use_dma         0
 118 #endif  /* !USE_DMA */
 119
 120
 121 static const char driver_name [] = "omap_udc";
 122 static const char driver_desc [] = DRIVER_DESC;
 123
 124 /*-------------------------------------------------------------------------*/
 125
 126 /* there's a notion of "current endpoint" for modifying endpoint
 127  * state, and PIO access to its FIFO.
 128  */
 129
 130 static void use_ep(struct omap_ep *ep, u16 select)
 131 {
 132         u16     num = ep->bEndpointAddress & 0x0f;
 133
 134         if (ep->bEndpointAddress & USB_DIR_IN)
 135                 num |= UDC_EP_DIR;
 136         UDC_EP_NUM_REG = num | select;
 137         /* when select, MUST deselect later !! */
 138 }
 139
 140 static inline void deselect_ep(void)
 141 {
 142         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
 143         /* 6 wait states before TX will happen */
 144 }
 145
 146 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 147
 148 /*-------------------------------------------------------------------------*/
 149
 150 static int omap_ep_enable(struct usb_ep *_ep,
 151                 const struct usb_endpoint_descriptor *desc)
 152 {
 153         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 154         struct omap_udc *udc;
 155         unsigned long   flags;
 156         u16             maxp;
 157
 158         /* catch various bogus parameters */
 159         if (!_ep || !desc || ep->desc
 160                         || desc->bDescriptorType != USB_DT_ENDPOINT
 161                         || ep->bEndpointAddress != desc->bEndpointAddress
 162                         || ep->maxpacket < le16_to_cpu
 163                                                 (desc->wMaxPacketSize)) {
 164                 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
 165                 return -EINVAL;
 166         }
 167         maxp = le16_to_cpu (desc->wMaxPacketSize);
 168         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 169                                 && maxp != ep->maxpacket)
 170                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 171                         || !desc->wMaxPacketSize) {
 172                 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 173                 return -ERANGE;
 174         }
 175
 176 #ifdef  USE_ISO
 177         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 178                                 && desc->bInterval != 1)) {
 179                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 180                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 181                                 1 << (desc->bInterval - 1));
 182                 return -EDOM;
 183         }
 184 #else
 185         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 186                 DBG("%s, ISO nyet\n", _ep->name);
 187                 return -EDOM;
 188         }
 189 #endif
 190
 191         /* xfer types must match, except that interrupt ~= bulk */
 192         if (ep->bmAttributes != desc->bmAttributes
 193                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 194                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 195                 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 196                 return -EINVAL;
 197         }
 198
 199         udc = ep->udc;
 200         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 201                 DBG("%s, bogus device state\n", __FUNCTION__);
 202                 return -ESHUTDOWN;
 203         }
 204
 205         spin_lock_irqsave(&udc->lock, flags);
 206
 207         ep->desc = desc;
 208         ep->irqs = 0;
 209         ep->stopped = 0;
 210         ep->ep.maxpacket = maxp;
 211
 212         /* set endpoint to initial state */
 213         ep->dma_channel = 0;
 214         ep->has_dma = 0;
 215         ep->lch = -1;
 216         use_ep(ep, UDC_EP_SEL);
 217         UDC_CTRL_REG = udc->clr_halt;
 218         ep->ackwait = 0;
 219         deselect_ep();
 220
 221         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 222                 list_add(&ep->iso, &udc->iso);
 223
 224         /* maybe assign a DMA channel to this endpoint */
 225         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 226                 /* FIXME ISO can dma, but prefers first channel */
 227                 dma_channel_claim(ep, 0);
 228
 229         /* PIO OUT may RX packets */
 230         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 231                         && !ep->has_dma
 232                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 233                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 234                 ep->ackwait = 1 + ep->double_buf;
 235         }
 236
 237         spin_unlock_irqrestore(&udc->lock, flags);
 238         VDBG("%s enabled\n", _ep->name);
 239         return 0;
 240 }
 241
 242 static void nuke(struct omap_ep *, int status);
 243
 244 static int omap_ep_disable(struct usb_ep *_ep)
 245 {
 246         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 247         unsigned long   flags;
 248
 249         if (!_ep || !ep->desc) {
 250                 DBG("%s, %s not enabled\n", __FUNCTION__,
 251                         _ep ? ep->ep.name : NULL);
 252                 return -EINVAL;
 253         }
 254
 255         spin_lock_irqsave(&ep->udc->lock, flags);
 256         ep->desc = NULL;
 257         nuke (ep, -ESHUTDOWN);
 258         ep->ep.maxpacket = ep->maxpacket;
 259         ep->has_dma = 0;
 260         UDC_CTRL_REG = UDC_SET_HALT;
 261         list_del_init(&ep->iso);
 262         del_timer(&ep->timer);
 263
 264         spin_unlock_irqrestore(&ep->udc->lock, flags);
 265
 266         VDBG("%s disabled\n", _ep->name);
 267         return 0;
 268 }
 269
 270 /*-------------------------------------------------------------------------*/
 271
 272 static struct usb_request *
 273 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 274 {
 275         struct omap_req *req;
 276
 277         req = kmalloc(sizeof *req, gfp_flags);
 278         if (req) {
 279                 memset (req, 0, sizeof *req);
 280                 req->req.dma = DMA_ADDR_INVALID;
 281                 INIT_LIST_HEAD (&req->queue);
 282         }
 283         return &req->req;
 284 }
 285
 286 static void
 287 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 288 {
 289         struct omap_req *req = container_of(_req, struct omap_req, req);
 290
 291         if (_req)
 292                 kfree (req);
 293 }
 294
 295 /*-------------------------------------------------------------------------*/
 296
 297 static void *
 298 omap_alloc_buffer(
 299         struct usb_ep   *_ep,
 300         unsigned        bytes,
 301         dma_addr_t      *dma,
 302         gfp_t           gfp_flags
 303 )
 304 {
 305         void            *retval;
 306         struct omap_ep  *ep;
 307
 308         ep = container_of(_ep, struct omap_ep, ep);
 309         if (use_dma && ep->has_dma) {
 310                 static int      warned;
 311                 if (!warned && bytes < PAGE_SIZE) {
 312                         dev_warn(ep->udc->gadget.dev.parent,
 313                                 "using dma_alloc_coherent for "
 314                                 "small allocations wastes memory\n");
 315                         warned++;
 316                 }
 317                 return dma_alloc_coherent(ep->udc->gadget.dev.parent,
 318                                 bytes, dma, gfp_flags);
 319         }
 320
 321         retval = kmalloc(bytes, gfp_flags);
 322         if (retval)
 323                 *dma = virt_to_phys(retval);
 324         return retval;
 325 }
 326
 327 static void omap_free_buffer(
 328         struct usb_ep   *_ep,
 329         void            *buf,
 330         dma_addr_t      dma,
 331         unsigned        bytes
 332 )
 333 {
 334         struct omap_ep  *ep;
 335
 336         ep = container_of(_ep, struct omap_ep, ep);
 337         if (use_dma && _ep && ep->has_dma)
 338                 dma_free_coherent(ep->udc->gadget.dev.parent, bytes, buf, dma);
 339         else
 340                 kfree (buf);
 341 }
 342
 343 /*-------------------------------------------------------------------------*/
 344
 345 static void
 346 done(struct omap_ep *ep, struct omap_req *req, int status)
 347 {
 348         unsigned                stopped = ep->stopped;
 349
 350         list_del_init(&req->queue);
 351
 352         if (req->req.status == -EINPROGRESS)
 353                 req->req.status = status;
 354         else
 355                 status = req->req.status;
 356
 357         if (use_dma && ep->has_dma) {
 358                 if (req->mapped) {
 359                         dma_unmap_single(ep->udc->gadget.dev.parent,
 360                                 req->req.dma, req->req.length,
 361                                 (ep->bEndpointAddress & USB_DIR_IN)
 362                                         ? DMA_TO_DEVICE
 363                                         : DMA_FROM_DEVICE);
 364                         req->req.dma = DMA_ADDR_INVALID;
 365                         req->mapped = 0;
 366                 } else
 367                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 368                                 req->req.dma, req->req.length,
 369                                 (ep->bEndpointAddress & USB_DIR_IN)
 370                                         ? DMA_TO_DEVICE
 371                                         : DMA_FROM_DEVICE);
 372         }
 373
 374 #ifndef USB_TRACE
 375         if (status && status != -ESHUTDOWN)
 376 #endif
 377                 VDBG("complete %s req %p stat %d len %u/%u\n",
 378                         ep->ep.name, &req->req, status,
 379                         req->req.actual, req->req.length);
 380
 381         /* don't modify queue heads during completion callback */
 382         ep->stopped = 1;
 383         spin_unlock(&ep->udc->lock);
 384         req->req.complete(&ep->ep, &req->req);
 385         spin_lock(&ep->udc->lock);
 386         ep->stopped = stopped;
 387 }
 388
 389 /*-------------------------------------------------------------------------*/
 390
 391 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 392 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 393
 394 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 395 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 396
 397 static inline int
 398 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 399 {
 400         unsigned        len;
 401         u16             *wp;
 402
 403         len = min(req->req.length - req->req.actual, max);
 404         req->req.actual += len;
 405
 406         max = len;
 407         if (likely((((int)buf) & 1) == 0)) {
 408                 wp = (u16 *)buf;
 409                 while (max >= 2) {
 410                         UDC_DATA_REG = *wp++;
 411                         max -= 2;
 412                 }
 413                 buf = (u8 *)wp;
 414         }
 415         while (max--)
 416                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
 417         return len;
 418 }
 419
 420 // FIXME change r/w fifo calling convention
 421
 422
 423 // return:  0 = still running, 1 = completed, negative = errno
 424 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 425 {
 426         u8              *buf;
 427         unsigned        count;
 428         int             is_last;
 429         u16             ep_stat;
 430
 431         buf = req->req.buf + req->req.actual;
 432         prefetch(buf);
 433
 434         /* PIO-IN isn't double buffered except for iso */
 435         ep_stat = UDC_STAT_FLG_REG;
 436         if (ep_stat & UDC_FIFO_UNWRITABLE)
 437                 return 0;
 438
 439         count = ep->ep.maxpacket;
 440         count = write_packet(buf, req, count);
 441         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 442         ep->ackwait = 1;
 443
 444         /* last packet is often short (sometimes a zlp) */
 445         if (count != ep->ep.maxpacket)
 446                 is_last = 1;
 447         else if (req->req.length == req->req.actual
 448                         && !req->req.zero)
 449                 is_last = 1;
 450         else
 451                 is_last = 0;
 452
 453         /* NOTE:  requests complete when all IN data is in a
 454          * FIFO (or sometimes later, if a zlp was needed).
 455          * Use usb_ep_fifo_status() where needed.
 456          */
 457         if (is_last)
 458                 done(ep, req, 0);
 459         return is_last;
 460 }
 461
 462 static inline int
 463 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 464 {
 465         unsigned        len;
 466         u16             *wp;
 467
 468         len = min(req->req.length - req->req.actual, avail);
 469         req->req.actual += len;
 470         avail = len;
 471
 472         if (likely((((int)buf) & 1) == 0)) {
 473                 wp = (u16 *)buf;
 474                 while (avail >= 2) {
 475                         *wp++ = UDC_DATA_REG;
 476                         avail -= 2;
 477                 }
 478                 buf = (u8 *)wp;
 479         }
 480         while (avail--)
 481                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
 482         return len;
 483 }
 484
 485 // return:  0 = still running, 1 = queue empty, negative = errno
 486 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 487 {
 488         u8              *buf;
 489         unsigned        count, avail;
 490         int             is_last;
 491
 492         buf = req->req.buf + req->req.actual;
 493         prefetchw(buf);
 494
 495         for (;;) {
 496                 u16     ep_stat = UDC_STAT_FLG_REG;
 497
 498                 is_last = 0;
 499                 if (ep_stat & FIFO_EMPTY) {
 500                         if (!ep->double_buf)
 501                                 break;
 502                         ep->fnf = 1;
 503                 }
 504                 if (ep_stat & UDC_EP_HALTED)
 505                         break;
 506
 507                 if (ep_stat & UDC_FIFO_FULL)
 508                         avail = ep->ep.maxpacket;
 509                 else  {
 510                         avail = UDC_RXFSTAT_REG;
 511                         ep->fnf = ep->double_buf;
 512                 }
 513                 count = read_packet(buf, req, avail);
 514
 515                 /* partial packet reads may not be errors */
 516                 if (count < ep->ep.maxpacket) {
 517                         is_last = 1;
 518                         /* overflowed this request?  flush extra data */
 519                         if (count != avail) {
 520                                 req->req.status = -EOVERFLOW;
 521                                 avail -= count;
 522                                 while (avail--)
 523                                         (void) *(volatile u8 *)&UDC_DATA_REG;
 524                         }
 525                 } else if (req->req.length == req->req.actual)
 526                         is_last = 1;
 527                 else
 528                         is_last = 0;
 529
 530                 if (!ep->bEndpointAddress)
 531                         break;
 532                 if (is_last)
 533                         done(ep, req, 0);
 534                 break;
 535         }
 536         return is_last;
 537 }
 538
 539 /*-------------------------------------------------------------------------*/
 540
 541 static inline dma_addr_t dma_csac(unsigned lch)
 542 {
 543         dma_addr_t      csac;
 544
 545         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 546          * read before the DMA controller finished disabling the channel.
 547          */
 548         csac = OMAP_DMA_CSAC_REG(lch);
 549         if (csac == 0)
 550                 csac = OMAP_DMA_CSAC_REG(lch);
 551         return csac;
 552 }
 553
 554 static inline dma_addr_t dma_cdac(unsigned lch)
 555 {
 556         dma_addr_t      cdac;
 557
 558         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 559          * read before the DMA controller finished disabling the channel.
 560          */
 561         cdac = OMAP_DMA_CDAC_REG(lch);
 562         if (cdac == 0)
 563                 cdac = OMAP_DMA_CDAC_REG(lch);
 564         return cdac;
 565 }
 566
 567 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 568 {
 569         dma_addr_t      end;
 570
 571         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 572          * the last transfer's bytecount by more than a FIFO's worth.
 573          */
 574         if (cpu_is_omap15xx())
 575                 return 0;
 576
 577         end = dma_csac(ep->lch);
 578         if (end == ep->dma_counter)
 579                 return 0;
 580
 581         end |= start & (0xffff << 16);
 582         if (end < start)
 583                 end += 0x10000;
 584         return end - start;
 585 }
 586
 587 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
 588                 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
 589                 : dma_cdac(x))
 590
 591 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 592 {
 593         dma_addr_t      end;
 594
 595         end = DMA_DEST_LAST(ep->lch);
 596         if (end == ep->dma_counter)
 597                 return 0;
 598
 599         end |= start & (0xffff << 16);
 600         if (cpu_is_omap15xx())
 601                 end++;
 602         if (end < start)
 603                 end += 0x10000;
 604         return end - start;
 605 }
 606
 607
 608 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 609  * When DMA completion isn't request completion, the UDC continues with
 610  * the next DMA transfer for that USB transfer.
 611  */
 612
 613 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 614 {
 615         u16             txdma_ctrl;
 616         unsigned        length = req->req.length - req->req.actual;
 617         const int       sync_mode = cpu_is_omap15xx()
 618                                 ? OMAP_DMA_SYNC_FRAME
 619                                 : OMAP_DMA_SYNC_ELEMENT;
 620
 621         /* measure length in either bytes or packets */
 622         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 623                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 624                 txdma_ctrl = UDC_TXN_EOT | length;
 625                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 626                                 length, 1, sync_mode, 0, 0);
 627         } else {
 628                 length = min(length / ep->maxpacket,
 629                                 (unsigned) UDC_TXN_TSC + 1);
 630                 txdma_ctrl = length;
 631                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 632                                 ep->ep.maxpacket >> 1, length, sync_mode,
 633                                 0, 0);
 634                 length *= ep->maxpacket;
 635         }
 636         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 637                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 638                 0, 0);
 639
 640         omap_start_dma(ep->lch);
 641         ep->dma_counter = dma_csac(ep->lch);
 642         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
 643         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
 644         req->dma_bytes = length;
 645 }
 646
 647 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 648 {
 649         if (status == 0) {
 650                 req->req.actual += req->dma_bytes;
 651
 652                 /* return if this request needs to send data or zlp */
 653                 if (req->req.actual < req->req.length)
 654                         return;
 655                 if (req->req.zero
 656                                 && req->dma_bytes != 0
 657                                 && (req->req.actual % ep->maxpacket) == 0)
 658                         return;
 659         } else
 660                 req->req.actual += dma_src_len(ep, req->req.dma
 661                                                         + req->req.actual);
 662
 663         /* tx completion */
 664         omap_stop_dma(ep->lch);
 665         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
 666         done(ep, req, status);
 667 }
 668
 669 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 670 {
 671         unsigned packets;
 672
 673         /* NOTE:  we filtered out "short reads" before, so we know
 674          * the buffer has only whole numbers of packets.
 675          */
 676
 677         /* set up this DMA transfer, enable the fifo, start */
 678         packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
 679         packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 680         req->dma_bytes = packets * ep->ep.maxpacket;
 681         omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 682                         ep->ep.maxpacket >> 1, packets,
 683                         OMAP_DMA_SYNC_ELEMENT,
 684                         0, 0);
 685         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 686                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 687                 0, 0);
 688         ep->dma_counter = DMA_DEST_LAST(ep->lch);
 689
 690         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
 691         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
 692         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
 693         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 694
 695         omap_start_dma(ep->lch);
 696 }
 697
 698 static void
 699 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 700 {
 701         u16     count;
 702
 703         if (status == 0)
 704                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 705         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 706         count += req->req.actual;
 707         if (one)
 708                 count--;
 709         if (count <= req->req.length)
 710                 req->req.actual = count;
 711
 712         if (count != req->dma_bytes || status)
 713                 omap_stop_dma(ep->lch);
 714
 715         /* if this wasn't short, request may need another transfer */
 716         else if (req->req.actual < req->req.length)
 717                 return;
 718
 719         /* rx completion */
 720         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
 721         done(ep, req, status);
 722 }
 723
 724 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 725 {
 726         u16             dman_stat = UDC_DMAN_STAT_REG;
 727         struct omap_ep  *ep;
 728         struct omap_req *req;
 729
 730         /* IN dma: tx to host */
 731         if (irq_src & UDC_TXN_DONE) {
 732                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 733                 ep->irqs++;
 734                 /* can see TXN_DONE after dma abort */
 735                 if (!list_empty(&ep->queue)) {
 736                         req = container_of(ep->queue.next,
 737                                                 struct omap_req, queue);
 738                         finish_in_dma(ep, req, 0);
 739                 }
 740                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
 741
 742                 if (!list_empty (&ep->queue)) {
 743                         req = container_of(ep->queue.next,
 744                                         struct omap_req, queue);
 745                         next_in_dma(ep, req);
 746                 }
 747         }
 748
 749         /* OUT dma: rx from host */
 750         if (irq_src & UDC_RXN_EOT) {
 751                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 752                 ep->irqs++;
 753                 /* can see RXN_EOT after dma abort */
 754                 if (!list_empty(&ep->queue)) {
 755                         req = container_of(ep->queue.next,
 756                                         struct omap_req, queue);
 757                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 758                 }
 759                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
 760
 761                 if (!list_empty (&ep->queue)) {
 762                         req = container_of(ep->queue.next,
 763                                         struct omap_req, queue);
 764                         next_out_dma(ep, req);
 765                 }
 766         }
 767
 768         if (irq_src & UDC_RXN_CNT) {
 769                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 770                 ep->irqs++;
 771                 /* omap15xx does this unasked... */
 772                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 773                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
 774         }
 775 }
 776
 777 static void dma_error(int lch, u16 ch_status, void *data)
 778 {
 779         struct omap_ep  *ep = data;
 780
 781         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 782         /* if ch_status & OMAP_DMA_TOUT_IRQ ... */
 783         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 784
 785         /* complete current transfer ... */
 786 }
 787
 788 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 789 {
 790         u16     reg;
 791         int     status, restart, is_in;
 792
 793         is_in = ep->bEndpointAddress & USB_DIR_IN;
 794         if (is_in)
 795                 reg = UDC_TXDMA_CFG_REG;
 796         else
 797                 reg = UDC_RXDMA_CFG_REG;
 798         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 799
 800         ep->dma_channel = 0;
 801         ep->lch = -1;
 802         if (channel == 0 || channel > 3) {
 803                 if ((reg & 0x0f00) == 0)
 804                         channel = 3;
 805                 else if ((reg & 0x00f0) == 0)
 806                         channel = 2;
 807                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 808                         channel = 1;
 809                 else {
 810                         status = -EMLINK;
 811                         goto just_restart;
 812                 }
 813         }
 814         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 815         ep->dma_channel = channel;
 816
 817         if (is_in) {
 818                 status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel,
 819                         ep->ep.name, dma_error, ep, &ep->lch);
 820                 if (status == 0) {
 821                         UDC_TXDMA_CFG_REG = reg;
 822                         /* EMIFF */
 823                         omap_set_dma_src_burst_mode(ep->lch,
 824                                                 OMAP_DMA_DATA_BURST_4);
 825                         omap_set_dma_src_data_pack(ep->lch, 1);
 826                         /* TIPB */
 827                         omap_set_dma_dest_params(ep->lch,
 828                                 OMAP_DMA_PORT_TIPB,
 829                                 OMAP_DMA_AMODE_CONSTANT,
 830                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 831                                 0, 0);
 832                 }
 833         } else {
 834                 status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
 835                         ep->ep.name, dma_error, ep, &ep->lch);
 836                 if (status == 0) {
 837                         UDC_RXDMA_CFG_REG = reg;
 838                         /* TIPB */
 839                         omap_set_dma_src_params(ep->lch,
 840                                 OMAP_DMA_PORT_TIPB,
 841                                 OMAP_DMA_AMODE_CONSTANT,
 842                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 843                                 0, 0);
 844                         /* EMIFF */
 845                         omap_set_dma_dest_burst_mode(ep->lch,
 846                                                 OMAP_DMA_DATA_BURST_4);
 847                         omap_set_dma_dest_data_pack(ep->lch, 1);
 848                 }
 849         }
 850         if (status)
 851                 ep->dma_channel = 0;
 852         else {
 853                 ep->has_dma = 1;
 854                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 855
 856                 /* channel type P: hw synch (fifo) */
 857                 if (!cpu_is_omap15xx())
 858                         OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
 859         }
 860
 861 just_restart:
 862         /* restart any queue, even if the claim failed  */
 863         restart = !ep->stopped && !list_empty(&ep->queue);
 864
 865         if (status)
 866                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 867                         restart ? " (restart)" : "");
 868         else
 869                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 870                         is_in ? 't' : 'r',
 871                         ep->dma_channel - 1, ep->lch,
 872                         restart ? " (restart)" : "");
 873
 874         if (restart) {
 875                 struct omap_req *req;
 876                 req = container_of(ep->queue.next, struct omap_req, queue);
 877                 if (ep->has_dma)
 878                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 879                 else {
 880                         use_ep(ep, UDC_EP_SEL);
 881                         (is_in ? write_fifo : read_fifo)(ep, req);
 882                         deselect_ep();
 883                         if (!is_in) {
 884                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 885                                 ep->ackwait = 1 + ep->double_buf;
 886                         }
 887                         /* IN: 6 wait states before it'll tx */
 888                 }
 889         }
 890 }
 891
 892 static void dma_channel_release(struct omap_ep *ep)
 893 {
 894         int             shift = 4 * (ep->dma_channel - 1);
 895         u16             mask = 0x0f << shift;
 896         struct omap_req *req;
 897         int             active;
 898
 899         /* abort any active usb transfer request */
 900         if (!list_empty(&ep->queue))
 901                 req = container_of(ep->queue.next, struct omap_req, queue);
 902         else
 903                 req = NULL;
 904
 905         active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
 906
 907         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 908                         active ? "active" : "idle",
 909                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 910                         ep->dma_channel - 1, req);
 911
 912         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 913          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 914          */
 915
 916         /* wait till current packet DMA finishes, and fifo empties */
 917         if (ep->bEndpointAddress & USB_DIR_IN) {
 918                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 919
 920                 if (req) {
 921                         finish_in_dma(ep, req, -ECONNRESET);
 922
 923                         /* clear FIFO; hosts probably won't empty it */
 924                         use_ep(ep, UDC_EP_SEL);
 925                         UDC_CTRL_REG = UDC_CLR_EP;
 926                         deselect_ep();
 927                 }
 928                 while (UDC_TXDMA_CFG_REG & mask)
 929                         udelay(10);
 930         } else {
 931                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 932
 933                 /* dma empties the fifo */
 934                 while (UDC_RXDMA_CFG_REG & mask)
 935                         udelay(10);
 936                 if (req)
 937                         finish_out_dma(ep, req, -ECONNRESET, 0);
 938         }
 939         omap_free_dma(ep->lch);
 940         ep->dma_channel = 0;
 941         ep->lch = -1;
 942         /* has_dma still set, till endpoint is fully quiesced */
 943 }
 944
 945
 946 /*-------------------------------------------------------------------------*/
 947
 948 static int
 949 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 950 {
 951         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 952         struct omap_req *req = container_of(_req, struct omap_req, req);
 953         struct omap_udc *udc;
 954         unsigned long   flags;
 955         int             is_iso = 0;
 956
 957         /* catch various bogus parameters */
 958         if (!_req || !req->req.complete || !req->req.buf
 959                         || !list_empty(&req->queue)) {
 960                 DBG("%s, bad params\n", __FUNCTION__);
 961                 return -EINVAL;
 962         }
 963         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
 964                 DBG("%s, bad ep\n", __FUNCTION__);
 965                 return -EINVAL;
 966         }
 967         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 968                 if (req->req.length > ep->ep.maxpacket)
 969                         return -EMSGSIZE;
 970                 is_iso = 1;
 971         }
 972
 973         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 974          * have a hard time with partial packet reads...  reject it.
 975          */
 976         if (use_dma
 977                         && ep->has_dma
 978                         && ep->bEndpointAddress != 0
 979                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 980                         && (req->req.length % ep->ep.maxpacket) != 0) {
 981                 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
 982                 return -EMSGSIZE;
 983         }
 984
 985         udc = ep->udc;
 986         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 987                 return -ESHUTDOWN;
 988
 989         if (use_dma && ep->has_dma) {
 990                 if (req->req.dma == DMA_ADDR_INVALID) {
 991                         req->req.dma = dma_map_single(
 992                                 ep->udc->gadget.dev.parent,
 993                                 req->req.buf,
 994                                 req->req.length,
 995                                 (ep->bEndpointAddress & USB_DIR_IN)
 996                                         ? DMA_TO_DEVICE
 997                                         : DMA_FROM_DEVICE);
 998                         req->mapped = 1;
 999                 } else {
1000                         dma_sync_single_for_device(
1001                                 ep->udc->gadget.dev.parent,
1002                                 req->req.dma, req->req.length,
1003                                 (ep->bEndpointAddress & USB_DIR_IN)
1004                                         ? DMA_TO_DEVICE
1005                                         : DMA_FROM_DEVICE);
1006                         req->mapped = 0;
1007                 }
1008         }
1009
1010         VDBG("%s queue req %p, len %d buf %p\n",
1011                 ep->ep.name, _req, _req->length, _req->buf);
1012
1013         spin_lock_irqsave(&udc->lock, flags);
1014
1015         req->req.status = -EINPROGRESS;
1016         req->req.actual = 0;
1017
1018         /* maybe kickstart non-iso i/o queues */
1019         if (is_iso)
1020                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
1021         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1022                 int     is_in;
1023
1024                 if (ep->bEndpointAddress == 0) {
1025                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1026                                 spin_unlock_irqrestore(&udc->lock, flags);
1027                                 return -EL2HLT;
1028                         }
1029
1030                         /* empty DATA stage? */
1031                         is_in = udc->ep0_in;
1032                         if (!req->req.length) {
1033
1034                                 /* chip became CONFIGURED or ADDRESSED
1035                                  * earlier; drivers may already have queued
1036                                  * requests to non-control endpoints
1037                                  */
1038                                 if (udc->ep0_set_config) {
1039                                         u16     irq_en = UDC_IRQ_EN_REG;
1040
1041                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1042                                         if (!udc->ep0_reset_config)
1043                                                 irq_en |= UDC_EPN_RX_IE
1044                                                         | UDC_EPN_TX_IE;
1045                                         UDC_IRQ_EN_REG = irq_en;
1046                                 }
1047
1048                                 /* STATUS for zero length DATA stages is
1049                                  * always an IN ... even for IN transfers,
1050                                  * a wierd case which seem to stall OMAP.
1051                                  */
1052                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1053                                 UDC_CTRL_REG = UDC_CLR_EP;
1054                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1055                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1056
1057                                 /* cleanup */
1058                                 udc->ep0_pending = 0;
1059                                 done(ep, req, 0);
1060                                 req = NULL;
1061
1062                         /* non-empty DATA stage */
1063                         } else if (is_in) {
1064                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1065                         } else {
1066                                 if (udc->ep0_setup)
1067                                         goto irq_wait;
1068                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1069                         }
1070                 } else {
1071                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1072                         if (!ep->has_dma)
1073                                 use_ep(ep, UDC_EP_SEL);
1074                         /* if ISO: SOF IRQs must be enabled/disabled! */
1075                 }
1076
1077                 if (ep->has_dma)
1078                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1079                 else if (req) {
1080                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1081                                 req = NULL;
1082                         deselect_ep();
1083                         if (!is_in) {
1084                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1085                                 ep->ackwait = 1 + ep->double_buf;
1086                         }
1087                         /* IN: 6 wait states before it'll tx */
1088                 }
1089         }
1090
1091 irq_wait:
1092         /* irq handler advances the queue */
1093         if (req != NULL)
1094                 list_add_tail(&req->queue, &ep->queue);
1095         spin_unlock_irqrestore(&udc->lock, flags);
1096
1097         return 0;
1098 }
1099
1100 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1101 {
1102         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1103         struct omap_req *req;
1104         unsigned long   flags;
1105
1106         if (!_ep || !_req)
1107                 return -EINVAL;
1108
1109         spin_lock_irqsave(&ep->udc->lock, flags);
1110
1111         /* make sure it's actually queued on this endpoint */
1112         list_for_each_entry (req, &ep->queue, queue) {
1113                 if (&req->req == _req)
1114                         break;
1115         }
1116         if (&req->req != _req) {
1117                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1118                 return -EINVAL;
1119         }
1120
1121         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1122                 int channel = ep->dma_channel;
1123
1124                 /* releasing the channel cancels the request,
1125                  * reclaiming the channel restarts the queue
1126                  */
1127                 dma_channel_release(ep);
1128                 dma_channel_claim(ep, channel);
1129         } else
1130                 done(ep, req, -ECONNRESET);
1131         spin_unlock_irqrestore(&ep->udc->lock, flags);
1132         return 0;
1133 }
1134
1135 /*-------------------------------------------------------------------------*/
1136
1137 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1138 {
1139         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1140         unsigned long   flags;
1141         int             status = -EOPNOTSUPP;
1142
1143         spin_lock_irqsave(&ep->udc->lock, flags);
1144
1145         /* just use protocol stalls for ep0; real halts are annoying */
1146         if (ep->bEndpointAddress == 0) {
1147                 if (!ep->udc->ep0_pending)
1148                         status = -EINVAL;
1149                 else if (value) {
1150                         if (ep->udc->ep0_set_config) {
1151                                 WARN("error changing config?\n");
1152                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1153                         }
1154                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1155                         ep->udc->ep0_pending = 0;
1156                         status = 0;
1157                 } else /* NOP */
1158                         status = 0;
1159
1160         /* otherwise, all active non-ISO endpoints can halt */
1161         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1162
1163                 /* IN endpoints must already be idle */
1164                 if ((ep->bEndpointAddress & USB_DIR_IN)
1165                                 && !list_empty(&ep->queue)) {
1166                         status = -EAGAIN;
1167                         goto done;
1168                 }
1169
1170                 if (value) {
1171                         int     channel;
1172
1173                         if (use_dma && ep->dma_channel
1174                                         && !list_empty(&ep->queue)) {
1175                                 channel = ep->dma_channel;
1176                                 dma_channel_release(ep);
1177                         } else
1178                                 channel = 0;
1179
1180                         use_ep(ep, UDC_EP_SEL);
1181                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1182                                 UDC_CTRL_REG = UDC_SET_HALT;
1183                                 status = 0;
1184                         } else
1185                                 status = -EAGAIN;
1186                         deselect_ep();
1187
1188                         if (channel)
1189                                 dma_channel_claim(ep, channel);
1190                 } else {
1191                         use_ep(ep, 0);
1192                         UDC_CTRL_REG = ep->udc->clr_halt;
1193                         ep->ackwait = 0;
1194                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1195                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1196                                 ep->ackwait = 1 + ep->double_buf;
1197                         }
1198                 }
1199         }
1200 done:
1201         VDBG("%s %s halt stat %d\n", ep->ep.name,
1202                 value ? "set" : "clear", status);
1203
1204         spin_unlock_irqrestore(&ep->udc->lock, flags);
1205         return status;
1206 }
1207
1208 static struct usb_ep_ops omap_ep_ops = {
1209         .enable         = omap_ep_enable,
1210         .disable        = omap_ep_disable,
1211
1212         .alloc_request  = omap_alloc_request,
1213         .free_request   = omap_free_request,
1214
1215         .alloc_buffer   = omap_alloc_buffer,
1216         .free_buffer    = omap_free_buffer,
1217
1218         .queue          = omap_ep_queue,
1219         .dequeue        = omap_ep_dequeue,
1220
1221         .set_halt       = omap_ep_set_halt,
1222         // fifo_status ... report bytes in fifo
1223         // fifo_flush ... flush fifo
1224 };
1225
1226 /*-------------------------------------------------------------------------*/
1227
1228 static int omap_get_frame(struct usb_gadget *gadget)
1229 {
1230         u16     sof = UDC_SOF_REG;
1231         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1232 }
1233
1234 static int omap_wakeup(struct usb_gadget *gadget)
1235 {
1236         struct omap_udc *udc;
1237         unsigned long   flags;
1238         int             retval = -EHOSTUNREACH;
1239
1240         udc = container_of(gadget, struct omap_udc, gadget);
1241
1242         spin_lock_irqsave(&udc->lock, flags);
1243         if (udc->devstat & UDC_SUS) {
1244                 /* NOTE:  OTG spec erratum says that OTG devices may
1245                  * issue wakeups without host enable.
1246                  */
1247                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1248                         DBG("remote wakeup...\n");
1249                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1250                         retval = 0;
1251                 }
1252
1253         /* NOTE:  non-OTG systems may use SRP TOO... */
1254         } else if (!(udc->devstat & UDC_ATT)) {
1255                 if (udc->transceiver)
1256                         retval = otg_start_srp(udc->transceiver);
1257         }
1258         spin_unlock_irqrestore(&udc->lock, flags);
1259
1260         return retval;
1261 }
1262
1263 static int
1264 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1265 {
1266         struct omap_udc *udc;
1267         unsigned long   flags;
1268         u16             syscon1;
1269
1270         udc = container_of(gadget, struct omap_udc, gadget);
1271         spin_lock_irqsave(&udc->lock, flags);
1272         syscon1 = UDC_SYSCON1_REG;
1273         if (is_selfpowered)
1274                 syscon1 |= UDC_SELF_PWR;
1275         else
1276                 syscon1 &= ~UDC_SELF_PWR;
1277         UDC_SYSCON1_REG = syscon1;
1278         spin_unlock_irqrestore(&udc->lock, flags);
1279
1280         return 0;
1281 }
1282
1283 static int can_pullup(struct omap_udc *udc)
1284 {
1285         return udc->driver && udc->softconnect && udc->vbus_active;
1286 }
1287
1288 static void pullup_enable(struct omap_udc *udc)
1289 {
1290         udc->gadget.dev.parent->power.power_state = PMSG_ON;
1291         udc->gadget.dev.power.power_state = PMSG_ON;
1292         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1293 #ifndef CONFIG_USB_OTG
1294         if (!cpu_is_omap15xx())
1295                 OTG_CTRL_REG |= OTG_BSESSVLD;
1296 #endif
1297         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1298 }
1299
1300 static void pullup_disable(struct omap_udc *udc)
1301 {
1302 #ifndef CONFIG_USB_OTG
1303         if (!cpu_is_omap15xx())
1304                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1305 #endif
1306         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1307         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1308 }
1309
1310 static struct omap_udc *udc;
1311
1312 static void omap_udc_enable_clock(int enable)
1313 {
1314         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1315                 return;
1316
1317         if (enable) {
1318                 clk_enable(udc->dc_clk);
1319                 clk_enable(udc->hhc_clk);
1320                 udelay(100);
1321         } else {
1322                 clk_disable(udc->hhc_clk);
1323                 clk_disable(udc->dc_clk);
1324         }
1325 }
1326
1327 /*
1328  * Called by whatever detects VBUS sessions:  external transceiver
1329  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1330  */
1331 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1332 {
1333         struct omap_udc *udc;
1334         unsigned long   flags;
1335
1336         udc = container_of(gadget, struct omap_udc, gadget);
1337         spin_lock_irqsave(&udc->lock, flags);
1338         VDBG("VBUS %s\n", is_active ? "on" : "off");
1339         udc->vbus_active = (is_active != 0);
1340         if (cpu_is_omap15xx()) {
1341                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1342                 if (is_active)
1343                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1344                 else
1345                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1346         }
1347         if (udc->dc_clk != NULL && is_active) {
1348                 if (!udc->clk_requested) {
1349                         omap_udc_enable_clock(1);
1350                         udc->clk_requested = 1;
1351                 }
1352         }
1353         if (can_pullup(udc))
1354                 pullup_enable(udc);
1355         else
1356                 pullup_disable(udc);
1357         if (udc->dc_clk != NULL && !is_active) {
1358                 if (udc->clk_requested) {
1359                         omap_udc_enable_clock(0);
1360                         udc->clk_requested = 0;
1361                 }
1362         }
1363         spin_unlock_irqrestore(&udc->lock, flags);
1364         return 0;
1365 }
1366
1367 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1368 {
1369         struct omap_udc *udc;
1370
1371         udc = container_of(gadget, struct omap_udc, gadget);
1372         if (udc->transceiver)
1373                 return otg_set_power(udc->transceiver, mA);
1374         return -EOPNOTSUPP;
1375 }
1376
1377 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1378 {
1379         struct omap_udc *udc;
1380         unsigned long   flags;
1381
1382         udc = container_of(gadget, struct omap_udc, gadget);
1383         spin_lock_irqsave(&udc->lock, flags);
1384         udc->softconnect = (is_on != 0);
1385         if (can_pullup(udc))
1386                 pullup_enable(udc);
1387         else
1388                 pullup_disable(udc);
1389         spin_unlock_irqrestore(&udc->lock, flags);
1390         return 0;
1391 }
1392
1393 static struct usb_gadget_ops omap_gadget_ops = {
1394         .get_frame              = omap_get_frame,
1395         .wakeup                 = omap_wakeup,
1396         .set_selfpowered        = omap_set_selfpowered,
1397         .vbus_session           = omap_vbus_session,
1398         .vbus_draw              = omap_vbus_draw,
1399         .pullup                 = omap_pullup,
1400 };
1401
1402 /*-------------------------------------------------------------------------*/
1403
1404 /* dequeue ALL requests; caller holds udc->lock */
1405 static void nuke(struct omap_ep *ep, int status)
1406 {
1407         struct omap_req *req;
1408
1409         ep->stopped = 1;
1410
1411         if (use_dma && ep->dma_channel)
1412                 dma_channel_release(ep);
1413
1414         use_ep(ep, 0);
1415         UDC_CTRL_REG = UDC_CLR_EP;
1416         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1417                 UDC_CTRL_REG = UDC_SET_HALT;
1418
1419         while (!list_empty(&ep->queue)) {
1420                 req = list_entry(ep->queue.next, struct omap_req, queue);
1421                 done(ep, req, status);
1422         }
1423 }
1424
1425 /* caller holds udc->lock */
1426 static void udc_quiesce(struct omap_udc *udc)
1427 {
1428         struct omap_ep  *ep;
1429
1430         udc->gadget.speed = USB_SPEED_UNKNOWN;
1431         nuke(&udc->ep[0], -ESHUTDOWN);
1432         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1433                 nuke(ep, -ESHUTDOWN);
1434 }
1435
1436 /*-------------------------------------------------------------------------*/
1437
1438 static void update_otg(struct omap_udc *udc)
1439 {
1440         u16     devstat;
1441
1442         if (!udc->gadget.is_otg)
1443                 return;
1444
1445         if (OTG_CTRL_REG & OTG_ID)
1446                 devstat = UDC_DEVSTAT_REG;
1447         else
1448                 devstat = 0;
1449
1450         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1451         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1452         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1453
1454         /* Enable HNP early, avoiding races on suspend irq path.
1455          * ASSUMES OTG state machine B_BUS_REQ input is true.
1456          */
1457         if (udc->gadget.b_hnp_enable)
1458                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1459                                 & ~OTG_PULLUP;
1460 }
1461
1462 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1463 {
1464         struct omap_ep  *ep0 = &udc->ep[0];
1465         struct omap_req *req = NULL;
1466
1467         ep0->irqs++;
1468
1469         /* Clear any pending requests and then scrub any rx/tx state
1470          * before starting to handle the SETUP request.
1471          */
1472         if (irq_src & UDC_SETUP) {
1473                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1474
1475                 nuke(ep0, 0);
1476                 if (ack) {
1477                         UDC_IRQ_SRC_REG = ack;
1478                         irq_src = UDC_SETUP;
1479                 }
1480         }
1481
1482         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1483          * This driver uses only uses protocol stalls (ep0 never halts),
1484          * and if we got this far the gadget driver already had a
1485          * chance to stall.  Tries to be forgiving of host oddities.
1486          *
1487          * NOTE:  the last chance gadget drivers have to stall control
1488          * requests is during their request completion callback.
1489          */
1490         if (!list_empty(&ep0->queue))
1491                 req = container_of(ep0->queue.next, struct omap_req, queue);
1492
1493         /* IN == TX to host */
1494         if (irq_src & UDC_EP0_TX) {
1495                 int     stat;
1496
1497                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1498                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1499                 stat = UDC_STAT_FLG_REG;
1500                 if (stat & UDC_ACK) {
1501                         if (udc->ep0_in) {
1502                                 /* write next IN packet from response,
1503                                  * or set up the status stage.
1504                                  */
1505                                 if (req)
1506                                         stat = write_fifo(ep0, req);
1507                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1508                                 if (!req && udc->ep0_pending) {
1509                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1510                                         UDC_CTRL_REG = UDC_CLR_EP;
1511                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1512                                         UDC_EP_NUM_REG = 0;
1513                                         udc->ep0_pending = 0;
1514                                 } /* else:  6 wait states before it'll tx */
1515                         } else {
1516                                 /* ack status stage of OUT transfer */
1517                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1518                                 if (req)
1519                                         done(ep0, req, 0);
1520                         }
1521                         req = NULL;
1522                 } else if (stat & UDC_STALL) {
1523                         UDC_CTRL_REG = UDC_CLR_HALT;
1524                         UDC_EP_NUM_REG = UDC_EP_DIR;
1525                 } else {
1526                         UDC_EP_NUM_REG = UDC_EP_DIR;
1527                 }
1528         }
1529
1530         /* OUT == RX from host */
1531         if (irq_src & UDC_EP0_RX) {
1532                 int     stat;
1533
1534                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1535                 UDC_EP_NUM_REG = UDC_EP_SEL;
1536                 stat = UDC_STAT_FLG_REG;
1537                 if (stat & UDC_ACK) {
1538                         if (!udc->ep0_in) {
1539                                 stat = 0;
1540                                 /* read next OUT packet of request, maybe
1541                                  * reactiviting the fifo; stall on errors.
1542                                  */
1543                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1544                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1545                                         udc->ep0_pending = 0;
1546                                         stat = 0;
1547                                 } else if (stat == 0)
1548                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1549                                 UDC_EP_NUM_REG = 0;
1550
1551                                 /* activate status stage */
1552                                 if (stat == 1) {
1553                                         done(ep0, req, 0);
1554                                         /* that may have STALLed ep0... */
1555                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1556                                         UDC_CTRL_REG = UDC_CLR_EP;
1557                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1558                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1559                                         udc->ep0_pending = 0;
1560                                 }
1561                         } else {
1562                                 /* ack status stage of IN transfer */
1563                                 UDC_EP_NUM_REG = 0;
1564                                 if (req)
1565                                         done(ep0, req, 0);
1566                         }
1567                 } else if (stat & UDC_STALL) {
1568                         UDC_CTRL_REG = UDC_CLR_HALT;
1569                         UDC_EP_NUM_REG = 0;
1570                 } else {
1571                         UDC_EP_NUM_REG = 0;
1572                 }
1573         }
1574
1575         /* SETUP starts all control transfers */
1576         if (irq_src & UDC_SETUP) {
1577                 union u {
1578                         u16                     word[4];
1579                         struct usb_ctrlrequest  r;
1580                 } u;
1581                 int                     status = -EINVAL;
1582                 struct omap_ep          *ep;
1583
1584                 /* read the (latest) SETUP message */
1585                 do {
1586                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1587                         /* two bytes at a time */
1588                         u.word[0] = UDC_DATA_REG;
1589                         u.word[1] = UDC_DATA_REG;
1590                         u.word[2] = UDC_DATA_REG;
1591                         u.word[3] = UDC_DATA_REG;
1592                         UDC_EP_NUM_REG = 0;
1593                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1594
1595 #define w_value         le16_to_cpup (&u.r.wValue)
1596 #define w_index         le16_to_cpup (&u.r.wIndex)
1597 #define w_length        le16_to_cpup (&u.r.wLength)
1598
1599                 /* Delegate almost all control requests to the gadget driver,
1600                  * except for a handful of ch9 status/feature requests that
1601                  * hardware doesn't autodecode _and_ the gadget API hides.
1602                  */
1603                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1604                 udc->ep0_set_config = 0;
1605                 udc->ep0_pending = 1;
1606                 ep0->stopped = 0;
1607                 ep0->ackwait = 0;
1608                 switch (u.r.bRequest) {
1609                 case USB_REQ_SET_CONFIGURATION:
1610                         /* udc needs to know when ep != 0 is valid */
1611                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1612                                 goto delegate;
1613                         if (w_length != 0)
1614                                 goto do_stall;
1615                         udc->ep0_set_config = 1;
1616                         udc->ep0_reset_config = (w_value == 0);
1617                         VDBG("set config %d\n", w_value);
1618
1619                         /* update udc NOW since gadget driver may start
1620                          * queueing requests immediately; clear config
1621                          * later if it fails the request.
1622                          */
1623                         if (udc->ep0_reset_config)
1624                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1625                         else
1626                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1627                         update_otg(udc);
1628                         goto delegate;
1629                 case USB_REQ_CLEAR_FEATURE:
1630                         /* clear endpoint halt */
1631                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1632                                 goto delegate;
1633                         if (w_value != USB_ENDPOINT_HALT
1634                                         || w_length != 0)
1635                                 goto do_stall;
1636                         ep = &udc->ep[w_index & 0xf];
1637                         if (ep != ep0) {
1638                                 if (w_index & USB_DIR_IN)
1639                                         ep += 16;
1640                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1641                                                 || !ep->desc)
1642                                         goto do_stall;
1643                                 use_ep(ep, 0);
1644                                 UDC_CTRL_REG = udc->clr_halt;
1645                                 ep->ackwait = 0;
1646                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1647                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1648                                         ep->ackwait = 1 + ep->double_buf;
1649                                 }
1650                                 /* NOTE:  assumes the host behaves sanely,
1651                                  * only clearing real halts.  Else we may
1652                                  * need to kill pending transfers and then
1653                                  * restart the queue... very messy for DMA!
1654                                  */
1655                         }
1656                         VDBG("%s halt cleared by host\n", ep->name);
1657                         goto ep0out_status_stage;
1658                 case USB_REQ_SET_FEATURE:
1659                         /* set endpoint halt */
1660                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1661                                 goto delegate;
1662                         if (w_value != USB_ENDPOINT_HALT
1663                                         || w_length != 0)
1664                                 goto do_stall;
1665                         ep = &udc->ep[w_index & 0xf];
1666                         if (w_index & USB_DIR_IN)
1667                                 ep += 16;
1668                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1669                                         || ep == ep0 || !ep->desc)
1670                                 goto do_stall;
1671                         if (use_dma && ep->has_dma) {
1672                                 /* this has rude side-effects (aborts) and
1673                                  * can't really work if DMA-IN is active
1674                                  */
1675                                 DBG("%s host set_halt, NYET \n", ep->name);
1676                                 goto do_stall;
1677                         }
1678                         use_ep(ep, 0);
1679                         /* can't halt if fifo isn't empty... */
1680                         UDC_CTRL_REG = UDC_CLR_EP;
1681                         UDC_CTRL_REG = UDC_SET_HALT;
1682                         VDBG("%s halted by host\n", ep->name);
1683 ep0out_status_stage:
1684                         status = 0;
1685                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1686                         UDC_CTRL_REG = UDC_CLR_EP;
1687                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1688                         UDC_EP_NUM_REG = UDC_EP_DIR;
1689                         udc->ep0_pending = 0;
1690                         break;
1691                 case USB_REQ_GET_STATUS:
1692                         /* return interface status.  if we were pedantic,
1693                          * we'd detect non-existent interfaces, and stall.
1694                          */
1695                         if (u.r.bRequestType
1696                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1697                                 goto delegate;
1698                         /* return two zero bytes */
1699                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1700                         UDC_DATA_REG = 0;
1701                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1702                         UDC_EP_NUM_REG = UDC_EP_DIR;
1703                         status = 0;
1704                         VDBG("GET_STATUS, interface %d\n", w_index);
1705                         /* next, status stage */
1706                         break;
1707                 default:
1708 delegate:
1709                         /* activate the ep0out fifo right away */
1710                         if (!udc->ep0_in && w_length) {
1711                                 UDC_EP_NUM_REG = 0;
1712                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1713                         }
1714
1715                         /* gadget drivers see class/vendor specific requests,
1716                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1717                          * and more
1718                          */
1719                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1720                                 u.r.bRequestType, u.r.bRequest,
1721                                 w_value, w_index, w_length);
1722
1723 #undef  w_value
1724 #undef  w_index
1725 #undef  w_length
1726
1727                         /* The gadget driver may return an error here,
1728                          * causing an immediate protocol stall.
1729                          *
1730                          * Else it must issue a response, either queueing a
1731                          * response buffer for the DATA stage, or halting ep0
1732                          * (causing a protocol stall, not a real halt).  A
1733                          * zero length buffer means no DATA stage.
1734                          *
1735                          * It's fine to issue that response after the setup()
1736                          * call returns, and this IRQ was handled.
1737                          */
1738                         udc->ep0_setup = 1;
1739                         spin_unlock(&udc->lock);
1740                         status = udc->driver->setup (&udc->gadget, &u.r);
1741                         spin_lock(&udc->lock);
1742                         udc->ep0_setup = 0;
1743                 }
1744
1745                 if (status < 0) {
1746 do_stall:
1747                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1748                                         u.r.bRequestType, u.r.bRequest, status);
1749                         if (udc->ep0_set_config) {
1750                                 if (udc->ep0_reset_config)
1751                                         WARN("error resetting config?\n");
1752                                 else
1753                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1754                         }
1755                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1756                         udc->ep0_pending = 0;
1757                 }
1758         }
1759 }
1760
1761 /*-------------------------------------------------------------------------*/
1762
1763 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1764
1765 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1766 {
1767         u16     devstat, change;
1768
1769         devstat = UDC_DEVSTAT_REG;
1770         change = devstat ^ udc->devstat;
1771         udc->devstat = devstat;
1772
1773         if (change & (UDC_USB_RESET|UDC_ATT)) {
1774                 udc_quiesce(udc);
1775
1776                 if (change & UDC_ATT) {
1777                         /* driver for any external transceiver will
1778                          * have called omap_vbus_session() already
1779                          */
1780                         if (devstat & UDC_ATT) {
1781                                 udc->gadget.speed = USB_SPEED_FULL;
1782                                 VDBG("connect\n");
1783                                 if (!udc->transceiver)
1784                                         pullup_enable(udc);
1785                                 // if (driver->connect) call it
1786                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1787                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1788                                 if (!udc->transceiver)
1789                                         pullup_disable(udc);
1790                                 DBG("disconnect, gadget %s\n",
1791                                         udc->driver->driver.name);
1792                                 if (udc->driver->disconnect) {
1793                                         spin_unlock(&udc->lock);
1794                                         udc->driver->disconnect(&udc->gadget);
1795                                         spin_lock(&udc->lock);
1796                                 }
1797                         }
1798                         change &= ~UDC_ATT;
1799                 }
1800
1801                 if (change & UDC_USB_RESET) {
1802                         if (devstat & UDC_USB_RESET) {
1803                                 VDBG("RESET=1\n");
1804                         } else {
1805                                 udc->gadget.speed = USB_SPEED_FULL;
1806                                 INFO("USB reset done, gadget %s\n",
1807                                         udc->driver->driver.name);
1808                                 /* ep0 traffic is legal from now on */
1809                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1810                         }
1811                         change &= ~UDC_USB_RESET;
1812                 }
1813         }
1814         if (change & UDC_SUS) {
1815                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1816                         // FIXME tell isp1301 to suspend/resume (?)
1817                         if (devstat & UDC_SUS) {
1818                                 VDBG("suspend\n");
1819                                 update_otg(udc);
1820                                 /* HNP could be under way already */
1821                                 if (udc->gadget.speed == USB_SPEED_FULL
1822                                                 && udc->driver->suspend) {
1823                                         spin_unlock(&udc->lock);
1824                                         udc->driver->suspend(&udc->gadget);
1825                                         spin_lock(&udc->lock);
1826                                 }
1827                                 if (udc->transceiver)
1828                                         otg_set_suspend(udc->transceiver, 1);
1829                         } else {
1830                                 VDBG("resume\n");
1831                                 if (udc->transceiver)
1832                                         otg_set_suspend(udc->transceiver, 0);
1833                                 if (udc->gadget.speed == USB_SPEED_FULL
1834                                                 && udc->driver->resume) {
1835                                         spin_unlock(&udc->lock);
1836                                         udc->driver->resume(&udc->gadget);
1837                                         spin_lock(&udc->lock);
1838                                 }
1839                         }
1840                 }
1841                 change &= ~UDC_SUS;
1842         }
1843         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1844                 update_otg(udc);
1845                 change &= ~OTG_FLAGS;
1846         }
1847
1848         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1849         if (change)
1850                 VDBG("devstat %03x, ignore change %03x\n",
1851                         devstat,  change);
1852
1853         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1854 }
1855
1856 static irqreturn_t
1857 omap_udc_irq(int irq, void *_udc, struct pt_regs *r)
1858 {
1859         struct omap_udc *udc = _udc;
1860         u16             irq_src;
1861         irqreturn_t     status = IRQ_NONE;
1862         unsigned long   flags;
1863
1864         spin_lock_irqsave(&udc->lock, flags);
1865         irq_src = UDC_IRQ_SRC_REG;
1866
1867         /* Device state change (usb ch9 stuff) */
1868         if (irq_src & UDC_DS_CHG) {
1869                 devstate_irq(_udc, irq_src);
1870                 status = IRQ_HANDLED;
1871                 irq_src &= ~UDC_DS_CHG;
1872         }
1873
1874         /* EP0 control transfers */
1875         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1876                 ep0_irq(_udc, irq_src);
1877                 status = IRQ_HANDLED;
1878                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1879         }
1880
1881         /* DMA transfer completion */
1882         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1883                 dma_irq(_udc, irq_src);
1884                 status = IRQ_HANDLED;
1885                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1886         }
1887
1888         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1889         if (irq_src)
1890                 DBG("udc_irq, unhandled %03x\n", irq_src);
1891         spin_unlock_irqrestore(&udc->lock, flags);
1892
1893         return status;
1894 }
1895
1896 /* workaround for seemingly-lost IRQs for RX ACKs... */
1897 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1898 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1899
1900 static void pio_out_timer(unsigned long _ep)
1901 {
1902         struct omap_ep  *ep = (void *) _ep;
1903         unsigned long   flags;
1904         u16             stat_flg;
1905
1906         spin_lock_irqsave(&ep->udc->lock, flags);
1907         if (!list_empty(&ep->queue) && ep->ackwait) {
1908                 use_ep(ep, UDC_EP_SEL);
1909                 stat_flg = UDC_STAT_FLG_REG;
1910
1911                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1912                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1913                         struct omap_req *req;
1914
1915                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1916                         req = container_of(ep->queue.next,
1917                                         struct omap_req, queue);
1918                         (void) read_fifo(ep, req);
1919                         UDC_EP_NUM_REG = ep->bEndpointAddress;
1920                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1921                         ep->ackwait = 1 + ep->double_buf;
1922                 }
1923                 else {
1924                     deselect_ep();
1925                 }
1926         }
1927         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1928         spin_unlock_irqrestore(&ep->udc->lock, flags);
1929 }
1930
1931 static irqreturn_t
1932 omap_udc_pio_irq(int irq, void *_dev, struct pt_regs *r)
1933 {
1934         u16             epn_stat, irq_src;
1935         irqreturn_t     status = IRQ_NONE;
1936         struct omap_ep  *ep;
1937         int             epnum;
1938         struct omap_udc *udc = _dev;
1939         struct omap_req *req;
1940         unsigned long   flags;
1941
1942         spin_lock_irqsave(&udc->lock, flags);
1943         epn_stat = UDC_EPN_STAT_REG;
1944         irq_src = UDC_IRQ_SRC_REG;
1945
1946         /* handle OUT first, to avoid some wasteful NAKs */
1947         if (irq_src & UDC_EPN_RX) {
1948                 epnum = (epn_stat >> 8) & 0x0f;
1949                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1950                 status = IRQ_HANDLED;
1951                 ep = &udc->ep[epnum];
1952                 ep->irqs++;
1953
1954                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1955                 ep->fnf = 0;
1956                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1957                         ep->ackwait--;
1958                         if (!list_empty(&ep->queue)) {
1959                                 int stat;
1960                                 req = container_of(ep->queue.next,
1961                                                 struct omap_req, queue);
1962                                 stat = read_fifo(ep, req);
1963                                 if (!ep->double_buf)
1964                                         ep->fnf = 1;
1965                         }
1966                 }
1967                 /* min 6 clock delay before clearing EP_SEL ... */
1968                 epn_stat = UDC_EPN_STAT_REG;
1969                 epn_stat = UDC_EPN_STAT_REG;
1970                 UDC_EP_NUM_REG = epnum;
1971
1972                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1973                  * reduces lossage; timer still needed though (sigh).
1974                  */
1975                 if (ep->fnf) {
1976                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1977                         ep->ackwait = 1 + ep->double_buf;
1978                 }
1979                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1980         }
1981
1982         /* then IN transfers */
1983         else if (irq_src & UDC_EPN_TX) {
1984                 epnum = epn_stat & 0x0f;
1985                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1986                 status = IRQ_HANDLED;
1987                 ep = &udc->ep[16 + epnum];
1988                 ep->irqs++;
1989
1990                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1991                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1992                         ep->ackwait = 0;
1993                         if (!list_empty(&ep->queue)) {
1994                                 req = container_of(ep->queue.next,
1995                                                 struct omap_req, queue);
1996                                 (void) write_fifo(ep, req);
1997                         }
1998                 }
1999                 /* min 6 clock delay before clearing EP_SEL ... */
2000                 epn_stat = UDC_EPN_STAT_REG;
2001                 epn_stat = UDC_EPN_STAT_REG;
2002                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
2003                 /* then 6 clocks before it'd tx */
2004         }
2005
2006         spin_unlock_irqrestore(&udc->lock, flags);
2007         return status;
2008 }
2009
2010 #ifdef  USE_ISO
2011 static irqreturn_t
2012 omap_udc_iso_irq(int irq, void *_dev, struct pt_regs *r)
2013 {
2014         struct omap_udc *udc = _dev;
2015         struct omap_ep  *ep;
2016         int             pending = 0;
2017         unsigned long   flags;
2018
2019         spin_lock_irqsave(&udc->lock, flags);
2020
2021         /* handle all non-DMA ISO transfers */
2022         list_for_each_entry (ep, &udc->iso, iso) {
2023                 u16             stat;
2024                 struct omap_req *req;
2025
2026                 if (ep->has_dma || list_empty(&ep->queue))
2027                         continue;
2028                 req = list_entry(ep->queue.next, struct omap_req, queue);
2029
2030                 use_ep(ep, UDC_EP_SEL);
2031                 stat = UDC_STAT_FLG_REG;
2032
2033                 /* NOTE: like the other controller drivers, this isn't
2034                  * currently reporting lost or damaged frames.
2035                  */
2036                 if (ep->bEndpointAddress & USB_DIR_IN) {
2037                         if (stat & UDC_MISS_IN)
2038                                 /* done(ep, req, -EPROTO) */;
2039                         else
2040                                 write_fifo(ep, req);
2041                 } else {
2042                         int     status = 0;
2043
2044                         if (stat & UDC_NO_RXPACKET)
2045                                 status = -EREMOTEIO;
2046                         else if (stat & UDC_ISO_ERR)
2047                                 status = -EILSEQ;
2048                         else if (stat & UDC_DATA_FLUSH)
2049                                 status = -ENOSR;
2050
2051                         if (status)
2052                                 /* done(ep, req, status) */;
2053                         else
2054                                 read_fifo(ep, req);
2055                 }
2056                 deselect_ep();
2057                 /* 6 wait states before next EP */
2058
2059                 ep->irqs++;
2060                 if (!list_empty(&ep->queue))
2061                         pending = 1;
2062         }
2063         if (!pending)
2064                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2065         UDC_IRQ_SRC_REG = UDC_SOF;
2066
2067         spin_unlock_irqrestore(&udc->lock, flags);
2068         return IRQ_HANDLED;
2069 }
2070 #endif
2071
2072 /*-------------------------------------------------------------------------*/
2073
2074
2075 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2076 {
2077         int             status = -ENODEV;
2078         struct omap_ep  *ep;
2079         unsigned long   flags;
2080
2081         /* basic sanity tests */
2082         if (!udc)
2083                 return -ENODEV;
2084         if (!driver
2085                         // FIXME if otg, check:  driver->is_otg
2086                         || driver->speed < USB_SPEED_FULL
2087                         || !driver->bind
2088                         || !driver->unbind
2089                         || !driver->setup)
2090                 return -EINVAL;
2091
2092         spin_lock_irqsave(&udc->lock, flags);
2093         if (udc->driver) {
2094                 spin_unlock_irqrestore(&udc->lock, flags);
2095                 return -EBUSY;
2096         }
2097
2098         /* reset state */
2099         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2100                 ep->irqs = 0;
2101                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2102                         continue;
2103                 use_ep(ep, 0);
2104                 UDC_CTRL_REG = UDC_SET_HALT;
2105         }
2106         udc->ep0_pending = 0;
2107         udc->ep[0].irqs = 0;
2108         udc->softconnect = 1;
2109
2110         /* hook up the driver */
2111         driver->driver.bus = NULL;
2112         udc->driver = driver;
2113         udc->gadget.dev.driver = &driver->driver;
2114         spin_unlock_irqrestore(&udc->lock, flags);
2115
2116         if (udc->dc_clk != NULL)
2117                 omap_udc_enable_clock(1);
2118
2119         status = driver->bind (&udc->gadget);
2120         if (status) {
2121                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2122                 udc->gadget.dev.driver = NULL;
2123                 udc->driver = NULL;
2124                 goto done;
2125         }
2126         DBG("bound to driver %s\n", driver->driver.name);
2127
2128         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2129
2130         /* connect to bus through transceiver */
2131         if (udc->transceiver) {
2132                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2133                 if (status < 0) {
2134                         ERR("can't bind to transceiver\n");
2135                         driver->unbind (&udc->gadget);
2136                         udc->gadget.dev.driver = NULL;
2137                         udc->driver = NULL;
2138                         goto done;
2139                 }
2140         } else {
2141                 if (can_pullup(udc))
2142                         pullup_enable (udc);
2143                 else
2144                         pullup_disable (udc);
2145         }
2146
2147         /* boards that don't have VBUS sensing can't autogate 48MHz;
2148          * can't enter deep sleep while a gadget driver is active.
2149          */
2150         if (machine_is_omap_innovator() || machine_is_omap_osk())
2151                 omap_vbus_session(&udc->gadget, 1);
2152
2153 done:
2154         if (udc->dc_clk != NULL)
2155                 omap_udc_enable_clock(0);
2156         return status;
2157 }
2158 EXPORT_SYMBOL(usb_gadget_register_driver);
2159
2160 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2161 {
2162         unsigned long   flags;
2163         int             status = -ENODEV;
2164
2165         if (!udc)
2166                 return -ENODEV;
2167         if (!driver || driver != udc->driver)
2168                 return -EINVAL;
2169
2170         if (udc->dc_clk != NULL)
2171                 omap_udc_enable_clock(1);
2172
2173         if (machine_is_omap_innovator() || machine_is_omap_osk())
2174                 omap_vbus_session(&udc->gadget, 0);
2175
2176         if (udc->transceiver)
2177                 (void) otg_set_peripheral(udc->transceiver, NULL);
2178         else
2179                 pullup_disable(udc);
2180
2181         spin_lock_irqsave(&udc->lock, flags);
2182         udc_quiesce(udc);
2183         spin_unlock_irqrestore(&udc->lock, flags);
2184
2185         driver->unbind(&udc->gadget);
2186         udc->gadget.dev.driver = NULL;
2187         udc->driver = NULL;
2188
2189         if (udc->dc_clk != NULL)
2190                 omap_udc_enable_clock(0);
2191         DBG("unregistered driver '%s'\n", driver->driver.name);
2192         return status;
2193 }
2194 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2195
2196
2197 /*-------------------------------------------------------------------------*/
2198
2199 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2200
2201 #include <linux/seq_file.h>
2202
2203 static const char proc_filename[] = "driver/udc";
2204
2205 #define FOURBITS "%s%s%s%s"
2206 #define EIGHTBITS FOURBITS FOURBITS
2207
2208 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2209 {
2210         u16             stat_flg;
2211         struct omap_req *req;
2212         char            buf[20];
2213
2214         use_ep(ep, 0);
2215
2216         if (use_dma && ep->has_dma)
2217                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2218                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2219                         ep->dma_channel - 1, ep->lch);
2220         else
2221                 buf[0] = 0;
2222
2223         stat_flg = UDC_STAT_FLG_REG;
2224         seq_printf(s,
2225                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2226                 ep->name, buf,
2227                 ep->double_buf ? "dbuf " : "",
2228                 ({char *s; switch(ep->ackwait){
2229                 case 0: s = ""; break;
2230                 case 1: s = "(ackw) "; break;
2231                 case 2: s = "(ackw2) "; break;
2232                 default: s = "(?) "; break;
2233                 } s;}),
2234                 ep->irqs, stat_flg,
2235                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2236                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2237                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2238                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2239                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2240                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2241                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2242                 (stat_flg & UDC_STALL) ? "STALL " : "",
2243                 (stat_flg & UDC_NAK) ? "NAK " : "",
2244                 (stat_flg & UDC_ACK) ? "ACK " : "",
2245                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2246                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2247                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2248
2249         if (list_empty (&ep->queue))
2250                 seq_printf(s, "\t(queue empty)\n");
2251         else
2252                 list_for_each_entry (req, &ep->queue, queue) {
2253                         unsigned        length = req->req.actual;
2254
2255                         if (use_dma && buf[0]) {
2256                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2257                                                 ? dma_src_len : dma_dest_len)
2258                                         (ep, req->req.dma + length);
2259                                 buf[0] = 0;
2260                         }
2261                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2262                                         &req->req, length,
2263                                         req->req.length, req->req.buf);
2264                 }
2265 }
2266
2267 static char *trx_mode(unsigned m, int enabled)
2268 {
2269         switch (m) {
2270         case 0:         return enabled ? "*6wire" : "unused";
2271         case 1:         return "4wire";
2272         case 2:         return "3wire";
2273         case 3:         return "6wire";
2274         default:        return "unknown";
2275         }
2276 }
2277
2278 static int proc_otg_show(struct seq_file *s)
2279 {
2280         u32             tmp;
2281         u32             trans;
2282
2283         tmp = OTG_REV_REG;
2284         trans = USB_TRANSCEIVER_CTRL_REG;
2285         seq_printf(s, "\nOTG rev %d.%d, transceiver_ctrl %05x\n",
2286                 tmp >> 4, tmp & 0xf, trans);
2287         tmp = OTG_SYSCON_1_REG;
2288         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2289                         FOURBITS "\n", tmp,
2290                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2291                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2292                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2293                         ? "internal"
2294                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2295                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2296                 (tmp & HST_IDLE_EN) ? " !host" : "",
2297                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2298                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2299         tmp = OTG_SYSCON_2_REG;
2300         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2301                         " b_ase_brst=%d hmc=%d\n", tmp,
2302                 (tmp & OTG_EN) ? " otg_en" : "",
2303                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2304                 // much more SRP stuff
2305                 (tmp & SRP_DATA) ? " srp_data" : "",
2306                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2307                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2308                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2309                 (tmp & UHOST_EN) ? " uhost_en" : "",
2310                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2311                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2312                 B_ASE_BRST(tmp),
2313                 OTG_HMC(tmp));
2314         tmp = OTG_CTRL_REG;
2315         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2316                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2317                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2318                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2319                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2320                 (tmp & OTG_ID) ? " id" : "",
2321                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2322                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2323                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2324                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2325                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2326                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2327                 (tmp & OTG_PULLDOWN) ? " down" : "",
2328                 (tmp & OTG_PULLUP) ? " up" : "",
2329                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2330                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2331                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2332                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2333                 );
2334         tmp = OTG_IRQ_EN_REG;
2335         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2336         tmp = OTG_IRQ_SRC_REG;
2337         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2338         tmp = OTG_OUTCTRL_REG;
2339         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2340         tmp = OTG_TEST_REG;
2341         seq_printf(s, "otg_test    %04x" "\n", tmp);
2342         return 0;
2343 }
2344
2345 static int proc_udc_show(struct seq_file *s, void *_)
2346 {
2347         u32             tmp;
2348         struct omap_ep  *ep;
2349         unsigned long   flags;
2350
2351         spin_lock_irqsave(&udc->lock, flags);
2352
2353         seq_printf(s, "%s, version: " DRIVER_VERSION
2354 #ifdef  USE_ISO
2355                 " (iso)"
2356 #endif
2357                 "%s\n",
2358                 driver_desc,
2359                 use_dma ?  " (dma)" : "");
2360
2361         tmp = UDC_REV_REG & 0xff;
2362         seq_printf(s,
2363                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2364                 "hmc %d, transceiver %s\n",
2365                 tmp >> 4, tmp & 0xf,
2366                 fifo_mode,
2367                 udc->driver ? udc->driver->driver.name : "(none)",
2368                 HMC,
2369                 udc->transceiver ? udc->transceiver->label : "(none)");
2370         seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2371                 __REG16(ULPD_CLOCK_CTRL),
2372                 __REG16(ULPD_SOFT_REQ),
2373                 __REG16(ULPD_STATUS_REQ));
2374
2375         /* OTG controller registers */
2376         if (!cpu_is_omap15xx())
2377                 proc_otg_show(s);
2378
2379         tmp = UDC_SYSCON1_REG;
2380         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2381                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2382                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2383                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2384                 (tmp & UDC_NAK_EN) ? " nak" : "",
2385                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2386                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2387                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2388                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2389         // syscon2 is write-only
2390
2391         /* UDC controller registers */
2392         if (!(tmp & UDC_PULLUP_EN)) {
2393                 seq_printf(s, "(suspended)\n");
2394                 spin_unlock_irqrestore(&udc->lock, flags);
2395                 return 0;
2396         }
2397
2398         tmp = UDC_DEVSTAT_REG;
2399         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2400                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2401                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2402                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2403                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2404                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2405                 (tmp & UDC_SUS) ? " SUS" : "",
2406                 (tmp & UDC_CFG) ? " CFG" : "",
2407                 (tmp & UDC_ADD) ? " ADD" : "",
2408                 (tmp & UDC_DEF) ? " DEF" : "",
2409                 (tmp & UDC_ATT) ? " ATT" : "");
2410         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2411         tmp = UDC_IRQ_EN_REG;
2412         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2413                 (tmp & UDC_SOF_IE) ? " sof" : "",
2414                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2415                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2416                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2417                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2418         tmp = UDC_IRQ_SRC_REG;
2419         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2420                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2421                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2422                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2423                 (tmp & UDC_SOF) ? " sof" : "",
2424                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2425                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2426                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2427                 (tmp & UDC_SETUP) ? " setup" : "",
2428                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2429                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2430         if (use_dma) {
2431                 unsigned i;
2432
2433                 tmp = UDC_DMA_IRQ_EN_REG;
2434                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2435                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2436                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2437                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2438
2439                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2440                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2441                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2442
2443                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2444                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2445                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2446
2447                 tmp = UDC_RXDMA_CFG_REG;
2448                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2449                 if (tmp) {
2450                         for (i = 0; i < 3; i++) {
2451                                 if ((tmp & (0x0f << (i * 4))) == 0)
2452                                         continue;
2453                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2454                                                 UDC_RXDMA_REG(i + 1));
2455                         }
2456                 }
2457                 tmp = UDC_TXDMA_CFG_REG;
2458                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2459                 if (tmp) {
2460                         for (i = 0; i < 3; i++) {
2461                                 if (!(tmp & (0x0f << (i * 4))))
2462                                         continue;
2463                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2464                                                 UDC_TXDMA_REG(i + 1));
2465                         }
2466                 }
2467         }
2468
2469         tmp = UDC_DEVSTAT_REG;
2470         if (tmp & UDC_ATT) {
2471                 proc_ep_show(s, &udc->ep[0]);
2472                 if (tmp & UDC_ADD) {
2473                         list_for_each_entry (ep, &udc->gadget.ep_list,
2474                                         ep.ep_list) {
2475                                 if (ep->desc)
2476                                         proc_ep_show(s, ep);
2477                         }
2478                 }
2479         }
2480         spin_unlock_irqrestore(&udc->lock, flags);
2481         return 0;
2482 }
2483
2484 static int proc_udc_open(struct inode *inode, struct file *file)
2485 {
2486         return single_open(file, proc_udc_show, NULL);
2487 }
2488
2489 static struct file_operations proc_ops = {
2490         .open           = proc_udc_open,
2491         .read           = seq_read,
2492         .llseek         = seq_lseek,
2493         .release        = single_release,
2494 };
2495
2496 static void create_proc_file(void)
2497 {
2498         struct proc_dir_entry *pde;
2499
2500         pde = create_proc_entry (proc_filename, 0, NULL);
2501         if (pde)
2502                 pde->proc_fops = &proc_ops;
2503 }
2504
2505 static void remove_proc_file(void)
2506 {
2507         remove_proc_entry(proc_filename, NULL);
2508 }
2509
2510 #else
2511
2512 static inline void create_proc_file(void) {}
2513 static inline void remove_proc_file(void) {}
2514
2515 #endif
2516
2517 /*-------------------------------------------------------------------------*/
2518
2519 /* Before this controller can enumerate, we need to pick an endpoint
2520  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2521  * buffer space among the endpoints we'll be operating.
2522  *
2523  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2524  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2525  * capability yet though.
2526  */
2527 static unsigned __init
2528 omap_ep_setup(char *name, u8 addr, u8 type,
2529                 unsigned buf, unsigned maxp, int dbuf)
2530 {
2531         struct omap_ep  *ep;
2532         u16             epn_rxtx = 0;
2533
2534         /* OUT endpoints first, then IN */
2535         ep = &udc->ep[addr & 0xf];
2536         if (addr & USB_DIR_IN)
2537                 ep += 16;
2538
2539         /* in case of ep init table bugs */
2540         BUG_ON(ep->name[0]);
2541
2542         /* chip setup ... bit values are same for IN, OUT */
2543         if (type == USB_ENDPOINT_XFER_ISOC) {
2544                 switch (maxp) {
2545                 case 8:         epn_rxtx = 0 << 12; break;
2546                 case 16:        epn_rxtx = 1 << 12; break;
2547                 case 32:        epn_rxtx = 2 << 12; break;
2548                 case 64:        epn_rxtx = 3 << 12; break;
2549                 case 128:       epn_rxtx = 4 << 12; break;
2550                 case 256:       epn_rxtx = 5 << 12; break;
2551                 case 512:       epn_rxtx = 6 << 12; break;
2552                 default:        BUG();
2553                 }
2554                 epn_rxtx |= UDC_EPN_RX_ISO;
2555                 dbuf = 1;
2556         } else {
2557                 /* double-buffering "not supported" on 15xx,
2558                  * and ignored for PIO-IN on 16xx
2559                  */
2560                 if (!use_dma || cpu_is_omap15xx())
2561                         dbuf = 0;
2562
2563                 switch (maxp) {
2564                 case 8:         epn_rxtx = 0 << 12; break;
2565                 case 16:        epn_rxtx = 1 << 12; break;
2566                 case 32:        epn_rxtx = 2 << 12; break;
2567                 case 64:        epn_rxtx = 3 << 12; break;
2568                 default:        BUG();
2569                 }
2570                 if (dbuf && addr)
2571                         epn_rxtx |= UDC_EPN_RX_DB;
2572                 init_timer(&ep->timer);
2573                 ep->timer.function = pio_out_timer;
2574                 ep->timer.data = (unsigned long) ep;
2575         }
2576         if (addr)
2577                 epn_rxtx |= UDC_EPN_RX_VALID;
2578         BUG_ON(buf & 0x07);
2579         epn_rxtx |= buf >> 3;
2580
2581         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2582                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2583
2584         if (addr & USB_DIR_IN)
2585                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2586         else
2587                 UDC_EP_RX_REG(addr) = epn_rxtx;
2588
2589         /* next endpoint's buffer starts after this one's */
2590         buf += maxp;
2591         if (dbuf)
2592                 buf += maxp;
2593         BUG_ON(buf > 2048);
2594
2595         /* set up driver data structures */
2596         BUG_ON(strlen(name) >= sizeof ep->name);
2597         strlcpy(ep->name, name, sizeof ep->name);
2598         INIT_LIST_HEAD(&ep->queue);
2599         INIT_LIST_HEAD(&ep->iso);
2600         ep->bEndpointAddress = addr;
2601         ep->bmAttributes = type;
2602         ep->double_buf = dbuf;
2603         ep->udc = udc;
2604
2605         ep->ep.name = ep->name;
2606         ep->ep.ops = &omap_ep_ops;
2607         ep->ep.maxpacket = ep->maxpacket = maxp;
2608         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2609
2610         return buf;
2611 }
2612
2613 static void omap_udc_release(struct device *dev)
2614 {
2615         complete(udc->done);
2616         kfree (udc);
2617         udc = NULL;
2618 }
2619
2620 static int __init
2621 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2622 {
2623         unsigned        tmp, buf;
2624
2625         /* abolish any previous hardware state */
2626         UDC_SYSCON1_REG = 0;
2627         UDC_IRQ_EN_REG = 0;
2628         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2629         UDC_DMA_IRQ_EN_REG = 0;
2630         UDC_RXDMA_CFG_REG = 0;
2631         UDC_TXDMA_CFG_REG = 0;
2632
2633         /* UDC_PULLUP_EN gates the chip clock */
2634         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2635
2636         udc = kmalloc (sizeof *udc, SLAB_KERNEL);
2637         if (!udc)
2638                 return -ENOMEM;
2639
2640         memset(udc, 0, sizeof *udc);
2641         spin_lock_init (&udc->lock);
2642
2643         udc->gadget.ops = &omap_gadget_ops;
2644         udc->gadget.ep0 = &udc->ep[0].ep;
2645         INIT_LIST_HEAD(&udc->gadget.ep_list);
2646         INIT_LIST_HEAD(&udc->iso);
2647         udc->gadget.speed = USB_SPEED_UNKNOWN;
2648         udc->gadget.name = driver_name;
2649
2650         device_initialize(&udc->gadget.dev);
2651         strcpy (udc->gadget.dev.bus_id, "gadget");
2652         udc->gadget.dev.release = omap_udc_release;
2653         udc->gadget.dev.parent = &odev->dev;
2654         if (use_dma)
2655                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2656
2657         udc->transceiver = xceiv;
2658
2659         /* ep0 is special; put it right after the SETUP buffer */
2660         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2661                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2662         list_del_init(&udc->ep[0].ep.ep_list);
2663
2664         /* initially disable all non-ep0 endpoints */
2665         for (tmp = 1; tmp < 15; tmp++) {
2666                 UDC_EP_RX_REG(tmp) = 0;
2667                 UDC_EP_TX_REG(tmp) = 0;
2668         }
2669
2670 #define OMAP_BULK_EP(name,addr) \
2671         buf = omap_ep_setup(name "-bulk", addr, \
2672                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2673 #define OMAP_INT_EP(name,addr, maxp) \
2674         buf = omap_ep_setup(name "-int", addr, \
2675                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2676 #define OMAP_ISO_EP(name,addr, maxp) \
2677         buf = omap_ep_setup(name "-iso", addr, \
2678                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2679
2680         switch (fifo_mode) {
2681         case 0:
2682                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2683                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2684                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2685                 break;
2686         case 1:
2687                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2688                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2689                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2690
2691                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2692                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2693                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2694
2695                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2696                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2697                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2698
2699                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2700                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2701                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2702
2703                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2704                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2705                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2706                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2707
2708                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2709                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2710                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2711                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2712
2713                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2714                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2715
2716                 break;
2717
2718 #ifdef  USE_ISO
2719         case 2:                 /* mixed iso/bulk */
2720                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2721                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2722                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2723                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2724
2725                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2726
2727                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2728                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2729                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2730                 break;
2731         case 3:                 /* mixed bulk/iso */
2732                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2733                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2734                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2735
2736                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2737                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2738                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2739
2740                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2741                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2742                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2743                 break;
2744 #endif
2745
2746         /* add more modes as needed */
2747
2748         default:
2749                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2750                 return -ENODEV;
2751         }
2752         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2753         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2754         return 0;
2755 }
2756
2757 static int __init omap_udc_probe(struct platform_device *pdev)
2758 {
2759         int                     status = -ENODEV;
2760         int                     hmc;
2761         struct otg_transceiver  *xceiv = NULL;
2762         const char              *type = NULL;
2763         struct omap_usb_config  *config = pdev->dev.platform_data;
2764         struct clk              *dc_clk;
2765         struct clk              *hhc_clk;
2766
2767         /* NOTE:  "knows" the order of the resources! */
2768         if (!request_mem_region(pdev->resource[0].start,
2769                         pdev->resource[0].end - pdev->resource[0].start + 1,
2770                         driver_name)) {
2771                 DBG("request_mem_region failed\n");
2772                 return -EBUSY;
2773         }
2774
2775         if (cpu_is_omap16xx()) {
2776                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2777                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2778                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2779                 /* can't use omap_udc_enable_clock yet */
2780                 clk_enable(dc_clk);
2781                 clk_enable(hhc_clk);
2782                 udelay(100);
2783         }
2784
2785         INFO("OMAP UDC rev %d.%d%s\n",
2786                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2787                 config->otg ? ", Mini-AB" : "");
2788
2789         /* use the mode given to us by board init code */
2790         if (cpu_is_omap15xx()) {
2791                 hmc = HMC_1510;
2792                 type = "(unknown)";
2793
2794                 if (machine_is_omap_innovator()) {
2795                         /* just set up software VBUS detect, and then
2796                          * later rig it so we always report VBUS.
2797                          * FIXME without really sensing VBUS, we can't
2798                          * know when to turn PULLUP_EN on/off; and that
2799                          * means we always "need" the 48MHz clock.
2800                          */
2801                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2802
2803                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2804                         tmp |= VBUS_MODE_1510;
2805                         tmp &= ~VBUS_CTRL_1510;
2806                         FUNC_MUX_CTRL_0_REG = tmp;
2807                 }
2808         } else {
2809                 /* The transceiver may package some GPIO logic or handle
2810                  * loopback and/or transceiverless setup; if we find one,
2811                  * use it.  Except for OTG, we don't _need_ to talk to one;
2812                  * but not having one probably means no VBUS detection.
2813                  */
2814                 xceiv = otg_get_transceiver();
2815                 if (xceiv)
2816                         type = xceiv->label;
2817                 else if (config->otg) {
2818                         DBG("OTG requires external transceiver!\n");
2819                         goto cleanup0;
2820                 }
2821
2822                 hmc = HMC_1610;
2823                 switch (hmc) {
2824                 case 0:                 /* POWERUP DEFAULT == 0 */
2825                 case 4:
2826                 case 12:
2827                 case 20:
2828                         if (!cpu_is_omap1710()) {
2829                                 type = "integrated";
2830                                 break;
2831                         }
2832                         /* FALL THROUGH */
2833                 case 3:
2834                 case 11:
2835                 case 16:
2836                 case 19:
2837                 case 25:
2838                         if (!xceiv) {
2839                                 DBG("external transceiver not registered!\n");
2840                                 type = "unknown";
2841                         }
2842                         break;
2843                 case 21:                        /* internal loopback */
2844                         type = "loopback";
2845                         break;
2846                 case 14:                        /* transceiverless */
2847                         if (cpu_is_omap1710())
2848                                 goto bad_on_1710;
2849                         /* FALL THROUGH */
2850                 case 13:
2851                 case 15:
2852                         type = "no";
2853                         break;
2854
2855                 default:
2856 bad_on_1710:
2857                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2858                         goto cleanup0;
2859                 }
2860         }
2861         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2862
2863         /* a "gadget" abstracts/virtualizes the controller */
2864         status = omap_udc_setup(pdev, xceiv);
2865         if (status) {
2866                 goto cleanup0;
2867         }
2868         xceiv = NULL;
2869         // "udc" is now valid
2870         pullup_disable(udc);
2871 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2872         udc->gadget.is_otg = (config->otg != 0);
2873 #endif
2874
2875         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2876         if (UDC_REV_REG >= 0x61)
2877                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2878         else
2879                 udc->clr_halt = UDC_RESET_EP;
2880
2881         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2882         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2883                         SA_SAMPLE_RANDOM, driver_name, udc);
2884         if (status != 0) {
2885                 ERR( "can't get irq %ld, err %d\n",
2886                         pdev->resource[1].start, status);
2887                 goto cleanup1;
2888         }
2889
2890         /* USB "non-iso" IRQ (PIO for all but ep0) */
2891         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2892                         SA_SAMPLE_RANDOM, "omap_udc pio", udc);
2893         if (status != 0) {
2894                 ERR( "can't get irq %ld, err %d\n",
2895                         pdev->resource[2].start, status);
2896                 goto cleanup2;
2897         }
2898 #ifdef  USE_ISO
2899         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2900                         SA_INTERRUPT, "omap_udc iso", udc);
2901         if (status != 0) {
2902                 ERR("can't get irq %ld, err %d\n",
2903                         pdev->resource[3].start, status);
2904                 goto cleanup3;
2905         }
2906 #endif
2907         if (cpu_is_omap16xx()) {
2908                 udc->dc_clk = dc_clk;
2909                 udc->hhc_clk = hhc_clk;
2910                 clk_disable(hhc_clk);
2911                 clk_disable(dc_clk);
2912         }
2913
2914         create_proc_file();
2915         device_add(&udc->gadget.dev);
2916         return 0;
2917
2918 #ifdef  USE_ISO
2919 cleanup3:
2920         free_irq(pdev->resource[2].start, udc);
2921 #endif
2922
2923 cleanup2:
2924         free_irq(pdev->resource[1].start, udc);
2925
2926 cleanup1:
2927         kfree (udc);
2928         udc = NULL;
2929
2930 cleanup0:
2931         if (xceiv)
2932                 put_device(xceiv->dev);
2933
2934         if (cpu_is_omap16xx()) {
2935                 clk_disable(hhc_clk);
2936                 clk_disable(dc_clk);
2937                 clk_put(hhc_clk);
2938                 clk_put(dc_clk);
2939         }
2940
2941         release_mem_region(pdev->resource[0].start,
2942                         pdev->resource[0].end - pdev->resource[0].start + 1);
2943
2944         return status;
2945 }
2946
2947 static int __exit omap_udc_remove(struct platform_device *pdev)
2948 {
2949         DECLARE_COMPLETION(done);
2950
2951         if (!udc)
2952                 return -ENODEV;
2953
2954         udc->done = &done;
2955
2956         pullup_disable(udc);
2957         if (udc->transceiver) {
2958                 put_device(udc->transceiver->dev);
2959                 udc->transceiver = NULL;
2960         }
2961         UDC_SYSCON1_REG = 0;
2962
2963         remove_proc_file();
2964
2965 #ifdef  USE_ISO
2966         free_irq(pdev->resource[3].start, udc);
2967 #endif
2968         free_irq(pdev->resource[2].start, udc);
2969         free_irq(pdev->resource[1].start, udc);
2970
2971         if (udc->dc_clk) {
2972                 if (udc->clk_requested)
2973                         omap_udc_enable_clock(0);
2974                 clk_put(udc->hhc_clk);
2975                 clk_put(udc->dc_clk);
2976         }
2977
2978         release_mem_region(pdev->resource[0].start,
2979                         pdev->resource[0].end - pdev->resource[0].start + 1);
2980
2981         device_unregister(&udc->gadget.dev);
2982         wait_for_completion(&done);
2983
2984         return 0;
2985 }
2986
2987 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
2988  * system is forced into deep sleep
2989  *
2990  * REVISIT we should probably reject suspend requests when there's a host
2991  * session active, rather than disconnecting, at least on boards that can
2992  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
2993  * make host resumes and VBUS detection trigger OMAP wakeup events; that
2994  * may involve talking to an external transceiver (e.g. isp1301).
2995  */
2996
2997 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
2998 {
2999         u32     devstat;
3000
3001         devstat = UDC_DEVSTAT_REG;
3002
3003         /* we're requesting 48 MHz clock if the pullup is enabled
3004          * (== we're attached to the host) and we're not suspended,
3005          * which would prevent entry to deep sleep...
3006          */
3007         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3008                 WARN("session active; suspend requires disconnect\n");
3009                 omap_pullup(&udc->gadget, 0);
3010         }
3011
3012         udc->gadget.dev.power.power_state = PMSG_SUSPEND;
3013         udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
3014         return 0;
3015 }
3016
3017 static int omap_udc_resume(struct platform_device *dev)
3018 {
3019         DBG("resume + wakeup/SRP\n");
3020         omap_pullup(&udc->gadget, 1);
3021
3022         /* maybe the host would enumerate us if we nudged it */
3023         msleep(100);
3024         return omap_wakeup(&udc->gadget);
3025 }
3026
3027 /*-------------------------------------------------------------------------*/
3028
3029 static struct platform_driver udc_driver = {
3030         .probe          = omap_udc_probe,
3031         .remove         = __exit_p(omap_udc_remove),
3032         .suspend        = omap_udc_suspend,
3033         .resume         = omap_udc_resume,
3034         .driver         = {
3035                 .owner  = THIS_MODULE,
3036                 .name   = (char *) driver_name,
3037         },
3038 };
3039
3040 static int __init udc_init(void)
3041 {
3042         INFO("%s, version: " DRIVER_VERSION
3043 #ifdef  USE_ISO
3044                 " (iso)"
3045 #endif
3046                 "%s\n", driver_desc,
3047                 use_dma ?  " (dma)" : "");
3048         return platform_driver_register(&udc_driver);
3049 }
3050 module_init(udc_init);
3051
3052 static void __exit udc_exit(void)
3053 {
3054         platform_driver_unregister(&udc_driver);
3055 }
3056 module_exit(udc_exit);
3057
3058 MODULE_DESCRIPTION(DRIVER_DESC);
3059 MODULE_LICENSE("GPL");
3060