2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/ioport.h>
30 #include <linux/types.h>
31 #include <linux/errno.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <linux/init.h>
35 #include <linux/timer.h>
36 #include <linux/list.h>
37 #include <linux/interrupt.h>
38 #include <linux/proc_fs.h>
40 #include <linux/moduleparam.h>
41 #include <linux/platform_device.h>
42 #include <linux/usb/ch9.h>
43 #include <linux/usb/gadget.h>
44 #include <linux/usb/otg.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/clk.h>
48 #include <asm/byteorder.h>
51 #include <asm/system.h>
52 #include <asm/unaligned.h>
53 #include <asm/mach-types.h>
57 #include <mach/control.h>
63 /* bulk DMA seems to be behaving for both IN and OUT */
64 #ifdef CONFIG_MACH_OMAP_H6300
74 #define DRIVER_DESC "OMAP UDC driver"
75 #define DRIVER_VERSION "4 October 2004"
77 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
79 #define OMAP2_DMA_CH(ch) (((ch) - 1) << 1)
80 #define OMAP24XX_DMA(name, ch) (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
83 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
84 * D+ pullup to allow enumeration. That's too early for the gadget
85 * framework to use from usb_endpoint_enable(), which happens after
86 * enumeration as part of activating an interface. (But if we add an
87 * optional new "UDC not yet running" state to the gadget driver model,
88 * even just during driver binding, the endpoint autoconfig logic is the
89 * natural spot to manufacture new endpoints.)
91 * So instead of using endpoint enable calls to control the hardware setup,
92 * this driver defines a "fifo mode" parameter. It's used during driver
93 * initialization to choose among a set of pre-defined endpoint configs.
94 * See omap_udc_setup() for available modes, or to add others. That code
95 * lives in an init section, so use this driver as a module if you need
96 * to change the fifo mode after the kernel boots.
98 * Gadget drivers normally ignore endpoints they don't care about, and
99 * won't include them in configuration descriptors. That means only
100 * misbehaving hosts would even notice they exist.
103 static unsigned fifo_mode = 3;
105 static unsigned fifo_mode = 0;
108 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
109 * boot parameter "omap_udc:fifo_mode=42"
111 module_param (fifo_mode, uint, 0);
112 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
115 static unsigned use_dma = 1;
117 /* "modprobe omap_udc use_dma=y", or else as a kernel
118 * boot parameter "omap_udc:use_dma=y"
120 module_param (use_dma, bool, 0);
121 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
124 /* save a bit of code */
126 #endif /* !USE_DMA */
129 static const char driver_name [] = "omap_udc";
130 static const char driver_desc [] = DRIVER_DESC;
132 /*-------------------------------------------------------------------------*/
134 /* there's a notion of "current endpoint" for modifying endpoint
135 * state, and PIO access to its FIFO.
138 static void use_ep(struct omap_ep *ep, u16 select)
140 u16 num = ep->bEndpointAddress & 0x0f;
142 if (ep->bEndpointAddress & USB_DIR_IN)
144 omap_writew(num | select, UDC_EP_NUM);
145 /* when select, MUST deselect later !! */
148 static inline void deselect_ep(void)
152 w = omap_readw(UDC_EP_NUM);
154 omap_writew(w, UDC_EP_NUM);
155 /* 6 wait states before TX will happen */
158 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
160 /*-------------------------------------------------------------------------*/
162 static int omap_ep_enable(struct usb_ep *_ep,
163 const struct usb_endpoint_descriptor *desc)
165 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
166 struct omap_udc *udc;
170 /* catch various bogus parameters */
171 if (!_ep || !desc || ep->desc
172 || desc->bDescriptorType != USB_DT_ENDPOINT
173 || ep->bEndpointAddress != desc->bEndpointAddress
174 || ep->maxpacket < le16_to_cpu
175 (desc->wMaxPacketSize)) {
176 DBG("%s, bad ep or descriptor\n", __func__);
179 maxp = le16_to_cpu (desc->wMaxPacketSize);
180 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
181 && maxp != ep->maxpacket)
182 || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
183 || !desc->wMaxPacketSize) {
184 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
189 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
190 && desc->bInterval != 1)) {
191 /* hardware wants period = 1; USB allows 2^(Interval-1) */
192 DBG("%s, unsupported ISO period %dms\n", _ep->name,
193 1 << (desc->bInterval - 1));
197 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
198 DBG("%s, ISO nyet\n", _ep->name);
203 /* xfer types must match, except that interrupt ~= bulk */
204 if (ep->bmAttributes != desc->bmAttributes
205 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
206 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
207 DBG("%s, %s type mismatch\n", __func__, _ep->name);
212 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
213 DBG("%s, bogus device state\n", __func__);
217 spin_lock_irqsave(&udc->lock, flags);
222 ep->ep.maxpacket = maxp;
224 /* set endpoint to initial state */
228 use_ep(ep, UDC_EP_SEL);
229 omap_writew(udc->clr_halt, UDC_CTRL);
233 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
234 list_add(&ep->iso, &udc->iso);
236 /* maybe assign a DMA channel to this endpoint */
237 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
238 /* FIXME ISO can dma, but prefers first channel */
239 dma_channel_claim(ep, 0);
241 /* PIO OUT may RX packets */
242 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
244 && !(ep->bEndpointAddress & USB_DIR_IN)) {
245 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
246 ep->ackwait = 1 + ep->double_buf;
249 spin_unlock_irqrestore(&udc->lock, flags);
250 VDBG("%s enabled\n", _ep->name);
254 static void nuke(struct omap_ep *, int status);
256 static int omap_ep_disable(struct usb_ep *_ep)
258 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
261 if (!_ep || !ep->desc) {
262 DBG("%s, %s not enabled\n", __func__,
263 _ep ? ep->ep.name : NULL);
267 spin_lock_irqsave(&ep->udc->lock, flags);
269 nuke (ep, -ESHUTDOWN);
270 ep->ep.maxpacket = ep->maxpacket;
272 omap_writew(UDC_SET_HALT, UDC_CTRL);
273 list_del_init(&ep->iso);
274 del_timer(&ep->timer);
276 spin_unlock_irqrestore(&ep->udc->lock, flags);
278 VDBG("%s disabled\n", _ep->name);
282 /*-------------------------------------------------------------------------*/
284 static struct usb_request *
285 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
287 struct omap_req *req;
289 req = kzalloc(sizeof(*req), gfp_flags);
291 req->req.dma = DMA_ADDR_INVALID;
292 INIT_LIST_HEAD (&req->queue);
298 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
300 struct omap_req *req = container_of(_req, struct omap_req, req);
306 /*-------------------------------------------------------------------------*/
309 done(struct omap_ep *ep, struct omap_req *req, int status)
311 unsigned stopped = ep->stopped;
313 list_del_init(&req->queue);
315 if (req->req.status == -EINPROGRESS)
316 req->req.status = status;
318 status = req->req.status;
320 if (use_dma && ep->has_dma) {
322 dma_unmap_single(ep->udc->gadget.dev.parent,
323 req->req.dma, req->req.length,
324 (ep->bEndpointAddress & USB_DIR_IN)
327 req->req.dma = DMA_ADDR_INVALID;
330 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
331 req->req.dma, req->req.length,
332 (ep->bEndpointAddress & USB_DIR_IN)
338 if (status && status != -ESHUTDOWN)
340 VDBG("complete %s req %p stat %d len %u/%u\n",
341 ep->ep.name, &req->req, status,
342 req->req.actual, req->req.length);
344 /* don't modify queue heads during completion callback */
346 spin_unlock(&ep->udc->lock);
347 req->req.complete(&ep->ep, &req->req);
348 spin_lock(&ep->udc->lock);
349 ep->stopped = stopped;
352 /*-------------------------------------------------------------------------*/
354 #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
355 #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
357 #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
358 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
361 write_packet(u8 *buf, struct omap_req *req, unsigned max)
366 len = min(req->req.length - req->req.actual, max);
367 req->req.actual += len;
370 if (likely((((int)buf) & 1) == 0)) {
373 omap_writew(*wp++, UDC_DATA);
379 omap_writeb(*buf++, UDC_DATA);
383 // FIXME change r/w fifo calling convention
386 // return: 0 = still running, 1 = completed, negative = errno
387 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
394 buf = req->req.buf + req->req.actual;
397 /* PIO-IN isn't double buffered except for iso */
398 ep_stat = omap_readw(UDC_STAT_FLG);
399 if (ep_stat & UDC_FIFO_UNWRITABLE)
402 count = ep->ep.maxpacket;
403 count = write_packet(buf, req, count);
404 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
407 /* last packet is often short (sometimes a zlp) */
408 if (count != ep->ep.maxpacket)
410 else if (req->req.length == req->req.actual
416 /* NOTE: requests complete when all IN data is in a
417 * FIFO (or sometimes later, if a zlp was needed).
418 * Use usb_ep_fifo_status() where needed.
426 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
431 len = min(req->req.length - req->req.actual, avail);
432 req->req.actual += len;
435 if (likely((((int)buf) & 1) == 0)) {
438 *wp++ = omap_readw(UDC_DATA);
444 *buf++ = omap_readb(UDC_DATA);
448 // return: 0 = still running, 1 = queue empty, negative = errno
449 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
452 unsigned count, avail;
455 buf = req->req.buf + req->req.actual;
459 u16 ep_stat = omap_readw(UDC_STAT_FLG);
462 if (ep_stat & FIFO_EMPTY) {
467 if (ep_stat & UDC_EP_HALTED)
470 if (ep_stat & UDC_FIFO_FULL)
471 avail = ep->ep.maxpacket;
473 avail = omap_readw(UDC_RXFSTAT);
474 ep->fnf = ep->double_buf;
476 count = read_packet(buf, req, avail);
478 /* partial packet reads may not be errors */
479 if (count < ep->ep.maxpacket) {
481 /* overflowed this request? flush extra data */
482 if (count != avail) {
483 req->req.status = -EOVERFLOW;
486 omap_readw(UDC_DATA);
488 } else if (req->req.length == req->req.actual)
493 if (!ep->bEndpointAddress)
502 /*-------------------------------------------------------------------------*/
504 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
508 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
509 * the last transfer's bytecount by more than a FIFO's worth.
511 if (cpu_is_omap15xx())
514 end = omap_get_dma_src_pos(ep->lch);
515 if (end == ep->dma_counter)
518 end |= start & (0xffff << 16);
524 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
528 end = omap_get_dma_dst_pos(ep->lch);
529 if (end == ep->dma_counter)
532 end |= start & (0xffff << 16);
533 if (cpu_is_omap15xx())
541 /* Each USB transfer request using DMA maps to one or more DMA transfers.
542 * When DMA completion isn't request completion, the UDC continues with
543 * the next DMA transfer for that USB transfer.
546 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
549 unsigned length = req->req.length - req->req.actual;
550 const int sync_mode = cpu_is_omap15xx()
551 ? OMAP_DMA_SYNC_FRAME
552 : OMAP_DMA_SYNC_ELEMENT;
555 if (cpu_is_omap24xx())
556 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
558 /* measure length in either bytes or packets */
559 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
560 || (cpu_is_omap24xx() && length < ep->maxpacket)
561 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
562 txdma_ctrl = UDC_TXN_EOT | length;
563 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
564 length, 1, sync_mode, dma_trigger, 0);
566 length = min(length / ep->maxpacket,
567 (unsigned) UDC_TXN_TSC + 1);
569 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
570 ep->ep.maxpacket >> 1, length, sync_mode,
572 length *= ep->maxpacket;
574 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
575 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
578 omap_start_dma(ep->lch);
579 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
580 w = omap_readw(UDC_DMA_IRQ_EN);
581 w |= UDC_TX_DONE_IE(ep->dma_channel);
582 omap_writew(w, UDC_DMA_IRQ_EN);
583 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
584 req->dma_bytes = length;
587 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
592 req->req.actual += req->dma_bytes;
594 /* return if this request needs to send data or zlp */
595 if (req->req.actual < req->req.length)
598 && req->dma_bytes != 0
599 && (req->req.actual % ep->maxpacket) == 0)
602 req->req.actual += dma_src_len(ep, req->req.dma
606 omap_stop_dma(ep->lch);
607 w = omap_readw(UDC_DMA_IRQ_EN);
608 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
609 omap_writew(w, UDC_DMA_IRQ_EN);
610 done(ep, req, status);
613 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
615 unsigned packets = req->req.length - req->req.actual;
619 if (cpu_is_omap24xx())
620 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
622 /* NOTE: we filtered out "short reads" before, so we know
623 * the buffer has only whole numbers of packets.
624 * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
626 if (cpu_is_omap24xx() && packets < ep->maxpacket) {
627 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
628 packets, 1, OMAP_DMA_SYNC_ELEMENT,
630 req->dma_bytes = packets;
632 /* set up this DMA transfer, enable the fifo, start */
633 packets /= ep->ep.maxpacket;
634 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
635 req->dma_bytes = packets * ep->ep.maxpacket;
636 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
637 ep->ep.maxpacket >> 1, packets,
638 OMAP_DMA_SYNC_ELEMENT,
641 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
642 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
644 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
646 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
647 w = omap_readw(UDC_DMA_IRQ_EN);
648 w |= UDC_RX_EOT_IE(ep->dma_channel);
649 omap_writew(w, UDC_DMA_IRQ_EN);
650 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
651 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
653 omap_start_dma(ep->lch);
657 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
662 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
663 count = dma_dest_len(ep, req->req.dma + req->req.actual);
664 count += req->req.actual;
667 if (count <= req->req.length)
668 req->req.actual = count;
670 if (count != req->dma_bytes || status)
671 omap_stop_dma(ep->lch);
673 /* if this wasn't short, request may need another transfer */
674 else if (req->req.actual < req->req.length)
678 w = omap_readw(UDC_DMA_IRQ_EN);
679 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
680 omap_writew(w, UDC_DMA_IRQ_EN);
681 done(ep, req, status);
684 static void dma_irq(struct omap_udc *udc, u16 irq_src)
686 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
688 struct omap_req *req;
690 /* IN dma: tx to host */
691 if (irq_src & UDC_TXN_DONE) {
692 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
694 /* can see TXN_DONE after dma abort */
695 if (!list_empty(&ep->queue)) {
696 req = container_of(ep->queue.next,
697 struct omap_req, queue);
698 finish_in_dma(ep, req, 0);
700 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
702 if (!list_empty (&ep->queue)) {
703 req = container_of(ep->queue.next,
704 struct omap_req, queue);
705 next_in_dma(ep, req);
709 /* OUT dma: rx from host */
710 if (irq_src & UDC_RXN_EOT) {
711 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
713 /* can see RXN_EOT after dma abort */
714 if (!list_empty(&ep->queue)) {
715 req = container_of(ep->queue.next,
716 struct omap_req, queue);
717 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
719 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
721 if (!list_empty (&ep->queue)) {
722 req = container_of(ep->queue.next,
723 struct omap_req, queue);
724 next_out_dma(ep, req);
728 if (irq_src & UDC_RXN_CNT) {
729 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
731 /* omap15xx does this unasked... */
732 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
733 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
737 static void dma_error(int lch, u16 ch_status, void *data)
739 struct omap_ep *ep = data;
741 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
742 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
743 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
745 /* complete current transfer ... */
748 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
751 int status, restart, is_in;
754 is_in = ep->bEndpointAddress & USB_DIR_IN;
756 reg = omap_readw(UDC_TXDMA_CFG);
758 reg = omap_readw(UDC_RXDMA_CFG);
759 reg |= UDC_DMA_REQ; /* "pulse" activated */
763 if (channel == 0 || channel > 3) {
764 if ((reg & 0x0f00) == 0)
766 else if ((reg & 0x00f0) == 0)
768 else if ((reg & 0x000f) == 0) /* preferred for ISO */
775 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
776 ep->dma_channel = channel;
779 if (cpu_is_omap24xx())
780 dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
782 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
783 status = omap_request_dma(dma_channel,
784 ep->ep.name, dma_error, ep, &ep->lch);
786 omap_writew(reg, UDC_TXDMA_CFG);
788 omap_set_dma_src_burst_mode(ep->lch,
789 OMAP_DMA_DATA_BURST_4);
790 omap_set_dma_src_data_pack(ep->lch, 1);
792 omap_set_dma_dest_params(ep->lch,
794 OMAP_DMA_AMODE_CONSTANT,
799 if (cpu_is_omap24xx())
800 dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
802 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
804 status = omap_request_dma(dma_channel,
805 ep->ep.name, dma_error, ep, &ep->lch);
807 omap_writew(reg, UDC_RXDMA_CFG);
809 omap_set_dma_src_params(ep->lch,
811 OMAP_DMA_AMODE_CONSTANT,
815 omap_set_dma_dest_burst_mode(ep->lch,
816 OMAP_DMA_DATA_BURST_4);
817 omap_set_dma_dest_data_pack(ep->lch, 1);
824 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
826 /* channel type P: hw synch (fifo) */
827 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
828 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
832 /* restart any queue, even if the claim failed */
833 restart = !ep->stopped && !list_empty(&ep->queue);
836 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
837 restart ? " (restart)" : "");
839 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
841 ep->dma_channel - 1, ep->lch,
842 restart ? " (restart)" : "");
845 struct omap_req *req;
846 req = container_of(ep->queue.next, struct omap_req, queue);
848 (is_in ? next_in_dma : next_out_dma)(ep, req);
850 use_ep(ep, UDC_EP_SEL);
851 (is_in ? write_fifo : read_fifo)(ep, req);
854 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
855 ep->ackwait = 1 + ep->double_buf;
857 /* IN: 6 wait states before it'll tx */
862 static void dma_channel_release(struct omap_ep *ep)
864 int shift = 4 * (ep->dma_channel - 1);
865 u16 mask = 0x0f << shift;
866 struct omap_req *req;
869 /* abort any active usb transfer request */
870 if (!list_empty(&ep->queue))
871 req = container_of(ep->queue.next, struct omap_req, queue);
875 active = omap_get_dma_active_status(ep->lch);
877 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
878 active ? "active" : "idle",
879 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
880 ep->dma_channel - 1, req);
882 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
883 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
886 /* wait till current packet DMA finishes, and fifo empties */
887 if (ep->bEndpointAddress & USB_DIR_IN) {
888 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
892 finish_in_dma(ep, req, -ECONNRESET);
894 /* clear FIFO; hosts probably won't empty it */
895 use_ep(ep, UDC_EP_SEL);
896 omap_writew(UDC_CLR_EP, UDC_CTRL);
899 while (omap_readw(UDC_TXDMA_CFG) & mask)
902 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
905 /* dma empties the fifo */
906 while (omap_readw(UDC_RXDMA_CFG) & mask)
909 finish_out_dma(ep, req, -ECONNRESET, 0);
911 omap_free_dma(ep->lch);
914 /* has_dma still set, till endpoint is fully quiesced */
918 /*-------------------------------------------------------------------------*/
921 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
923 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
924 struct omap_req *req = container_of(_req, struct omap_req, req);
925 struct omap_udc *udc;
929 /* catch various bogus parameters */
930 if (!_req || !req->req.complete || !req->req.buf
931 || !list_empty(&req->queue)) {
932 DBG("%s, bad params\n", __func__);
935 if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
936 DBG("%s, bad ep\n", __func__);
939 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
940 if (req->req.length > ep->ep.maxpacket)
945 /* this isn't bogus, but OMAP DMA isn't the only hardware to
946 * have a hard time with partial packet reads... reject it.
947 * Except OMAP2 can handle the small packets.
951 && ep->bEndpointAddress != 0
952 && (ep->bEndpointAddress & USB_DIR_IN) == 0
953 && !cpu_class_is_omap2()
954 && (req->req.length % ep->ep.maxpacket) != 0) {
955 DBG("%s, no partial packet OUT reads\n", __func__);
960 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
963 if (use_dma && ep->has_dma) {
964 if (req->req.dma == DMA_ADDR_INVALID) {
965 req->req.dma = dma_map_single(
966 ep->udc->gadget.dev.parent,
969 (ep->bEndpointAddress & USB_DIR_IN)
974 dma_sync_single_for_device(
975 ep->udc->gadget.dev.parent,
976 req->req.dma, req->req.length,
977 (ep->bEndpointAddress & USB_DIR_IN)
984 VDBG("%s queue req %p, len %d buf %p\n",
985 ep->ep.name, _req, _req->length, _req->buf);
987 spin_lock_irqsave(&udc->lock, flags);
989 req->req.status = -EINPROGRESS;
992 /* maybe kickstart non-iso i/o queues */
996 w = omap_readw(UDC_IRQ_EN);
998 omap_writew(w, UDC_IRQ_EN);
999 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1002 if (ep->bEndpointAddress == 0) {
1003 if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1004 spin_unlock_irqrestore(&udc->lock, flags);
1008 /* empty DATA stage? */
1009 is_in = udc->ep0_in;
1010 if (!req->req.length) {
1012 /* chip became CONFIGURED or ADDRESSED
1013 * earlier; drivers may already have queued
1014 * requests to non-control endpoints
1016 if (udc->ep0_set_config) {
1017 u16 irq_en = omap_readw(UDC_IRQ_EN);
1019 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1020 if (!udc->ep0_reset_config)
1021 irq_en |= UDC_EPN_RX_IE
1023 omap_writew(irq_en, UDC_IRQ_EN);
1026 /* STATUS for zero length DATA stages is
1027 * always an IN ... even for IN transfers,
1028 * a weird case which seem to stall OMAP.
1030 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1031 omap_writew(UDC_CLR_EP, UDC_CTRL);
1032 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1033 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1036 udc->ep0_pending = 0;
1040 /* non-empty DATA stage */
1042 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1046 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1049 is_in = ep->bEndpointAddress & USB_DIR_IN;
1051 use_ep(ep, UDC_EP_SEL);
1052 /* if ISO: SOF IRQs must be enabled/disabled! */
1056 (is_in ? next_in_dma : next_out_dma)(ep, req);
1058 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1062 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1063 ep->ackwait = 1 + ep->double_buf;
1065 /* IN: 6 wait states before it'll tx */
1070 /* irq handler advances the queue */
1072 list_add_tail(&req->queue, &ep->queue);
1073 spin_unlock_irqrestore(&udc->lock, flags);
1078 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1080 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1081 struct omap_req *req;
1082 unsigned long flags;
1087 spin_lock_irqsave(&ep->udc->lock, flags);
1089 /* make sure it's actually queued on this endpoint */
1090 list_for_each_entry (req, &ep->queue, queue) {
1091 if (&req->req == _req)
1094 if (&req->req != _req) {
1095 spin_unlock_irqrestore(&ep->udc->lock, flags);
1099 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1100 int channel = ep->dma_channel;
1102 /* releasing the channel cancels the request,
1103 * reclaiming the channel restarts the queue
1105 dma_channel_release(ep);
1106 dma_channel_claim(ep, channel);
1108 done(ep, req, -ECONNRESET);
1109 spin_unlock_irqrestore(&ep->udc->lock, flags);
1113 /*-------------------------------------------------------------------------*/
1115 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1117 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1118 unsigned long flags;
1119 int status = -EOPNOTSUPP;
1121 spin_lock_irqsave(&ep->udc->lock, flags);
1123 /* just use protocol stalls for ep0; real halts are annoying */
1124 if (ep->bEndpointAddress == 0) {
1125 if (!ep->udc->ep0_pending)
1128 if (ep->udc->ep0_set_config) {
1129 WARNING("error changing config?\n");
1130 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1132 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1133 ep->udc->ep0_pending = 0;
1138 /* otherwise, all active non-ISO endpoints can halt */
1139 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1141 /* IN endpoints must already be idle */
1142 if ((ep->bEndpointAddress & USB_DIR_IN)
1143 && !list_empty(&ep->queue)) {
1151 if (use_dma && ep->dma_channel
1152 && !list_empty(&ep->queue)) {
1153 channel = ep->dma_channel;
1154 dma_channel_release(ep);
1158 use_ep(ep, UDC_EP_SEL);
1159 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1160 omap_writew(UDC_SET_HALT, UDC_CTRL);
1167 dma_channel_claim(ep, channel);
1170 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1172 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1173 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1174 ep->ackwait = 1 + ep->double_buf;
1179 VDBG("%s %s halt stat %d\n", ep->ep.name,
1180 value ? "set" : "clear", status);
1182 spin_unlock_irqrestore(&ep->udc->lock, flags);
1186 static struct usb_ep_ops omap_ep_ops = {
1187 .enable = omap_ep_enable,
1188 .disable = omap_ep_disable,
1190 .alloc_request = omap_alloc_request,
1191 .free_request = omap_free_request,
1193 .queue = omap_ep_queue,
1194 .dequeue = omap_ep_dequeue,
1196 .set_halt = omap_ep_set_halt,
1197 // fifo_status ... report bytes in fifo
1198 // fifo_flush ... flush fifo
1201 /*-------------------------------------------------------------------------*/
1203 static int omap_get_frame(struct usb_gadget *gadget)
1205 u16 sof = omap_readw(UDC_SOF);
1206 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1209 static int omap_wakeup(struct usb_gadget *gadget)
1211 struct omap_udc *udc;
1212 unsigned long flags;
1213 int retval = -EHOSTUNREACH;
1215 udc = container_of(gadget, struct omap_udc, gadget);
1217 spin_lock_irqsave(&udc->lock, flags);
1218 if (udc->devstat & UDC_SUS) {
1219 /* NOTE: OTG spec erratum says that OTG devices may
1220 * issue wakeups without host enable.
1222 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1223 DBG("remote wakeup...\n");
1224 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1228 /* NOTE: non-OTG systems may use SRP TOO... */
1229 } else if (!(udc->devstat & UDC_ATT)) {
1230 if (udc->transceiver)
1231 retval = otg_start_srp(udc->transceiver);
1233 spin_unlock_irqrestore(&udc->lock, flags);
1239 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1241 struct omap_udc *udc;
1242 unsigned long flags;
1245 udc = container_of(gadget, struct omap_udc, gadget);
1246 spin_lock_irqsave(&udc->lock, flags);
1247 syscon1 = omap_readw(UDC_SYSCON1);
1249 syscon1 |= UDC_SELF_PWR;
1251 syscon1 &= ~UDC_SELF_PWR;
1252 omap_writew(syscon1, UDC_SYSCON1);
1253 spin_unlock_irqrestore(&udc->lock, flags);
1258 static int can_pullup(struct omap_udc *udc)
1260 return udc->driver && udc->softconnect && udc->vbus_active;
1263 static void pullup_enable(struct omap_udc *udc)
1267 w = omap_readw(UDC_SYSCON1);
1269 omap_writew(w, UDC_SYSCON1);
1270 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1273 l = omap_readl(OTG_CTRL);
1275 omap_writel(l, OTG_CTRL);
1277 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1280 static void pullup_disable(struct omap_udc *udc)
1284 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1287 l = omap_readl(OTG_CTRL);
1289 omap_writel(l, OTG_CTRL);
1291 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1292 w = omap_readw(UDC_SYSCON1);
1293 w &= ~UDC_PULLUP_EN;
1294 omap_writew(w, UDC_SYSCON1);
1297 static struct omap_udc *udc;
1299 static void omap_udc_enable_clock(int enable)
1301 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1305 clk_enable(udc->dc_clk);
1306 clk_enable(udc->hhc_clk);
1309 clk_disable(udc->hhc_clk);
1310 clk_disable(udc->dc_clk);
1315 * Called by whatever detects VBUS sessions: external transceiver
1316 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1318 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1320 struct omap_udc *udc;
1321 unsigned long flags;
1324 udc = container_of(gadget, struct omap_udc, gadget);
1325 spin_lock_irqsave(&udc->lock, flags);
1326 VDBG("VBUS %s\n", is_active ? "on" : "off");
1327 udc->vbus_active = (is_active != 0);
1328 if (cpu_is_omap15xx()) {
1329 /* "software" detect, ignored if !VBUS_MODE_1510 */
1330 l = omap_readl(FUNC_MUX_CTRL_0);
1332 l |= VBUS_CTRL_1510;
1334 l &= ~VBUS_CTRL_1510;
1335 omap_writel(l, FUNC_MUX_CTRL_0);
1337 if (udc->dc_clk != NULL && is_active) {
1338 if (!udc->clk_requested) {
1339 omap_udc_enable_clock(1);
1340 udc->clk_requested = 1;
1343 if (can_pullup(udc))
1346 pullup_disable(udc);
1347 if (udc->dc_clk != NULL && !is_active) {
1348 if (udc->clk_requested) {
1349 omap_udc_enable_clock(0);
1350 udc->clk_requested = 0;
1353 spin_unlock_irqrestore(&udc->lock, flags);
1357 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1359 struct omap_udc *udc;
1361 udc = container_of(gadget, struct omap_udc, gadget);
1362 if (udc->transceiver)
1363 return otg_set_power(udc->transceiver, mA);
1367 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1369 struct omap_udc *udc;
1370 unsigned long flags;
1372 udc = container_of(gadget, struct omap_udc, gadget);
1373 spin_lock_irqsave(&udc->lock, flags);
1374 udc->softconnect = (is_on != 0);
1375 if (can_pullup(udc))
1378 pullup_disable(udc);
1379 spin_unlock_irqrestore(&udc->lock, flags);
1383 static struct usb_gadget_ops omap_gadget_ops = {
1384 .get_frame = omap_get_frame,
1385 .wakeup = omap_wakeup,
1386 .set_selfpowered = omap_set_selfpowered,
1387 .vbus_session = omap_vbus_session,
1388 .vbus_draw = omap_vbus_draw,
1389 .pullup = omap_pullup,
1392 /*-------------------------------------------------------------------------*/
1394 /* dequeue ALL requests; caller holds udc->lock */
1395 static void nuke(struct omap_ep *ep, int status)
1397 struct omap_req *req;
1401 if (use_dma && ep->dma_channel)
1402 dma_channel_release(ep);
1405 omap_writew(UDC_CLR_EP, UDC_CTRL);
1406 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1407 omap_writew(UDC_SET_HALT, UDC_CTRL);
1409 while (!list_empty(&ep->queue)) {
1410 req = list_entry(ep->queue.next, struct omap_req, queue);
1411 done(ep, req, status);
1415 /* caller holds udc->lock */
1416 static void udc_quiesce(struct omap_udc *udc)
1420 udc->gadget.speed = USB_SPEED_UNKNOWN;
1421 nuke(&udc->ep[0], -ESHUTDOWN);
1422 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1423 nuke(ep, -ESHUTDOWN);
1426 /*-------------------------------------------------------------------------*/
1428 static void update_otg(struct omap_udc *udc)
1432 if (!gadget_is_otg(&udc->gadget))
1435 if (omap_readl(OTG_CTRL) & OTG_ID)
1436 devstat = omap_readw(UDC_DEVSTAT);
1440 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1441 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1442 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1444 /* Enable HNP early, avoiding races on suspend irq path.
1445 * ASSUMES OTG state machine B_BUS_REQ input is true.
1447 if (udc->gadget.b_hnp_enable) {
1450 l = omap_readl(OTG_CTRL);
1451 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1453 omap_writel(l, OTG_CTRL);
1457 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1459 struct omap_ep *ep0 = &udc->ep[0];
1460 struct omap_req *req = NULL;
1464 /* Clear any pending requests and then scrub any rx/tx state
1465 * before starting to handle the SETUP request.
1467 if (irq_src & UDC_SETUP) {
1468 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1472 omap_writew(ack, UDC_IRQ_SRC);
1473 irq_src = UDC_SETUP;
1477 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1478 * This driver uses only uses protocol stalls (ep0 never halts),
1479 * and if we got this far the gadget driver already had a
1480 * chance to stall. Tries to be forgiving of host oddities.
1482 * NOTE: the last chance gadget drivers have to stall control
1483 * requests is during their request completion callback.
1485 if (!list_empty(&ep0->queue))
1486 req = container_of(ep0->queue.next, struct omap_req, queue);
1488 /* IN == TX to host */
1489 if (irq_src & UDC_EP0_TX) {
1492 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1493 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1494 stat = omap_readw(UDC_STAT_FLG);
1495 if (stat & UDC_ACK) {
1497 /* write next IN packet from response,
1498 * or set up the status stage.
1501 stat = write_fifo(ep0, req);
1502 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1503 if (!req && udc->ep0_pending) {
1504 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1505 omap_writew(UDC_CLR_EP, UDC_CTRL);
1506 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1507 omap_writew(0, UDC_EP_NUM);
1508 udc->ep0_pending = 0;
1509 } /* else: 6 wait states before it'll tx */
1511 /* ack status stage of OUT transfer */
1512 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1517 } else if (stat & UDC_STALL) {
1518 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1519 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1521 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1525 /* OUT == RX from host */
1526 if (irq_src & UDC_EP0_RX) {
1529 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1530 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1531 stat = omap_readw(UDC_STAT_FLG);
1532 if (stat & UDC_ACK) {
1535 /* read next OUT packet of request, maybe
1536 * reactiviting the fifo; stall on errors.
1538 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1539 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1540 udc->ep0_pending = 0;
1542 } else if (stat == 0)
1543 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1544 omap_writew(0, UDC_EP_NUM);
1546 /* activate status stage */
1549 /* that may have STALLed ep0... */
1550 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1552 omap_writew(UDC_CLR_EP, UDC_CTRL);
1553 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1554 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1555 udc->ep0_pending = 0;
1558 /* ack status stage of IN transfer */
1559 omap_writew(0, UDC_EP_NUM);
1563 } else if (stat & UDC_STALL) {
1564 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1565 omap_writew(0, UDC_EP_NUM);
1567 omap_writew(0, UDC_EP_NUM);
1571 /* SETUP starts all control transfers */
1572 if (irq_src & UDC_SETUP) {
1575 struct usb_ctrlrequest r;
1577 int status = -EINVAL;
1580 /* read the (latest) SETUP message */
1582 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1583 /* two bytes at a time */
1584 u.word[0] = omap_readw(UDC_DATA);
1585 u.word[1] = omap_readw(UDC_DATA);
1586 u.word[2] = omap_readw(UDC_DATA);
1587 u.word[3] = omap_readw(UDC_DATA);
1588 omap_writew(0, UDC_EP_NUM);
1589 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1591 #define w_value le16_to_cpu(u.r.wValue)
1592 #define w_index le16_to_cpu(u.r.wIndex)
1593 #define w_length le16_to_cpu(u.r.wLength)
1595 /* Delegate almost all control requests to the gadget driver,
1596 * except for a handful of ch9 status/feature requests that
1597 * hardware doesn't autodecode _and_ the gadget API hides.
1599 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1600 udc->ep0_set_config = 0;
1601 udc->ep0_pending = 1;
1604 switch (u.r.bRequest) {
1605 case USB_REQ_SET_CONFIGURATION:
1606 /* udc needs to know when ep != 0 is valid */
1607 if (u.r.bRequestType != USB_RECIP_DEVICE)
1611 udc->ep0_set_config = 1;
1612 udc->ep0_reset_config = (w_value == 0);
1613 VDBG("set config %d\n", w_value);
1615 /* update udc NOW since gadget driver may start
1616 * queueing requests immediately; clear config
1617 * later if it fails the request.
1619 if (udc->ep0_reset_config)
1620 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1622 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1625 case USB_REQ_CLEAR_FEATURE:
1626 /* clear endpoint halt */
1627 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1629 if (w_value != USB_ENDPOINT_HALT
1632 ep = &udc->ep[w_index & 0xf];
1634 if (w_index & USB_DIR_IN)
1636 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1640 omap_writew(udc->clr_halt, UDC_CTRL);
1642 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1643 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1644 ep->ackwait = 1 + ep->double_buf;
1646 /* NOTE: assumes the host behaves sanely,
1647 * only clearing real halts. Else we may
1648 * need to kill pending transfers and then
1649 * restart the queue... very messy for DMA!
1652 VDBG("%s halt cleared by host\n", ep->name);
1653 goto ep0out_status_stage;
1654 case USB_REQ_SET_FEATURE:
1655 /* set endpoint halt */
1656 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1658 if (w_value != USB_ENDPOINT_HALT
1661 ep = &udc->ep[w_index & 0xf];
1662 if (w_index & USB_DIR_IN)
1664 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1665 || ep == ep0 || !ep->desc)
1667 if (use_dma && ep->has_dma) {
1668 /* this has rude side-effects (aborts) and
1669 * can't really work if DMA-IN is active
1671 DBG("%s host set_halt, NYET \n", ep->name);
1675 /* can't halt if fifo isn't empty... */
1676 omap_writew(UDC_CLR_EP, UDC_CTRL);
1677 omap_writew(UDC_SET_HALT, UDC_CTRL);
1678 VDBG("%s halted by host\n", ep->name);
1679 ep0out_status_stage:
1681 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1682 omap_writew(UDC_CLR_EP, UDC_CTRL);
1683 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1684 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1685 udc->ep0_pending = 0;
1687 case USB_REQ_GET_STATUS:
1688 /* USB_ENDPOINT_HALT status? */
1689 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1692 /* ep0 never stalls */
1693 if (!(w_index & 0xf))
1696 /* only active endpoints count */
1697 ep = &udc->ep[w_index & 0xf];
1698 if (w_index & USB_DIR_IN)
1703 /* iso never stalls */
1704 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1707 /* FIXME don't assume non-halted endpoints!! */
1708 ERR("%s status, can't report\n", ep->ep.name);
1712 /* return interface status. if we were pedantic,
1713 * we'd detect non-existent interfaces, and stall.
1715 if (u.r.bRequestType
1716 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1720 /* return two zero bytes */
1721 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1722 omap_writew(0, UDC_DATA);
1723 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1724 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1726 VDBG("GET_STATUS, interface %d\n", w_index);
1727 /* next, status stage */
1731 /* activate the ep0out fifo right away */
1732 if (!udc->ep0_in && w_length) {
1733 omap_writew(0, UDC_EP_NUM);
1734 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1737 /* gadget drivers see class/vendor specific requests,
1738 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1741 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1742 u.r.bRequestType, u.r.bRequest,
1743 w_value, w_index, w_length);
1749 /* The gadget driver may return an error here,
1750 * causing an immediate protocol stall.
1752 * Else it must issue a response, either queueing a
1753 * response buffer for the DATA stage, or halting ep0
1754 * (causing a protocol stall, not a real halt). A
1755 * zero length buffer means no DATA stage.
1757 * It's fine to issue that response after the setup()
1758 * call returns, and this IRQ was handled.
1761 spin_unlock(&udc->lock);
1762 status = udc->driver->setup (&udc->gadget, &u.r);
1763 spin_lock(&udc->lock);
1769 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1770 u.r.bRequestType, u.r.bRequest, status);
1771 if (udc->ep0_set_config) {
1772 if (udc->ep0_reset_config)
1773 WARNING("error resetting config?\n");
1775 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1777 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1778 udc->ep0_pending = 0;
1783 /*-------------------------------------------------------------------------*/
1785 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1787 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1789 u16 devstat, change;
1791 devstat = omap_readw(UDC_DEVSTAT);
1792 change = devstat ^ udc->devstat;
1793 udc->devstat = devstat;
1795 if (change & (UDC_USB_RESET|UDC_ATT)) {
1798 if (change & UDC_ATT) {
1799 /* driver for any external transceiver will
1800 * have called omap_vbus_session() already
1802 if (devstat & UDC_ATT) {
1803 udc->gadget.speed = USB_SPEED_FULL;
1805 if (!udc->transceiver)
1807 // if (driver->connect) call it
1808 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1809 udc->gadget.speed = USB_SPEED_UNKNOWN;
1810 if (!udc->transceiver)
1811 pullup_disable(udc);
1812 DBG("disconnect, gadget %s\n",
1813 udc->driver->driver.name);
1814 if (udc->driver->disconnect) {
1815 spin_unlock(&udc->lock);
1816 udc->driver->disconnect(&udc->gadget);
1817 spin_lock(&udc->lock);
1823 if (change & UDC_USB_RESET) {
1824 if (devstat & UDC_USB_RESET) {
1827 udc->gadget.speed = USB_SPEED_FULL;
1828 INFO("USB reset done, gadget %s\n",
1829 udc->driver->driver.name);
1830 /* ep0 traffic is legal from now on */
1831 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1834 change &= ~UDC_USB_RESET;
1837 if (change & UDC_SUS) {
1838 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1839 // FIXME tell isp1301 to suspend/resume (?)
1840 if (devstat & UDC_SUS) {
1843 /* HNP could be under way already */
1844 if (udc->gadget.speed == USB_SPEED_FULL
1845 && udc->driver->suspend) {
1846 spin_unlock(&udc->lock);
1847 udc->driver->suspend(&udc->gadget);
1848 spin_lock(&udc->lock);
1850 if (udc->transceiver)
1851 otg_set_suspend(udc->transceiver, 1);
1854 if (udc->transceiver)
1855 otg_set_suspend(udc->transceiver, 0);
1856 if (udc->gadget.speed == USB_SPEED_FULL
1857 && udc->driver->resume) {
1858 spin_unlock(&udc->lock);
1859 udc->driver->resume(&udc->gadget);
1860 spin_lock(&udc->lock);
1866 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1868 change &= ~OTG_FLAGS;
1871 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1873 VDBG("devstat %03x, ignore change %03x\n",
1876 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1879 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1881 struct omap_udc *udc = _udc;
1883 irqreturn_t status = IRQ_NONE;
1884 unsigned long flags;
1886 spin_lock_irqsave(&udc->lock, flags);
1887 irq_src = omap_readw(UDC_IRQ_SRC);
1889 /* Device state change (usb ch9 stuff) */
1890 if (irq_src & UDC_DS_CHG) {
1891 devstate_irq(_udc, irq_src);
1892 status = IRQ_HANDLED;
1893 irq_src &= ~UDC_DS_CHG;
1896 /* EP0 control transfers */
1897 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1898 ep0_irq(_udc, irq_src);
1899 status = IRQ_HANDLED;
1900 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1903 /* DMA transfer completion */
1904 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1905 dma_irq(_udc, irq_src);
1906 status = IRQ_HANDLED;
1907 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1910 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1912 DBG("udc_irq, unhandled %03x\n", irq_src);
1913 spin_unlock_irqrestore(&udc->lock, flags);
1918 /* workaround for seemingly-lost IRQs for RX ACKs... */
1919 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1920 #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1922 static void pio_out_timer(unsigned long _ep)
1924 struct omap_ep *ep = (void *) _ep;
1925 unsigned long flags;
1928 spin_lock_irqsave(&ep->udc->lock, flags);
1929 if (!list_empty(&ep->queue) && ep->ackwait) {
1930 use_ep(ep, UDC_EP_SEL);
1931 stat_flg = omap_readw(UDC_STAT_FLG);
1933 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1934 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1935 struct omap_req *req;
1937 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1938 req = container_of(ep->queue.next,
1939 struct omap_req, queue);
1940 (void) read_fifo(ep, req);
1941 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1942 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1943 ep->ackwait = 1 + ep->double_buf;
1947 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1948 spin_unlock_irqrestore(&ep->udc->lock, flags);
1951 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1953 u16 epn_stat, irq_src;
1954 irqreturn_t status = IRQ_NONE;
1957 struct omap_udc *udc = _dev;
1958 struct omap_req *req;
1959 unsigned long flags;
1961 spin_lock_irqsave(&udc->lock, flags);
1962 epn_stat = omap_readw(UDC_EPN_STAT);
1963 irq_src = omap_readw(UDC_IRQ_SRC);
1965 /* handle OUT first, to avoid some wasteful NAKs */
1966 if (irq_src & UDC_EPN_RX) {
1967 epnum = (epn_stat >> 8) & 0x0f;
1968 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1969 status = IRQ_HANDLED;
1970 ep = &udc->ep[epnum];
1973 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1975 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1977 if (!list_empty(&ep->queue)) {
1979 req = container_of(ep->queue.next,
1980 struct omap_req, queue);
1981 stat = read_fifo(ep, req);
1982 if (!ep->double_buf)
1986 /* min 6 clock delay before clearing EP_SEL ... */
1987 epn_stat = omap_readw(UDC_EPN_STAT);
1988 epn_stat = omap_readw(UDC_EPN_STAT);
1989 omap_writew(epnum, UDC_EP_NUM);
1991 /* enabling fifo _after_ clearing ACK, contrary to docs,
1992 * reduces lossage; timer still needed though (sigh).
1995 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1996 ep->ackwait = 1 + ep->double_buf;
1998 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
2001 /* then IN transfers */
2002 else if (irq_src & UDC_EPN_TX) {
2003 epnum = epn_stat & 0x0f;
2004 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
2005 status = IRQ_HANDLED;
2006 ep = &udc->ep[16 + epnum];
2009 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
2010 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
2012 if (!list_empty(&ep->queue)) {
2013 req = container_of(ep->queue.next,
2014 struct omap_req, queue);
2015 (void) write_fifo(ep, req);
2018 /* min 6 clock delay before clearing EP_SEL ... */
2019 epn_stat = omap_readw(UDC_EPN_STAT);
2020 epn_stat = omap_readw(UDC_EPN_STAT);
2021 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
2022 /* then 6 clocks before it'd tx */
2025 spin_unlock_irqrestore(&udc->lock, flags);
2030 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2032 struct omap_udc *udc = _dev;
2035 unsigned long flags;
2037 spin_lock_irqsave(&udc->lock, flags);
2039 /* handle all non-DMA ISO transfers */
2040 list_for_each_entry (ep, &udc->iso, iso) {
2042 struct omap_req *req;
2044 if (ep->has_dma || list_empty(&ep->queue))
2046 req = list_entry(ep->queue.next, struct omap_req, queue);
2048 use_ep(ep, UDC_EP_SEL);
2049 stat = omap_readw(UDC_STAT_FLG);
2051 /* NOTE: like the other controller drivers, this isn't
2052 * currently reporting lost or damaged frames.
2054 if (ep->bEndpointAddress & USB_DIR_IN) {
2055 if (stat & UDC_MISS_IN)
2056 /* done(ep, req, -EPROTO) */;
2058 write_fifo(ep, req);
2062 if (stat & UDC_NO_RXPACKET)
2063 status = -EREMOTEIO;
2064 else if (stat & UDC_ISO_ERR)
2066 else if (stat & UDC_DATA_FLUSH)
2070 /* done(ep, req, status) */;
2075 /* 6 wait states before next EP */
2078 if (!list_empty(&ep->queue))
2084 w = omap_readw(UDC_IRQ_EN);
2086 omap_writew(w, UDC_IRQ_EN);
2088 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2090 spin_unlock_irqrestore(&udc->lock, flags);
2095 /*-------------------------------------------------------------------------*/
2097 static inline int machine_without_vbus_sense(void)
2099 return (machine_is_omap_innovator()
2100 || machine_is_omap_osk()
2101 || machine_is_omap_apollon()
2102 #ifndef CONFIG_MACH_OMAP_H4_OTG
2103 || machine_is_omap_h4()
2106 || machine_is_omap_h6300()
2110 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2112 int status = -ENODEV;
2114 unsigned long flags;
2116 /* basic sanity tests */
2120 // FIXME if otg, check: driver->is_otg
2121 || driver->speed < USB_SPEED_FULL
2126 spin_lock_irqsave(&udc->lock, flags);
2128 spin_unlock_irqrestore(&udc->lock, flags);
2133 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2135 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2138 omap_writew(UDC_SET_HALT, UDC_CTRL);
2140 udc->ep0_pending = 0;
2141 udc->ep[0].irqs = 0;
2142 udc->softconnect = 1;
2144 /* hook up the driver */
2145 driver->driver.bus = NULL;
2146 udc->driver = driver;
2147 udc->gadget.dev.driver = &driver->driver;
2148 spin_unlock_irqrestore(&udc->lock, flags);
2150 if (udc->dc_clk != NULL)
2151 omap_udc_enable_clock(1);
2153 status = driver->bind (&udc->gadget);
2155 DBG("bind to %s --> %d\n", driver->driver.name, status);
2156 udc->gadget.dev.driver = NULL;
2160 DBG("bound to driver %s\n", driver->driver.name);
2162 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2164 /* connect to bus through transceiver */
2165 if (udc->transceiver) {
2166 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2168 ERR("can't bind to transceiver\n");
2169 if (driver->unbind) {
2170 driver->unbind (&udc->gadget);
2171 udc->gadget.dev.driver = NULL;
2177 if (can_pullup(udc))
2178 pullup_enable (udc);
2180 pullup_disable (udc);
2183 /* boards that don't have VBUS sensing can't autogate 48MHz;
2184 * can't enter deep sleep while a gadget driver is active.
2186 if (machine_without_vbus_sense())
2187 omap_vbus_session(&udc->gadget, 1);
2190 if (udc->dc_clk != NULL)
2191 omap_udc_enable_clock(0);
2194 EXPORT_SYMBOL(usb_gadget_register_driver);
2196 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2198 unsigned long flags;
2199 int status = -ENODEV;
2203 if (!driver || driver != udc->driver || !driver->unbind)
2206 if (udc->dc_clk != NULL)
2207 omap_udc_enable_clock(1);
2209 if (machine_without_vbus_sense())
2210 omap_vbus_session(&udc->gadget, 0);
2212 if (udc->transceiver)
2213 (void) otg_set_peripheral(udc->transceiver, NULL);
2215 pullup_disable(udc);
2217 spin_lock_irqsave(&udc->lock, flags);
2219 spin_unlock_irqrestore(&udc->lock, flags);
2221 driver->unbind(&udc->gadget);
2222 udc->gadget.dev.driver = NULL;
2225 if (udc->dc_clk != NULL)
2226 omap_udc_enable_clock(0);
2227 DBG("unregistered driver '%s'\n", driver->driver.name);
2230 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2233 /*-------------------------------------------------------------------------*/
2235 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2237 #include <linux/seq_file.h>
2239 static const char proc_filename[] = "driver/udc";
2241 #define FOURBITS "%s%s%s%s"
2242 #define EIGHTBITS FOURBITS FOURBITS
2244 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2247 struct omap_req *req;
2252 if (use_dma && ep->has_dma)
2253 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2254 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2255 ep->dma_channel - 1, ep->lch);
2259 stat_flg = omap_readw(UDC_STAT_FLG);
2261 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2263 ep->double_buf ? "dbuf " : "",
2264 ({char *s; switch(ep->ackwait){
2265 case 0: s = ""; break;
2266 case 1: s = "(ackw) "; break;
2267 case 2: s = "(ackw2) "; break;
2268 default: s = "(?) "; break;
2271 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2272 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2273 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2274 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2275 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2276 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2277 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2278 (stat_flg & UDC_STALL) ? "STALL " : "",
2279 (stat_flg & UDC_NAK) ? "NAK " : "",
2280 (stat_flg & UDC_ACK) ? "ACK " : "",
2281 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2282 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2283 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2285 if (list_empty (&ep->queue))
2286 seq_printf(s, "\t(queue empty)\n");
2288 list_for_each_entry (req, &ep->queue, queue) {
2289 unsigned length = req->req.actual;
2291 if (use_dma && buf[0]) {
2292 length += ((ep->bEndpointAddress & USB_DIR_IN)
2293 ? dma_src_len : dma_dest_len)
2294 (ep, req->req.dma + length);
2297 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2299 req->req.length, req->req.buf);
2303 static char *trx_mode(unsigned m, int enabled)
2306 case 0: return enabled ? "*6wire" : "unused";
2307 case 1: return "4wire";
2308 case 2: return "3wire";
2309 case 3: return "6wire";
2310 default: return "unknown";
2314 static int proc_otg_show(struct seq_file *s)
2320 tmp = omap_readl(OTG_REV);
2321 if (cpu_is_omap24xx()) {
2323 * REVISIT: Not clear how this works on OMAP2. trans
2324 * is ANDed to produce bits 7 and 8, which might make
2325 * sense for USB_TRANSCEIVER_CTRL on OMAP1,
2326 * but with CONTROL_DEVCONF, these bits have something to
2327 * do with the frame adjustment counter and McBSP2.
2329 ctrl_name = "control_devconf";
2330 trans = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
2332 ctrl_name = "tranceiver_ctrl";
2333 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2335 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2336 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2337 tmp = omap_readw(OTG_SYSCON_1);
2338 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2340 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2341 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2342 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2344 : trx_mode(USB0_TRX_MODE(tmp), 1),
2345 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2346 (tmp & HST_IDLE_EN) ? " !host" : "",
2347 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2348 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2349 tmp = omap_readl(OTG_SYSCON_2);
2350 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2351 " b_ase_brst=%d hmc=%d\n", tmp,
2352 (tmp & OTG_EN) ? " otg_en" : "",
2353 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2354 // much more SRP stuff
2355 (tmp & SRP_DATA) ? " srp_data" : "",
2356 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2357 (tmp & OTG_PADEN) ? " otg_paden" : "",
2358 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2359 (tmp & UHOST_EN) ? " uhost_en" : "",
2360 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2361 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2364 tmp = omap_readl(OTG_CTRL);
2365 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2366 (tmp & OTG_ASESSVLD) ? " asess" : "",
2367 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2368 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2369 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2370 (tmp & OTG_ID) ? " id" : "",
2371 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2372 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2373 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2374 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2375 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2376 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2377 (tmp & OTG_PULLDOWN) ? " down" : "",
2378 (tmp & OTG_PULLUP) ? " up" : "",
2379 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2380 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2381 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2382 (tmp & OTG_PU_ID) ? " pu_id" : ""
2384 tmp = omap_readw(OTG_IRQ_EN);
2385 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2386 tmp = omap_readw(OTG_IRQ_SRC);
2387 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2388 tmp = omap_readw(OTG_OUTCTRL);
2389 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2390 tmp = omap_readw(OTG_TEST);
2391 seq_printf(s, "otg_test %04x" "\n", tmp);
2395 static int proc_udc_show(struct seq_file *s, void *_)
2399 unsigned long flags;
2401 spin_lock_irqsave(&udc->lock, flags);
2403 seq_printf(s, "%s, version: " DRIVER_VERSION
2409 use_dma ? " (dma)" : "");
2411 tmp = omap_readw(UDC_REV) & 0xff;
2413 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2414 "hmc %d, transceiver %s\n",
2415 tmp >> 4, tmp & 0xf,
2417 udc->driver ? udc->driver->driver.name : "(none)",
2420 ? udc->transceiver->label
2421 : ((cpu_is_omap1710() || cpu_is_omap24xx())
2422 ? "external" : "(none)"));
2423 if (cpu_class_is_omap1()) {
2424 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2425 omap_readw(ULPD_CLOCK_CTRL),
2426 omap_readw(ULPD_SOFT_REQ),
2427 omap_readw(ULPD_STATUS_REQ));
2430 /* OTG controller registers */
2431 if (!cpu_is_omap15xx())
2434 tmp = omap_readw(UDC_SYSCON1);
2435 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2436 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2437 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2438 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2439 (tmp & UDC_NAK_EN) ? " nak" : "",
2440 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2441 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2442 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2443 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2444 // syscon2 is write-only
2446 /* UDC controller registers */
2447 if (!(tmp & UDC_PULLUP_EN)) {
2448 seq_printf(s, "(suspended)\n");
2449 spin_unlock_irqrestore(&udc->lock, flags);
2453 tmp = omap_readw(UDC_DEVSTAT);
2454 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2455 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2456 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2457 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2458 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2459 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2460 (tmp & UDC_SUS) ? " SUS" : "",
2461 (tmp & UDC_CFG) ? " CFG" : "",
2462 (tmp & UDC_ADD) ? " ADD" : "",
2463 (tmp & UDC_DEF) ? " DEF" : "",
2464 (tmp & UDC_ATT) ? " ATT" : "");
2465 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2466 tmp = omap_readw(UDC_IRQ_EN);
2467 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2468 (tmp & UDC_SOF_IE) ? " sof" : "",
2469 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2470 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2471 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2472 (tmp & UDC_EP0_IE) ? " ep0" : "");
2473 tmp = omap_readw(UDC_IRQ_SRC);
2474 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2475 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2476 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2477 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2478 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2479 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2480 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2481 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2482 (tmp & UDC_SETUP) ? " setup" : "",
2483 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2484 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2488 tmp = omap_readw(UDC_DMA_IRQ_EN);
2489 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2490 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2491 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2492 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2494 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2495 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2496 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2498 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2499 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2500 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2502 tmp = omap_readw(UDC_RXDMA_CFG);
2503 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2505 for (i = 0; i < 3; i++) {
2506 if ((tmp & (0x0f << (i * 4))) == 0)
2508 seq_printf(s, "rxdma[%d] %04x\n", i,
2509 omap_readw(UDC_RXDMA(i + 1)));
2512 tmp = omap_readw(UDC_TXDMA_CFG);
2513 seq_printf(s, "txdma_cfg %04x\n", tmp);
2515 for (i = 0; i < 3; i++) {
2516 if (!(tmp & (0x0f << (i * 4))))
2518 seq_printf(s, "txdma[%d] %04x\n", i,
2519 omap_readw(UDC_TXDMA(i + 1)));
2524 tmp = omap_readw(UDC_DEVSTAT);
2525 if (tmp & UDC_ATT) {
2526 proc_ep_show(s, &udc->ep[0]);
2527 if (tmp & UDC_ADD) {
2528 list_for_each_entry (ep, &udc->gadget.ep_list,
2531 proc_ep_show(s, ep);
2535 spin_unlock_irqrestore(&udc->lock, flags);
2539 static int proc_udc_open(struct inode *inode, struct file *file)
2541 return single_open(file, proc_udc_show, NULL);
2544 static const struct file_operations proc_ops = {
2545 .owner = THIS_MODULE,
2546 .open = proc_udc_open,
2548 .llseek = seq_lseek,
2549 .release = single_release,
2552 static void create_proc_file(void)
2554 proc_create(proc_filename, 0, NULL, &proc_ops);
2557 static void remove_proc_file(void)
2559 remove_proc_entry(proc_filename, NULL);
2564 static inline void create_proc_file(void) {}
2565 static inline void remove_proc_file(void) {}
2569 /*-------------------------------------------------------------------------*/
2571 /* Before this controller can enumerate, we need to pick an endpoint
2572 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2573 * buffer space among the endpoints we'll be operating.
2575 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2576 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
2577 * capability yet though.
2579 static unsigned __init
2580 omap_ep_setup(char *name, u8 addr, u8 type,
2581 unsigned buf, unsigned maxp, int dbuf)
2586 /* OUT endpoints first, then IN */
2587 ep = &udc->ep[addr & 0xf];
2588 if (addr & USB_DIR_IN)
2591 /* in case of ep init table bugs */
2592 BUG_ON(ep->name[0]);
2594 /* chip setup ... bit values are same for IN, OUT */
2595 if (type == USB_ENDPOINT_XFER_ISOC) {
2597 case 8: epn_rxtx = 0 << 12; break;
2598 case 16: epn_rxtx = 1 << 12; break;
2599 case 32: epn_rxtx = 2 << 12; break;
2600 case 64: epn_rxtx = 3 << 12; break;
2601 case 128: epn_rxtx = 4 << 12; break;
2602 case 256: epn_rxtx = 5 << 12; break;
2603 case 512: epn_rxtx = 6 << 12; break;
2606 epn_rxtx |= UDC_EPN_RX_ISO;
2609 /* double-buffering "not supported" on 15xx,
2610 * and ignored for PIO-IN on newer chips
2611 * (for more reliable behavior)
2613 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2617 case 8: epn_rxtx = 0 << 12; break;
2618 case 16: epn_rxtx = 1 << 12; break;
2619 case 32: epn_rxtx = 2 << 12; break;
2620 case 64: epn_rxtx = 3 << 12; break;
2624 epn_rxtx |= UDC_EPN_RX_DB;
2625 init_timer(&ep->timer);
2626 ep->timer.function = pio_out_timer;
2627 ep->timer.data = (unsigned long) ep;
2630 epn_rxtx |= UDC_EPN_RX_VALID;
2632 epn_rxtx |= buf >> 3;
2634 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2635 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2637 if (addr & USB_DIR_IN)
2638 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2640 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2642 /* next endpoint's buffer starts after this one's */
2648 /* set up driver data structures */
2649 BUG_ON(strlen(name) >= sizeof ep->name);
2650 strlcpy(ep->name, name, sizeof ep->name);
2651 INIT_LIST_HEAD(&ep->queue);
2652 INIT_LIST_HEAD(&ep->iso);
2653 ep->bEndpointAddress = addr;
2654 ep->bmAttributes = type;
2655 ep->double_buf = dbuf;
2658 ep->ep.name = ep->name;
2659 ep->ep.ops = &omap_ep_ops;
2660 ep->ep.maxpacket = ep->maxpacket = maxp;
2661 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2666 static void omap_udc_release(struct device *dev)
2668 complete(udc->done);
2674 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2678 /* abolish any previous hardware state */
2679 omap_writew(0, UDC_SYSCON1);
2680 omap_writew(0, UDC_IRQ_EN);
2681 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2682 omap_writew(0, UDC_DMA_IRQ_EN);
2683 omap_writew(0, UDC_RXDMA_CFG);
2684 omap_writew(0, UDC_TXDMA_CFG);
2686 /* UDC_PULLUP_EN gates the chip clock */
2687 // OTG_SYSCON_1 |= DEV_IDLE_EN;
2689 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2693 spin_lock_init (&udc->lock);
2695 udc->gadget.ops = &omap_gadget_ops;
2696 udc->gadget.ep0 = &udc->ep[0].ep;
2697 INIT_LIST_HEAD(&udc->gadget.ep_list);
2698 INIT_LIST_HEAD(&udc->iso);
2699 udc->gadget.speed = USB_SPEED_UNKNOWN;
2700 udc->gadget.name = driver_name;
2702 device_initialize(&udc->gadget.dev);
2703 dev_set_name(&udc->gadget.dev, "gadget");
2704 udc->gadget.dev.release = omap_udc_release;
2705 udc->gadget.dev.parent = &odev->dev;
2707 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2709 udc->transceiver = xceiv;
2711 /* ep0 is special; put it right after the SETUP buffer */
2712 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2713 8 /* after SETUP */, 64 /* maxpacket */, 0);
2714 list_del_init(&udc->ep[0].ep.ep_list);
2716 /* initially disable all non-ep0 endpoints */
2717 for (tmp = 1; tmp < 15; tmp++) {
2718 omap_writew(0, UDC_EP_RX(tmp));
2719 omap_writew(0, UDC_EP_TX(tmp));
2722 #define OMAP_BULK_EP(name,addr) \
2723 buf = omap_ep_setup(name "-bulk", addr, \
2724 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2725 #define OMAP_INT_EP(name,addr, maxp) \
2726 buf = omap_ep_setup(name "-int", addr, \
2727 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2728 #define OMAP_ISO_EP(name,addr, maxp) \
2729 buf = omap_ep_setup(name "-iso", addr, \
2730 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2732 switch (fifo_mode) {
2734 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2735 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2736 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2739 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2740 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2741 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2743 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2744 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2745 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2747 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2748 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2749 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2751 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2752 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2753 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2755 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2756 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2757 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2758 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2760 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2761 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2762 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2763 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2765 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2766 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2771 case 2: /* mixed iso/bulk */
2772 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2773 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2774 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2775 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2777 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2779 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2780 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2781 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2783 case 3: /* mixed bulk/iso */
2784 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2785 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2786 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2788 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2789 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2790 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2792 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2793 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2794 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2798 /* add more modes as needed */
2801 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2804 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2805 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2809 static int __init omap_udc_probe(struct platform_device *pdev)
2811 int status = -ENODEV;
2813 struct otg_transceiver *xceiv = NULL;
2814 const char *type = NULL;
2815 struct omap_usb_config *config = pdev->dev.platform_data;
2817 struct clk *hhc_clk;
2819 /* NOTE: "knows" the order of the resources! */
2820 if (!request_mem_region(pdev->resource[0].start,
2821 pdev->resource[0].end - pdev->resource[0].start + 1,
2823 DBG("request_mem_region failed\n");
2827 if (cpu_is_omap16xx()) {
2828 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2829 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2830 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2831 /* can't use omap_udc_enable_clock yet */
2833 clk_enable(hhc_clk);
2837 if (cpu_is_omap24xx()) {
2838 dc_clk = clk_get(&pdev->dev, "usb_fck");
2839 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2840 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2841 /* can't use omap_udc_enable_clock yet */
2843 clk_enable(hhc_clk);
2847 INFO("OMAP UDC rev %d.%d%s\n",
2848 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2849 config->otg ? ", Mini-AB" : "");
2851 /* use the mode given to us by board init code */
2852 if (cpu_is_omap15xx()) {
2856 if (machine_without_vbus_sense()) {
2857 /* just set up software VBUS detect, and then
2858 * later rig it so we always report VBUS.
2859 * FIXME without really sensing VBUS, we can't
2860 * know when to turn PULLUP_EN on/off; and that
2861 * means we always "need" the 48MHz clock.
2863 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2864 tmp &= ~VBUS_CTRL_1510;
2865 omap_writel(tmp, FUNC_MUX_CTRL_0);
2866 tmp |= VBUS_MODE_1510;
2867 tmp &= ~VBUS_CTRL_1510;
2868 omap_writel(tmp, FUNC_MUX_CTRL_0);
2871 /* The transceiver may package some GPIO logic or handle
2872 * loopback and/or transceiverless setup; if we find one,
2873 * use it. Except for OTG, we don't _need_ to talk to one;
2874 * but not having one probably means no VBUS detection.
2876 xceiv = otg_get_transceiver();
2878 type = xceiv->label;
2879 else if (config->otg) {
2880 DBG("OTG requires external transceiver!\n");
2886 if (cpu_is_omap24xx()) {
2887 /* this could be transceiverless in one of the
2888 * "we don't need to know" modes.
2895 case 0: /* POWERUP DEFAULT == 0 */
2899 if (!cpu_is_omap1710()) {
2900 type = "integrated";
2910 DBG("external transceiver not registered!\n");
2914 case 21: /* internal loopback */
2917 case 14: /* transceiverless */
2918 if (cpu_is_omap1710())
2928 ERR("unrecognized UDC HMC mode %d\n", hmc);
2933 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2935 /* a "gadget" abstracts/virtualizes the controller */
2936 status = omap_udc_setup(pdev, xceiv);
2941 // "udc" is now valid
2942 pullup_disable(udc);
2943 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2944 udc->gadget.is_otg = (config->otg != 0);
2947 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2948 if (omap_readw(UDC_REV) >= 0x61)
2949 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2951 udc->clr_halt = UDC_RESET_EP;
2953 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2954 status = request_irq(pdev->resource[1].start, omap_udc_irq,
2955 IRQF_SAMPLE_RANDOM, driver_name, udc);
2957 ERR("can't get irq %d, err %d\n",
2958 (int) pdev->resource[1].start, status);
2962 /* USB "non-iso" IRQ (PIO for all but ep0) */
2963 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2964 IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2966 ERR("can't get irq %d, err %d\n",
2967 (int) pdev->resource[2].start, status);
2971 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2972 IRQF_DISABLED, "omap_udc iso", udc);
2974 ERR("can't get irq %d, err %d\n",
2975 (int) pdev->resource[3].start, status);
2979 if (cpu_is_omap16xx()) {
2980 udc->dc_clk = dc_clk;
2981 udc->hhc_clk = hhc_clk;
2982 clk_disable(hhc_clk);
2983 clk_disable(dc_clk);
2986 if (cpu_is_omap24xx()) {
2987 udc->dc_clk = dc_clk;
2988 udc->hhc_clk = hhc_clk;
2989 /* FIXME OMAP2 don't release hhc & dc clock */
2991 clk_disable(hhc_clk);
2992 clk_disable(dc_clk);
2997 status = device_add(&udc->gadget.dev);
3000 /* If fail, fall through */
3003 free_irq(pdev->resource[2].start, udc);
3007 free_irq(pdev->resource[1].start, udc);
3015 otg_put_transceiver(xceiv);
3017 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
3018 clk_disable(hhc_clk);
3019 clk_disable(dc_clk);
3024 release_mem_region(pdev->resource[0].start,
3025 pdev->resource[0].end - pdev->resource[0].start + 1);
3030 static int __exit omap_udc_remove(struct platform_device *pdev)
3032 DECLARE_COMPLETION_ONSTACK(done);
3041 pullup_disable(udc);
3042 if (udc->transceiver) {
3043 otg_put_transceiver(udc->transceiver);
3044 udc->transceiver = NULL;
3046 omap_writew(0, UDC_SYSCON1);
3051 free_irq(pdev->resource[3].start, udc);
3053 free_irq(pdev->resource[2].start, udc);
3054 free_irq(pdev->resource[1].start, udc);
3057 if (udc->clk_requested)
3058 omap_udc_enable_clock(0);
3059 clk_put(udc->hhc_clk);
3060 clk_put(udc->dc_clk);
3063 release_mem_region(pdev->resource[0].start,
3064 pdev->resource[0].end - pdev->resource[0].start + 1);
3066 device_unregister(&udc->gadget.dev);
3067 wait_for_completion(&done);
3072 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3073 * system is forced into deep sleep
3075 * REVISIT we should probably reject suspend requests when there's a host
3076 * session active, rather than disconnecting, at least on boards that can
3077 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
3078 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3079 * may involve talking to an external transceiver (e.g. isp1301).
3082 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3086 devstat = omap_readw(UDC_DEVSTAT);
3088 /* we're requesting 48 MHz clock if the pullup is enabled
3089 * (== we're attached to the host) and we're not suspended,
3090 * which would prevent entry to deep sleep...
3092 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3093 WARNING("session active; suspend requires disconnect\n");
3094 omap_pullup(&udc->gadget, 0);
3100 static int omap_udc_resume(struct platform_device *dev)
3102 DBG("resume + wakeup/SRP\n");
3103 omap_pullup(&udc->gadget, 1);
3105 /* maybe the host would enumerate us if we nudged it */
3107 return omap_wakeup(&udc->gadget);
3110 /*-------------------------------------------------------------------------*/
3112 static struct platform_driver udc_driver = {
3113 .probe = omap_udc_probe,
3114 .remove = __exit_p(omap_udc_remove),
3115 .suspend = omap_udc_suspend,
3116 .resume = omap_udc_resume,
3118 .owner = THIS_MODULE,
3119 .name = (char *) driver_name,
3123 static int __init udc_init(void)
3125 INFO("%s, version: " DRIVER_VERSION
3129 "%s\n", driver_desc,
3130 use_dma ? " (dma)" : "");
3131 return platform_driver_register(&udc_driver);
3133 module_init(udc_init);
3135 static void __exit udc_exit(void)
3137 platform_driver_unregister(&udc_driver);
3139 module_exit(udc_exit);
3141 MODULE_DESCRIPTION(DRIVER_DESC);
3142 MODULE_LICENSE("GPL");
3143 MODULE_ALIAS("platform:omap_udc");