drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #undef  DEBUG
  25 #undef  VERBOSE
  26
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/ioport.h>
  30 #include <linux/types.h>
  31 #include <linux/errno.h>
  32 #include <linux/delay.h>
  33 #include <linux/slab.h>
  34 #include <linux/init.h>
  35 #include <linux/timer.h>
  36 #include <linux/list.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/proc_fs.h>
  39 #include <linux/mm.h>
  40 #include <linux/moduleparam.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/usb/ch9.h>
  43 #include <linux/usb/gadget.h>
  44 #include <linux/usb/otg.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/clk.h>
  47
  48 #include <asm/byteorder.h>
  49 #include <asm/io.h>
  50 #include <asm/irq.h>
  51 #include <asm/system.h>
  52 #include <asm/unaligned.h>
  53 #include <asm/mach-types.h>
  54
  55 #include <mach/dma.h>
  56 #include <mach/usb.h>
  57 #include <mach/control.h>
  58
  59 #include "omap_udc.h"
  60
  61 #undef  USB_TRACE
  62
  63 /* bulk DMA seems to be behaving for both IN and OUT */
  64 #ifdef CONFIG_MACH_OMAP_H6300
  65 #undef USE_DMA
  66 #else
  67 #define USE_DMA
  68 #endif
  69
  70 /* ISO too */
  71 #define USE_ISO
  72
  73 #define DRIVER_DESC     "OMAP UDC driver"
  74 #define DRIVER_VERSION  "4 October 2004"
  75
  76 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  77
  78 #define OMAP2_DMA_CH(ch)        (((ch) - 1) << 1)
  79 #define OMAP24XX_DMA(name, ch)  (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
  80
  81 /*
  82  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  83  * D+ pullup to allow enumeration.  That's too early for the gadget
  84  * framework to use from usb_endpoint_enable(), which happens after
  85  * enumeration as part of activating an interface.  (But if we add an
  86  * optional new "UDC not yet running" state to the gadget driver model,
  87  * even just during driver binding, the endpoint autoconfig logic is the
  88  * natural spot to manufacture new endpoints.)
  89  *
  90  * So instead of using endpoint enable calls to control the hardware setup,
  91  * this driver defines a "fifo mode" parameter.  It's used during driver
  92  * initialization to choose among a set of pre-defined endpoint configs.
  93  * See omap_udc_setup() for available modes, or to add others.  That code
  94  * lives in an init section, so use this driver as a module if you need
  95  * to change the fifo mode after the kernel boots.
  96  *
  97  * Gadget drivers normally ignore endpoints they don't care about, and
  98  * won't include them in configuration descriptors.  That means only
  99  * misbehaving hosts would even notice they exist.
 100  */
 101 #ifdef  USE_ISO
 102 static unsigned fifo_mode = 3;
 103 #else
 104 static unsigned fifo_mode = 0;
 105 #endif
 106
 107 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 108  * boot parameter "omap_udc:fifo_mode=42"
 109  */
 110 module_param (fifo_mode, uint, 0);
 111 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
 112
 113 #ifdef  USE_DMA
 114 static unsigned use_dma = 1;
 115
 116 /* "modprobe omap_udc use_dma=y", or else as a kernel
 117  * boot parameter "omap_udc:use_dma=y"
 118  */
 119 module_param (use_dma, bool, 0);
 120 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 121 #else   /* !USE_DMA */
 122
 123 /* save a bit of code */
 124 #define use_dma         0
 125 #endif  /* !USE_DMA */
 126
 127
 128 static const char driver_name [] = "omap_udc";
 129 static const char driver_desc [] = DRIVER_DESC;
 130
 131 /*-------------------------------------------------------------------------*/
 132
 133 /* there's a notion of "current endpoint" for modifying endpoint
 134  * state, and PIO access to its FIFO.
 135  */
 136
 137 static void use_ep(struct omap_ep *ep, u16 select)
 138 {
 139         u16     num = ep->bEndpointAddress & 0x0f;
 140
 141         if (ep->bEndpointAddress & USB_DIR_IN)
 142                 num |= UDC_EP_DIR;
 143         omap_writew(num | select, UDC_EP_NUM);
 144         /* when select, MUST deselect later !! */
 145 }
 146
 147 static inline void deselect_ep(void)
 148 {
 149         u16 w;
 150
 151         w = omap_readw(UDC_EP_NUM);
 152         w &= ~UDC_EP_SEL;
 153         omap_writew(w, UDC_EP_NUM);
 154         /* 6 wait states before TX will happen */
 155 }
 156
 157 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 158
 159 /*-------------------------------------------------------------------------*/
 160
 161 static int omap_ep_enable(struct usb_ep *_ep,
 162                 const struct usb_endpoint_descriptor *desc)
 163 {
 164         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 165         struct omap_udc *udc;
 166         unsigned long   flags;
 167         u16             maxp;
 168
 169         /* catch various bogus parameters */
 170         if (!_ep || !desc || ep->desc
 171                         || desc->bDescriptorType != USB_DT_ENDPOINT
 172                         || ep->bEndpointAddress != desc->bEndpointAddress
 173                         || ep->maxpacket < le16_to_cpu
 174                                                 (desc->wMaxPacketSize)) {
 175                 DBG("%s, bad ep or descriptor\n", __func__);
 176                 return -EINVAL;
 177         }
 178         maxp = le16_to_cpu (desc->wMaxPacketSize);
 179         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 180                                 && maxp != ep->maxpacket)
 181                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 182                         || !desc->wMaxPacketSize) {
 183                 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
 184                 return -ERANGE;
 185         }
 186
 187 #ifdef  USE_ISO
 188         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 189                                 && desc->bInterval != 1)) {
 190                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 191                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 192                                 1 << (desc->bInterval - 1));
 193                 return -EDOM;
 194         }
 195 #else
 196         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 197                 DBG("%s, ISO nyet\n", _ep->name);
 198                 return -EDOM;
 199         }
 200 #endif
 201
 202         /* xfer types must match, except that interrupt ~= bulk */
 203         if (ep->bmAttributes != desc->bmAttributes
 204                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 205                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 206                 DBG("%s, %s type mismatch\n", __func__, _ep->name);
 207                 return -EINVAL;
 208         }
 209
 210         udc = ep->udc;
 211         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 212                 DBG("%s, bogus device state\n", __func__);
 213                 return -ESHUTDOWN;
 214         }
 215
 216         spin_lock_irqsave(&udc->lock, flags);
 217
 218         ep->desc = desc;
 219         ep->irqs = 0;
 220         ep->stopped = 0;
 221         ep->ep.maxpacket = maxp;
 222
 223         /* set endpoint to initial state */
 224         ep->dma_channel = 0;
 225         ep->has_dma = 0;
 226         ep->lch = -1;
 227         use_ep(ep, UDC_EP_SEL);
 228         omap_writew(udc->clr_halt, UDC_CTRL);
 229         ep->ackwait = 0;
 230         deselect_ep();
 231
 232         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 233                 list_add(&ep->iso, &udc->iso);
 234
 235         /* maybe assign a DMA channel to this endpoint */
 236         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 237                 /* FIXME ISO can dma, but prefers first channel */
 238                 dma_channel_claim(ep, 0);
 239
 240         /* PIO OUT may RX packets */
 241         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 242                         && !ep->has_dma
 243                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 244                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 245                 ep->ackwait = 1 + ep->double_buf;
 246         }
 247
 248         spin_unlock_irqrestore(&udc->lock, flags);
 249         VDBG("%s enabled\n", _ep->name);
 250         return 0;
 251 }
 252
 253 static void nuke(struct omap_ep *, int status);
 254
 255 static int omap_ep_disable(struct usb_ep *_ep)
 256 {
 257         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 258         unsigned long   flags;
 259
 260         if (!_ep || !ep->desc) {
 261                 DBG("%s, %s not enabled\n", __func__,
 262                         _ep ? ep->ep.name : NULL);
 263                 return -EINVAL;
 264         }
 265
 266         spin_lock_irqsave(&ep->udc->lock, flags);
 267         ep->desc = NULL;
 268         nuke (ep, -ESHUTDOWN);
 269         ep->ep.maxpacket = ep->maxpacket;
 270         ep->has_dma = 0;
 271         omap_writew(UDC_SET_HALT, UDC_CTRL);
 272         list_del_init(&ep->iso);
 273         del_timer(&ep->timer);
 274
 275         spin_unlock_irqrestore(&ep->udc->lock, flags);
 276
 277         VDBG("%s disabled\n", _ep->name);
 278         return 0;
 279 }
 280
 281 /*-------------------------------------------------------------------------*/
 282
 283 static struct usb_request *
 284 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 285 {
 286         struct omap_req *req;
 287
 288         req = kzalloc(sizeof(*req), gfp_flags);
 289         if (req) {
 290                 req->req.dma = DMA_ADDR_INVALID;
 291                 INIT_LIST_HEAD (&req->queue);
 292         }
 293         return &req->req;
 294 }
 295
 296 static void
 297 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 298 {
 299         struct omap_req *req = container_of(_req, struct omap_req, req);
 300
 301         if (_req)
 302                 kfree (req);
 303 }
 304
 305 /*-------------------------------------------------------------------------*/
 306
 307 static void
 308 done(struct omap_ep *ep, struct omap_req *req, int status)
 309 {
 310         unsigned                stopped = ep->stopped;
 311
 312         list_del_init(&req->queue);
 313
 314         if (req->req.status == -EINPROGRESS)
 315                 req->req.status = status;
 316         else
 317                 status = req->req.status;
 318
 319         if (use_dma && ep->has_dma) {
 320                 if (req->mapped) {
 321                         dma_unmap_single(ep->udc->gadget.dev.parent,
 322                                 req->req.dma, req->req.length,
 323                                 (ep->bEndpointAddress & USB_DIR_IN)
 324                                         ? DMA_TO_DEVICE
 325                                         : DMA_FROM_DEVICE);
 326                         req->req.dma = DMA_ADDR_INVALID;
 327                         req->mapped = 0;
 328                 } else
 329                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 330                                 req->req.dma, req->req.length,
 331                                 (ep->bEndpointAddress & USB_DIR_IN)
 332                                         ? DMA_TO_DEVICE
 333                                         : DMA_FROM_DEVICE);
 334         }
 335
 336 #ifndef USB_TRACE
 337         if (status && status != -ESHUTDOWN)
 338 #endif
 339                 VDBG("complete %s req %p stat %d len %u/%u\n",
 340                         ep->ep.name, &req->req, status,
 341                         req->req.actual, req->req.length);
 342
 343         /* don't modify queue heads during completion callback */
 344         ep->stopped = 1;
 345         spin_unlock(&ep->udc->lock);
 346         req->req.complete(&ep->ep, &req->req);
 347         spin_lock(&ep->udc->lock);
 348         ep->stopped = stopped;
 349 }
 350
 351 /*-------------------------------------------------------------------------*/
 352
 353 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 354 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 355
 356 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 357 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 358
 359 static inline int
 360 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 361 {
 362         unsigned        len;
 363         u16             *wp;
 364
 365         len = min(req->req.length - req->req.actual, max);
 366         req->req.actual += len;
 367
 368         max = len;
 369         if (likely((((int)buf) & 1) == 0)) {
 370                 wp = (u16 *)buf;
 371                 while (max >= 2) {
 372                         omap_writew(*wp++, UDC_DATA);
 373                         max -= 2;
 374                 }
 375                 buf = (u8 *)wp;
 376         }
 377         while (max--)
 378                 omap_writeb(*buf++, UDC_DATA);
 379         return len;
 380 }
 381
 382 // FIXME change r/w fifo calling convention
 383
 384
 385 // return:  0 = still running, 1 = completed, negative = errno
 386 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 387 {
 388         u8              *buf;
 389         unsigned        count;
 390         int             is_last;
 391         u16             ep_stat;
 392
 393         buf = req->req.buf + req->req.actual;
 394         prefetch(buf);
 395
 396         /* PIO-IN isn't double buffered except for iso */
 397         ep_stat = omap_readw(UDC_STAT_FLG);
 398         if (ep_stat & UDC_FIFO_UNWRITABLE)
 399                 return 0;
 400
 401         count = ep->ep.maxpacket;
 402         count = write_packet(buf, req, count);
 403         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 404         ep->ackwait = 1;
 405
 406         /* last packet is often short (sometimes a zlp) */
 407         if (count != ep->ep.maxpacket)
 408                 is_last = 1;
 409         else if (req->req.length == req->req.actual
 410                         && !req->req.zero)
 411                 is_last = 1;
 412         else
 413                 is_last = 0;
 414
 415         /* NOTE:  requests complete when all IN data is in a
 416          * FIFO (or sometimes later, if a zlp was needed).
 417          * Use usb_ep_fifo_status() where needed.
 418          */
 419         if (is_last)
 420                 done(ep, req, 0);
 421         return is_last;
 422 }
 423
 424 static inline int
 425 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 426 {
 427         unsigned        len;
 428         u16             *wp;
 429
 430         len = min(req->req.length - req->req.actual, avail);
 431         req->req.actual += len;
 432         avail = len;
 433
 434         if (likely((((int)buf) & 1) == 0)) {
 435                 wp = (u16 *)buf;
 436                 while (avail >= 2) {
 437                         *wp++ = omap_readw(UDC_DATA);
 438                         avail -= 2;
 439                 }
 440                 buf = (u8 *)wp;
 441         }
 442         while (avail--)
 443                 *buf++ = omap_readb(UDC_DATA);
 444         return len;
 445 }
 446
 447 // return:  0 = still running, 1 = queue empty, negative = errno
 448 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 449 {
 450         u8              *buf;
 451         unsigned        count, avail;
 452         int             is_last;
 453
 454         buf = req->req.buf + req->req.actual;
 455         prefetchw(buf);
 456
 457         for (;;) {
 458                 u16     ep_stat = omap_readw(UDC_STAT_FLG);
 459
 460                 is_last = 0;
 461                 if (ep_stat & FIFO_EMPTY) {
 462                         if (!ep->double_buf)
 463                                 break;
 464                         ep->fnf = 1;
 465                 }
 466                 if (ep_stat & UDC_EP_HALTED)
 467                         break;
 468
 469                 if (ep_stat & UDC_FIFO_FULL)
 470                         avail = ep->ep.maxpacket;
 471                 else  {
 472                         avail = omap_readw(UDC_RXFSTAT);
 473                         ep->fnf = ep->double_buf;
 474                 }
 475                 count = read_packet(buf, req, avail);
 476
 477                 /* partial packet reads may not be errors */
 478                 if (count < ep->ep.maxpacket) {
 479                         is_last = 1;
 480                         /* overflowed this request?  flush extra data */
 481                         if (count != avail) {
 482                                 req->req.status = -EOVERFLOW;
 483                                 avail -= count;
 484                                 while (avail--)
 485                                         omap_readw(UDC_DATA);
 486                         }
 487                 } else if (req->req.length == req->req.actual)
 488                         is_last = 1;
 489                 else
 490                         is_last = 0;
 491
 492                 if (!ep->bEndpointAddress)
 493                         break;
 494                 if (is_last)
 495                         done(ep, req, 0);
 496                 break;
 497         }
 498         return is_last;
 499 }
 500
 501 /*-------------------------------------------------------------------------*/
 502
 503 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 504 {
 505         dma_addr_t      end;
 506
 507         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 508          * the last transfer's bytecount by more than a FIFO's worth.
 509          */
 510         if (cpu_is_omap15xx())
 511                 return 0;
 512
 513         end = omap_get_dma_src_pos(ep->lch);
 514         if (end == ep->dma_counter)
 515                 return 0;
 516
 517         end |= start & (0xffff << 16);
 518         if (end < start)
 519                 end += 0x10000;
 520         return end - start;
 521 }
 522
 523 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 524 {
 525         dma_addr_t      end;
 526
 527         end = omap_get_dma_dst_pos(ep->lch);
 528         if (end == ep->dma_counter)
 529                 return 0;
 530
 531         end |= start & (0xffff << 16);
 532         if (cpu_is_omap15xx())
 533                 end++;
 534         if (end < start)
 535                 end += 0x10000;
 536         return end - start;
 537 }
 538
 539
 540 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 541  * When DMA completion isn't request completion, the UDC continues with
 542  * the next DMA transfer for that USB transfer.
 543  */
 544
 545 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 546 {
 547         u16             txdma_ctrl, w;
 548         unsigned        length = req->req.length - req->req.actual;
 549         const int       sync_mode = cpu_is_omap15xx()
 550                                 ? OMAP_DMA_SYNC_FRAME
 551                                 : OMAP_DMA_SYNC_ELEMENT;
 552         int             dma_trigger = 0;
 553
 554         if (cpu_is_omap24xx())
 555                 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
 556
 557         /* measure length in either bytes or packets */
 558         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 559                         || (cpu_is_omap24xx() && length < ep->maxpacket)
 560                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 561                 txdma_ctrl = UDC_TXN_EOT | length;
 562                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 563                                 length, 1, sync_mode, dma_trigger, 0);
 564         } else {
 565                 length = min(length / ep->maxpacket,
 566                                 (unsigned) UDC_TXN_TSC + 1);
 567                 txdma_ctrl = length;
 568                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 569                                 ep->ep.maxpacket >> 1, length, sync_mode,
 570                                 dma_trigger, 0);
 571                 length *= ep->maxpacket;
 572         }
 573         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 574                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 575                 0, 0);
 576
 577         omap_start_dma(ep->lch);
 578         ep->dma_counter = omap_get_dma_src_pos(ep->lch);
 579         w = omap_readw(UDC_DMA_IRQ_EN);
 580         w |= UDC_TX_DONE_IE(ep->dma_channel);
 581         omap_writew(w, UDC_DMA_IRQ_EN);
 582         omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
 583         req->dma_bytes = length;
 584 }
 585
 586 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 587 {
 588         u16 w;
 589
 590         if (status == 0) {
 591                 req->req.actual += req->dma_bytes;
 592
 593                 /* return if this request needs to send data or zlp */
 594                 if (req->req.actual < req->req.length)
 595                         return;
 596                 if (req->req.zero
 597                                 && req->dma_bytes != 0
 598                                 && (req->req.actual % ep->maxpacket) == 0)
 599                         return;
 600         } else
 601                 req->req.actual += dma_src_len(ep, req->req.dma
 602                                                         + req->req.actual);
 603
 604         /* tx completion */
 605         omap_stop_dma(ep->lch);
 606         w = omap_readw(UDC_DMA_IRQ_EN);
 607         w &= ~UDC_TX_DONE_IE(ep->dma_channel);
 608         omap_writew(w, UDC_DMA_IRQ_EN);
 609         done(ep, req, status);
 610 }
 611
 612 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 613 {
 614         unsigned packets = req->req.length - req->req.actual;
 615         int dma_trigger = 0;
 616         u16 w;
 617
 618         if (cpu_is_omap24xx())
 619                 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
 620
 621         /* NOTE:  we filtered out "short reads" before, so we know
 622          * the buffer has only whole numbers of packets.
 623          * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
 624          */
 625         if (cpu_is_omap24xx() && packets < ep->maxpacket) {
 626                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 627                                 packets, 1, OMAP_DMA_SYNC_ELEMENT,
 628                                 dma_trigger, 0);
 629                 req->dma_bytes = packets;
 630         } else {
 631                 /* set up this DMA transfer, enable the fifo, start */
 632                 packets /= ep->ep.maxpacket;
 633                 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 634                 req->dma_bytes = packets * ep->ep.maxpacket;
 635                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 636                                 ep->ep.maxpacket >> 1, packets,
 637                                 OMAP_DMA_SYNC_ELEMENT,
 638                                 dma_trigger, 0);
 639         }
 640         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 641                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 642                 0, 0);
 643         ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
 644
 645         omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
 646         w = omap_readw(UDC_DMA_IRQ_EN);
 647         w |= UDC_RX_EOT_IE(ep->dma_channel);
 648         omap_writew(w, UDC_DMA_IRQ_EN);
 649         omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
 650         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 651
 652         omap_start_dma(ep->lch);
 653 }
 654
 655 static void
 656 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 657 {
 658         u16     count, w;
 659
 660         if (status == 0)
 661                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 662         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 663         count += req->req.actual;
 664         if (one)
 665                 count--;
 666         if (count <= req->req.length)
 667                 req->req.actual = count;
 668
 669         if (count != req->dma_bytes || status)
 670                 omap_stop_dma(ep->lch);
 671
 672         /* if this wasn't short, request may need another transfer */
 673         else if (req->req.actual < req->req.length)
 674                 return;
 675
 676         /* rx completion */
 677         w = omap_readw(UDC_DMA_IRQ_EN);
 678         w &= ~UDC_RX_EOT_IE(ep->dma_channel);
 679         omap_writew(w, UDC_DMA_IRQ_EN);
 680         done(ep, req, status);
 681 }
 682
 683 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 684 {
 685         u16             dman_stat = omap_readw(UDC_DMAN_STAT);
 686         struct omap_ep  *ep;
 687         struct omap_req *req;
 688
 689         /* IN dma: tx to host */
 690         if (irq_src & UDC_TXN_DONE) {
 691                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 692                 ep->irqs++;
 693                 /* can see TXN_DONE after dma abort */
 694                 if (!list_empty(&ep->queue)) {
 695                         req = container_of(ep->queue.next,
 696                                                 struct omap_req, queue);
 697                         finish_in_dma(ep, req, 0);
 698                 }
 699                 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
 700
 701                 if (!list_empty (&ep->queue)) {
 702                         req = container_of(ep->queue.next,
 703                                         struct omap_req, queue);
 704                         next_in_dma(ep, req);
 705                 }
 706         }
 707
 708         /* OUT dma: rx from host */
 709         if (irq_src & UDC_RXN_EOT) {
 710                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 711                 ep->irqs++;
 712                 /* can see RXN_EOT after dma abort */
 713                 if (!list_empty(&ep->queue)) {
 714                         req = container_of(ep->queue.next,
 715                                         struct omap_req, queue);
 716                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 717                 }
 718                 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
 719
 720                 if (!list_empty (&ep->queue)) {
 721                         req = container_of(ep->queue.next,
 722                                         struct omap_req, queue);
 723                         next_out_dma(ep, req);
 724                 }
 725         }
 726
 727         if (irq_src & UDC_RXN_CNT) {
 728                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 729                 ep->irqs++;
 730                 /* omap15xx does this unasked... */
 731                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 732                 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
 733         }
 734 }
 735
 736 static void dma_error(int lch, u16 ch_status, void *data)
 737 {
 738         struct omap_ep  *ep = data;
 739
 740         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 741         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 742         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 743
 744         /* complete current transfer ... */
 745 }
 746
 747 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 748 {
 749         u16     reg;
 750         int     status, restart, is_in;
 751         int     dma_channel;
 752
 753         is_in = ep->bEndpointAddress & USB_DIR_IN;
 754         if (is_in)
 755                 reg = omap_readw(UDC_TXDMA_CFG);
 756         else
 757                 reg = omap_readw(UDC_RXDMA_CFG);
 758         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 759
 760         ep->dma_channel = 0;
 761         ep->lch = -1;
 762         if (channel == 0 || channel > 3) {
 763                 if ((reg & 0x0f00) == 0)
 764                         channel = 3;
 765                 else if ((reg & 0x00f0) == 0)
 766                         channel = 2;
 767                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 768                         channel = 1;
 769                 else {
 770                         status = -EMLINK;
 771                         goto just_restart;
 772                 }
 773         }
 774         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 775         ep->dma_channel = channel;
 776
 777         if (is_in) {
 778                 if (cpu_is_omap24xx())
 779                         dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
 780                 else
 781                         dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
 782                 status = omap_request_dma(dma_channel,
 783                         ep->ep.name, dma_error, ep, &ep->lch);
 784                 if (status == 0) {
 785                         omap_writew(reg, UDC_TXDMA_CFG);
 786                         /* EMIFF or SDRC */
 787                         omap_set_dma_src_burst_mode(ep->lch,
 788                                                 OMAP_DMA_DATA_BURST_4);
 789                         omap_set_dma_src_data_pack(ep->lch, 1);
 790                         /* TIPB */
 791                         omap_set_dma_dest_params(ep->lch,
 792                                 OMAP_DMA_PORT_TIPB,
 793                                 OMAP_DMA_AMODE_CONSTANT,
 794                                 UDC_DATA_DMA,
 795                                 0, 0);
 796                 }
 797         } else {
 798                 if (cpu_is_omap24xx())
 799                         dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
 800                 else
 801                         dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
 802
 803                 status = omap_request_dma(dma_channel,
 804                         ep->ep.name, dma_error, ep, &ep->lch);
 805                 if (status == 0) {
 806                         omap_writew(reg, UDC_RXDMA_CFG);
 807                         /* TIPB */
 808                         omap_set_dma_src_params(ep->lch,
 809                                 OMAP_DMA_PORT_TIPB,
 810                                 OMAP_DMA_AMODE_CONSTANT,
 811                                 UDC_DATA_DMA,
 812                                 0, 0);
 813                         /* EMIFF or SDRC */
 814                         omap_set_dma_dest_burst_mode(ep->lch,
 815                                                 OMAP_DMA_DATA_BURST_4);
 816                         omap_set_dma_dest_data_pack(ep->lch, 1);
 817                 }
 818         }
 819         if (status)
 820                 ep->dma_channel = 0;
 821         else {
 822                 ep->has_dma = 1;
 823                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 824
 825                 /* channel type P: hw synch (fifo) */
 826                 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
 827                         omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
 828         }
 829
 830 just_restart:
 831         /* restart any queue, even if the claim failed  */
 832         restart = !ep->stopped && !list_empty(&ep->queue);
 833
 834         if (status)
 835                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 836                         restart ? " (restart)" : "");
 837         else
 838                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 839                         is_in ? 't' : 'r',
 840                         ep->dma_channel - 1, ep->lch,
 841                         restart ? " (restart)" : "");
 842
 843         if (restart) {
 844                 struct omap_req *req;
 845                 req = container_of(ep->queue.next, struct omap_req, queue);
 846                 if (ep->has_dma)
 847                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 848                 else {
 849                         use_ep(ep, UDC_EP_SEL);
 850                         (is_in ? write_fifo : read_fifo)(ep, req);
 851                         deselect_ep();
 852                         if (!is_in) {
 853                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 854                                 ep->ackwait = 1 + ep->double_buf;
 855                         }
 856                         /* IN: 6 wait states before it'll tx */
 857                 }
 858         }
 859 }
 860
 861 static void dma_channel_release(struct omap_ep *ep)
 862 {
 863         int             shift = 4 * (ep->dma_channel - 1);
 864         u16             mask = 0x0f << shift;
 865         struct omap_req *req;
 866         int             active;
 867
 868         /* abort any active usb transfer request */
 869         if (!list_empty(&ep->queue))
 870                 req = container_of(ep->queue.next, struct omap_req, queue);
 871         else
 872                 req = NULL;
 873
 874         active = omap_get_dma_active_status(ep->lch);
 875
 876         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 877                         active ? "active" : "idle",
 878                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 879                         ep->dma_channel - 1, req);
 880
 881         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 882          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 883          */
 884
 885         /* wait till current packet DMA finishes, and fifo empties */
 886         if (ep->bEndpointAddress & USB_DIR_IN) {
 887                 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 888                                         UDC_TXDMA_CFG);
 889
 890                 if (req) {
 891                         finish_in_dma(ep, req, -ECONNRESET);
 892
 893                         /* clear FIFO; hosts probably won't empty it */
 894                         use_ep(ep, UDC_EP_SEL);
 895                         omap_writew(UDC_CLR_EP, UDC_CTRL);
 896                         deselect_ep();
 897                 }
 898                 while (omap_readw(UDC_TXDMA_CFG) & mask)
 899                         udelay(10);
 900         } else {
 901                 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 902                                         UDC_RXDMA_CFG);
 903
 904                 /* dma empties the fifo */
 905                 while (omap_readw(UDC_RXDMA_CFG) & mask)
 906                         udelay(10);
 907                 if (req)
 908                         finish_out_dma(ep, req, -ECONNRESET, 0);
 909         }
 910         omap_free_dma(ep->lch);
 911         ep->dma_channel = 0;
 912         ep->lch = -1;
 913         /* has_dma still set, till endpoint is fully quiesced */
 914 }
 915
 916
 917 /*-------------------------------------------------------------------------*/
 918
 919 static int
 920 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 921 {
 922         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 923         struct omap_req *req = container_of(_req, struct omap_req, req);
 924         struct omap_udc *udc;
 925         unsigned long   flags;
 926         int             is_iso = 0;
 927
 928         /* catch various bogus parameters */
 929         if (!_req || !req->req.complete || !req->req.buf
 930                         || !list_empty(&req->queue)) {
 931                 DBG("%s, bad params\n", __func__);
 932                 return -EINVAL;
 933         }
 934         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
 935                 DBG("%s, bad ep\n", __func__);
 936                 return -EINVAL;
 937         }
 938         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 939                 if (req->req.length > ep->ep.maxpacket)
 940                         return -EMSGSIZE;
 941                 is_iso = 1;
 942         }
 943
 944         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 945          * have a hard time with partial packet reads...  reject it.
 946          * Except OMAP2 can handle the small packets.
 947          */
 948         if (use_dma
 949                         && ep->has_dma
 950                         && ep->bEndpointAddress != 0
 951                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 952                         && !cpu_class_is_omap2()
 953                         && (req->req.length % ep->ep.maxpacket) != 0) {
 954                 DBG("%s, no partial packet OUT reads\n", __func__);
 955                 return -EMSGSIZE;
 956         }
 957
 958         udc = ep->udc;
 959         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 960                 return -ESHUTDOWN;
 961
 962         if (use_dma && ep->has_dma) {
 963                 if (req->req.dma == DMA_ADDR_INVALID) {
 964                         req->req.dma = dma_map_single(
 965                                 ep->udc->gadget.dev.parent,
 966                                 req->req.buf,
 967                                 req->req.length,
 968                                 (ep->bEndpointAddress & USB_DIR_IN)
 969                                         ? DMA_TO_DEVICE
 970                                         : DMA_FROM_DEVICE);
 971                         req->mapped = 1;
 972                 } else {
 973                         dma_sync_single_for_device(
 974                                 ep->udc->gadget.dev.parent,
 975                                 req->req.dma, req->req.length,
 976                                 (ep->bEndpointAddress & USB_DIR_IN)
 977                                         ? DMA_TO_DEVICE
 978                                         : DMA_FROM_DEVICE);
 979                         req->mapped = 0;
 980                 }
 981         }
 982
 983         VDBG("%s queue req %p, len %d buf %p\n",
 984                 ep->ep.name, _req, _req->length, _req->buf);
 985
 986         spin_lock_irqsave(&udc->lock, flags);
 987
 988         req->req.status = -EINPROGRESS;
 989         req->req.actual = 0;
 990
 991         /* maybe kickstart non-iso i/o queues */
 992         if (is_iso) {
 993                 u16 w;
 994
 995                 w = omap_readw(UDC_IRQ_EN);
 996                 w |= UDC_SOF_IE;
 997                 omap_writew(w, UDC_IRQ_EN);
 998         } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
 999                 int     is_in;
1000
1001                 if (ep->bEndpointAddress == 0) {
1002                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1003                                 spin_unlock_irqrestore(&udc->lock, flags);
1004                                 return -EL2HLT;
1005                         }
1006
1007                         /* empty DATA stage? */
1008                         is_in = udc->ep0_in;
1009                         if (!req->req.length) {
1010
1011                                 /* chip became CONFIGURED or ADDRESSED
1012                                  * earlier; drivers may already have queued
1013                                  * requests to non-control endpoints
1014                                  */
1015                                 if (udc->ep0_set_config) {
1016                                         u16     irq_en = omap_readw(UDC_IRQ_EN);
1017
1018                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1019                                         if (!udc->ep0_reset_config)
1020                                                 irq_en |= UDC_EPN_RX_IE
1021                                                         | UDC_EPN_TX_IE;
1022                                         omap_writew(irq_en, UDC_IRQ_EN);
1023                                 }
1024
1025                                 /* STATUS for zero length DATA stages is
1026                                  * always an IN ... even for IN transfers,
1027                                  * a weird case which seem to stall OMAP.
1028                                  */
1029                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1030                                 omap_writew(UDC_CLR_EP, UDC_CTRL);
1031                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1032                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1033
1034                                 /* cleanup */
1035                                 udc->ep0_pending = 0;
1036                                 done(ep, req, 0);
1037                                 req = NULL;
1038
1039                         /* non-empty DATA stage */
1040                         } else if (is_in) {
1041                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1042                         } else {
1043                                 if (udc->ep0_setup)
1044                                         goto irq_wait;
1045                                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1046                         }
1047                 } else {
1048                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1049                         if (!ep->has_dma)
1050                                 use_ep(ep, UDC_EP_SEL);
1051                         /* if ISO: SOF IRQs must be enabled/disabled! */
1052                 }
1053
1054                 if (ep->has_dma)
1055                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1056                 else if (req) {
1057                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1058                                 req = NULL;
1059                         deselect_ep();
1060                         if (!is_in) {
1061                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1062                                 ep->ackwait = 1 + ep->double_buf;
1063                         }
1064                         /* IN: 6 wait states before it'll tx */
1065                 }
1066         }
1067
1068 irq_wait:
1069         /* irq handler advances the queue */
1070         if (req != NULL)
1071                 list_add_tail(&req->queue, &ep->queue);
1072         spin_unlock_irqrestore(&udc->lock, flags);
1073
1074         return 0;
1075 }
1076
1077 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1078 {
1079         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1080         struct omap_req *req;
1081         unsigned long   flags;
1082
1083         if (!_ep || !_req)
1084                 return -EINVAL;
1085
1086         spin_lock_irqsave(&ep->udc->lock, flags);
1087
1088         /* make sure it's actually queued on this endpoint */
1089         list_for_each_entry (req, &ep->queue, queue) {
1090                 if (&req->req == _req)
1091                         break;
1092         }
1093         if (&req->req != _req) {
1094                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1095                 return -EINVAL;
1096         }
1097
1098         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1099                 int channel = ep->dma_channel;
1100
1101                 /* releasing the channel cancels the request,
1102                  * reclaiming the channel restarts the queue
1103                  */
1104                 dma_channel_release(ep);
1105                 dma_channel_claim(ep, channel);
1106         } else
1107                 done(ep, req, -ECONNRESET);
1108         spin_unlock_irqrestore(&ep->udc->lock, flags);
1109         return 0;
1110 }
1111
1112 /*-------------------------------------------------------------------------*/
1113
1114 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1115 {
1116         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1117         unsigned long   flags;
1118         int             status = -EOPNOTSUPP;
1119
1120         spin_lock_irqsave(&ep->udc->lock, flags);
1121
1122         /* just use protocol stalls for ep0; real halts are annoying */
1123         if (ep->bEndpointAddress == 0) {
1124                 if (!ep->udc->ep0_pending)
1125                         status = -EINVAL;
1126                 else if (value) {
1127                         if (ep->udc->ep0_set_config) {
1128                                 WARNING("error changing config?\n");
1129                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1130                         }
1131                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1132                         ep->udc->ep0_pending = 0;
1133                         status = 0;
1134                 } else /* NOP */
1135                         status = 0;
1136
1137         /* otherwise, all active non-ISO endpoints can halt */
1138         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1139
1140                 /* IN endpoints must already be idle */
1141                 if ((ep->bEndpointAddress & USB_DIR_IN)
1142                                 && !list_empty(&ep->queue)) {
1143                         status = -EAGAIN;
1144                         goto done;
1145                 }
1146
1147                 if (value) {
1148                         int     channel;
1149
1150                         if (use_dma && ep->dma_channel
1151                                         && !list_empty(&ep->queue)) {
1152                                 channel = ep->dma_channel;
1153                                 dma_channel_release(ep);
1154                         } else
1155                                 channel = 0;
1156
1157                         use_ep(ep, UDC_EP_SEL);
1158                         if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1159                                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1160                                 status = 0;
1161                         } else
1162                                 status = -EAGAIN;
1163                         deselect_ep();
1164
1165                         if (channel)
1166                                 dma_channel_claim(ep, channel);
1167                 } else {
1168                         use_ep(ep, 0);
1169                         omap_writew(ep->udc->clr_halt, UDC_CTRL);
1170                         ep->ackwait = 0;
1171                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1172                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1173                                 ep->ackwait = 1 + ep->double_buf;
1174                         }
1175                 }
1176         }
1177 done:
1178         VDBG("%s %s halt stat %d\n", ep->ep.name,
1179                 value ? "set" : "clear", status);
1180
1181         spin_unlock_irqrestore(&ep->udc->lock, flags);
1182         return status;
1183 }
1184
1185 static struct usb_ep_ops omap_ep_ops = {
1186         .enable         = omap_ep_enable,
1187         .disable        = omap_ep_disable,
1188
1189         .alloc_request  = omap_alloc_request,
1190         .free_request   = omap_free_request,
1191
1192         .queue          = omap_ep_queue,
1193         .dequeue        = omap_ep_dequeue,
1194
1195         .set_halt       = omap_ep_set_halt,
1196         // fifo_status ... report bytes in fifo
1197         // fifo_flush ... flush fifo
1198 };
1199
1200 /*-------------------------------------------------------------------------*/
1201
1202 static int omap_get_frame(struct usb_gadget *gadget)
1203 {
1204         u16     sof = omap_readw(UDC_SOF);
1205         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1206 }
1207
1208 static int omap_wakeup(struct usb_gadget *gadget)
1209 {
1210         struct omap_udc *udc;
1211         unsigned long   flags;
1212         int             retval = -EHOSTUNREACH;
1213
1214         udc = container_of(gadget, struct omap_udc, gadget);
1215
1216         spin_lock_irqsave(&udc->lock, flags);
1217         if (udc->devstat & UDC_SUS) {
1218                 /* NOTE:  OTG spec erratum says that OTG devices may
1219                  * issue wakeups without host enable.
1220                  */
1221                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1222                         DBG("remote wakeup...\n");
1223                         omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1224                         retval = 0;
1225                 }
1226
1227         /* NOTE:  non-OTG systems may use SRP TOO... */
1228         } else if (!(udc->devstat & UDC_ATT)) {
1229                 if (udc->transceiver)
1230                         retval = otg_start_srp(udc->transceiver);
1231         }
1232         spin_unlock_irqrestore(&udc->lock, flags);
1233
1234         return retval;
1235 }
1236
1237 static int
1238 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1239 {
1240         struct omap_udc *udc;
1241         unsigned long   flags;
1242         u16             syscon1;
1243
1244         udc = container_of(gadget, struct omap_udc, gadget);
1245         spin_lock_irqsave(&udc->lock, flags);
1246         syscon1 = omap_readw(UDC_SYSCON1);
1247         if (is_selfpowered)
1248                 syscon1 |= UDC_SELF_PWR;
1249         else
1250                 syscon1 &= ~UDC_SELF_PWR;
1251         omap_writew(syscon1, UDC_SYSCON1);
1252         spin_unlock_irqrestore(&udc->lock, flags);
1253
1254         return 0;
1255 }
1256
1257 static int can_pullup(struct omap_udc *udc)
1258 {
1259         return udc->driver && udc->softconnect && udc->vbus_active;
1260 }
1261
1262 static void pullup_enable(struct omap_udc *udc)
1263 {
1264         u16 w;
1265
1266         w = omap_readw(UDC_SYSCON1);
1267         w |= UDC_PULLUP_EN;
1268         omap_writew(w, UDC_SYSCON1);
1269         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1270                 u32 l;
1271
1272                 l = omap_readl(OTG_CTRL);
1273                 l |= OTG_BSESSVLD;
1274                 omap_writel(l, OTG_CTRL);
1275         }
1276         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1277 }
1278
1279 static void pullup_disable(struct omap_udc *udc)
1280 {
1281         u16 w;
1282
1283         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1284                 u32 l;
1285
1286                 l = omap_readl(OTG_CTRL);
1287                 l &= ~OTG_BSESSVLD;
1288                 omap_writel(l, OTG_CTRL);
1289         }
1290         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1291         w = omap_readw(UDC_SYSCON1);
1292         w &= ~UDC_PULLUP_EN;
1293         omap_writew(w, UDC_SYSCON1);
1294 }
1295
1296 static struct omap_udc *udc;
1297
1298 static void omap_udc_enable_clock(int enable)
1299 {
1300         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1301                 return;
1302
1303         if (enable) {
1304                 clk_enable(udc->dc_clk);
1305                 clk_enable(udc->hhc_clk);
1306                 udelay(100);
1307         } else {
1308                 clk_disable(udc->hhc_clk);
1309                 clk_disable(udc->dc_clk);
1310         }
1311 }
1312
1313 /*
1314  * Called by whatever detects VBUS sessions:  external transceiver
1315  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1316  */
1317 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1318 {
1319         struct omap_udc *udc;
1320         unsigned long   flags;
1321         u32 l;
1322
1323         udc = container_of(gadget, struct omap_udc, gadget);
1324         spin_lock_irqsave(&udc->lock, flags);
1325         VDBG("VBUS %s\n", is_active ? "on" : "off");
1326         udc->vbus_active = (is_active != 0);
1327         if (cpu_is_omap15xx()) {
1328                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1329                 l = omap_readl(FUNC_MUX_CTRL_0);
1330                 if (is_active)
1331                         l |= VBUS_CTRL_1510;
1332                 else
1333                         l &= ~VBUS_CTRL_1510;
1334                 omap_writel(l, FUNC_MUX_CTRL_0);
1335         }
1336         if (udc->dc_clk != NULL && is_active) {
1337                 if (!udc->clk_requested) {
1338                         omap_udc_enable_clock(1);
1339                         udc->clk_requested = 1;
1340                 }
1341         }
1342         if (can_pullup(udc))
1343                 pullup_enable(udc);
1344         else
1345                 pullup_disable(udc);
1346         if (udc->dc_clk != NULL && !is_active) {
1347                 if (udc->clk_requested) {
1348                         omap_udc_enable_clock(0);
1349                         udc->clk_requested = 0;
1350                 }
1351         }
1352         spin_unlock_irqrestore(&udc->lock, flags);
1353         return 0;
1354 }
1355
1356 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1357 {
1358         struct omap_udc *udc;
1359
1360         udc = container_of(gadget, struct omap_udc, gadget);
1361         if (udc->transceiver)
1362                 return otg_set_power(udc->transceiver, mA);
1363         return -EOPNOTSUPP;
1364 }
1365
1366 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1367 {
1368         struct omap_udc *udc;
1369         unsigned long   flags;
1370
1371         udc = container_of(gadget, struct omap_udc, gadget);
1372         spin_lock_irqsave(&udc->lock, flags);
1373         udc->softconnect = (is_on != 0);
1374         if (can_pullup(udc))
1375                 pullup_enable(udc);
1376         else
1377                 pullup_disable(udc);
1378         spin_unlock_irqrestore(&udc->lock, flags);
1379         return 0;
1380 }
1381
1382 static struct usb_gadget_ops omap_gadget_ops = {
1383         .get_frame              = omap_get_frame,
1384         .wakeup                 = omap_wakeup,
1385         .set_selfpowered        = omap_set_selfpowered,
1386         .vbus_session           = omap_vbus_session,
1387         .vbus_draw              = omap_vbus_draw,
1388         .pullup                 = omap_pullup,
1389 };
1390
1391 /*-------------------------------------------------------------------------*/
1392
1393 /* dequeue ALL requests; caller holds udc->lock */
1394 static void nuke(struct omap_ep *ep, int status)
1395 {
1396         struct omap_req *req;
1397
1398         ep->stopped = 1;
1399
1400         if (use_dma && ep->dma_channel)
1401                 dma_channel_release(ep);
1402
1403         use_ep(ep, 0);
1404         omap_writew(UDC_CLR_EP, UDC_CTRL);
1405         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1406                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1407
1408         while (!list_empty(&ep->queue)) {
1409                 req = list_entry(ep->queue.next, struct omap_req, queue);
1410                 done(ep, req, status);
1411         }
1412 }
1413
1414 /* caller holds udc->lock */
1415 static void udc_quiesce(struct omap_udc *udc)
1416 {
1417         struct omap_ep  *ep;
1418
1419         udc->gadget.speed = USB_SPEED_UNKNOWN;
1420         nuke(&udc->ep[0], -ESHUTDOWN);
1421         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1422                 nuke(ep, -ESHUTDOWN);
1423 }
1424
1425 /*-------------------------------------------------------------------------*/
1426
1427 static void update_otg(struct omap_udc *udc)
1428 {
1429         u16     devstat;
1430
1431         if (!gadget_is_otg(&udc->gadget))
1432                 return;
1433
1434         if (omap_readl(OTG_CTRL) & OTG_ID)
1435                 devstat = omap_readw(UDC_DEVSTAT);
1436         else
1437                 devstat = 0;
1438
1439         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1440         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1441         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1442
1443         /* Enable HNP early, avoiding races on suspend irq path.
1444          * ASSUMES OTG state machine B_BUS_REQ input is true.
1445          */
1446         if (udc->gadget.b_hnp_enable) {
1447                 u32 l;
1448
1449                 l = omap_readl(OTG_CTRL);
1450                 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1451                 l &= ~OTG_PULLUP;
1452                 omap_writel(l, OTG_CTRL);
1453         }
1454 }
1455
1456 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1457 {
1458         struct omap_ep  *ep0 = &udc->ep[0];
1459         struct omap_req *req = NULL;
1460
1461         ep0->irqs++;
1462
1463         /* Clear any pending requests and then scrub any rx/tx state
1464          * before starting to handle the SETUP request.
1465          */
1466         if (irq_src & UDC_SETUP) {
1467                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1468
1469                 nuke(ep0, 0);
1470                 if (ack) {
1471                         omap_writew(ack, UDC_IRQ_SRC);
1472                         irq_src = UDC_SETUP;
1473                 }
1474         }
1475
1476         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1477          * This driver uses only uses protocol stalls (ep0 never halts),
1478          * and if we got this far the gadget driver already had a
1479          * chance to stall.  Tries to be forgiving of host oddities.
1480          *
1481          * NOTE:  the last chance gadget drivers have to stall control
1482          * requests is during their request completion callback.
1483          */
1484         if (!list_empty(&ep0->queue))
1485                 req = container_of(ep0->queue.next, struct omap_req, queue);
1486
1487         /* IN == TX to host */
1488         if (irq_src & UDC_EP0_TX) {
1489                 int     stat;
1490
1491                 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1492                 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1493                 stat = omap_readw(UDC_STAT_FLG);
1494                 if (stat & UDC_ACK) {
1495                         if (udc->ep0_in) {
1496                                 /* write next IN packet from response,
1497                                  * or set up the status stage.
1498                                  */
1499                                 if (req)
1500                                         stat = write_fifo(ep0, req);
1501                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1502                                 if (!req && udc->ep0_pending) {
1503                                         omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1504                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1505                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1506                                         omap_writew(0, UDC_EP_NUM);
1507                                         udc->ep0_pending = 0;
1508                                 } /* else:  6 wait states before it'll tx */
1509                         } else {
1510                                 /* ack status stage of OUT transfer */
1511                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1512                                 if (req)
1513                                         done(ep0, req, 0);
1514                         }
1515                         req = NULL;
1516                 } else if (stat & UDC_STALL) {
1517                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1518                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1519                 } else {
1520                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1521                 }
1522         }
1523
1524         /* OUT == RX from host */
1525         if (irq_src & UDC_EP0_RX) {
1526                 int     stat;
1527
1528                 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1529                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1530                 stat = omap_readw(UDC_STAT_FLG);
1531                 if (stat & UDC_ACK) {
1532                         if (!udc->ep0_in) {
1533                                 stat = 0;
1534                                 /* read next OUT packet of request, maybe
1535                                  * reactiviting the fifo; stall on errors.
1536                                  */
1537                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1538                                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1539                                         udc->ep0_pending = 0;
1540                                         stat = 0;
1541                                 } else if (stat == 0)
1542                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1543                                 omap_writew(0, UDC_EP_NUM);
1544
1545                                 /* activate status stage */
1546                                 if (stat == 1) {
1547                                         done(ep0, req, 0);
1548                                         /* that may have STALLed ep0... */
1549                                         omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1550                                                         UDC_EP_NUM);
1551                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1552                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1553                                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1554                                         udc->ep0_pending = 0;
1555                                 }
1556                         } else {
1557                                 /* ack status stage of IN transfer */
1558                                 omap_writew(0, UDC_EP_NUM);
1559                                 if (req)
1560                                         done(ep0, req, 0);
1561                         }
1562                 } else if (stat & UDC_STALL) {
1563                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1564                         omap_writew(0, UDC_EP_NUM);
1565                 } else {
1566                         omap_writew(0, UDC_EP_NUM);
1567                 }
1568         }
1569
1570         /* SETUP starts all control transfers */
1571         if (irq_src & UDC_SETUP) {
1572                 union u {
1573                         u16                     word[4];
1574                         struct usb_ctrlrequest  r;
1575                 } u;
1576                 int                     status = -EINVAL;
1577                 struct omap_ep          *ep;
1578
1579                 /* read the (latest) SETUP message */
1580                 do {
1581                         omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1582                         /* two bytes at a time */
1583                         u.word[0] = omap_readw(UDC_DATA);
1584                         u.word[1] = omap_readw(UDC_DATA);
1585                         u.word[2] = omap_readw(UDC_DATA);
1586                         u.word[3] = omap_readw(UDC_DATA);
1587                         omap_writew(0, UDC_EP_NUM);
1588                 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1589
1590 #define w_value         le16_to_cpu(u.r.wValue)
1591 #define w_index         le16_to_cpu(u.r.wIndex)
1592 #define w_length        le16_to_cpu(u.r.wLength)
1593
1594                 /* Delegate almost all control requests to the gadget driver,
1595                  * except for a handful of ch9 status/feature requests that
1596                  * hardware doesn't autodecode _and_ the gadget API hides.
1597                  */
1598                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1599                 udc->ep0_set_config = 0;
1600                 udc->ep0_pending = 1;
1601                 ep0->stopped = 0;
1602                 ep0->ackwait = 0;
1603                 switch (u.r.bRequest) {
1604                 case USB_REQ_SET_CONFIGURATION:
1605                         /* udc needs to know when ep != 0 is valid */
1606                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1607                                 goto delegate;
1608                         if (w_length != 0)
1609                                 goto do_stall;
1610                         udc->ep0_set_config = 1;
1611                         udc->ep0_reset_config = (w_value == 0);
1612                         VDBG("set config %d\n", w_value);
1613
1614                         /* update udc NOW since gadget driver may start
1615                          * queueing requests immediately; clear config
1616                          * later if it fails the request.
1617                          */
1618                         if (udc->ep0_reset_config)
1619                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1620                         else
1621                                 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1622                         update_otg(udc);
1623                         goto delegate;
1624                 case USB_REQ_CLEAR_FEATURE:
1625                         /* clear endpoint halt */
1626                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1627                                 goto delegate;
1628                         if (w_value != USB_ENDPOINT_HALT
1629                                         || w_length != 0)
1630                                 goto do_stall;
1631                         ep = &udc->ep[w_index & 0xf];
1632                         if (ep != ep0) {
1633                                 if (w_index & USB_DIR_IN)
1634                                         ep += 16;
1635                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1636                                                 || !ep->desc)
1637                                         goto do_stall;
1638                                 use_ep(ep, 0);
1639                                 omap_writew(udc->clr_halt, UDC_CTRL);
1640                                 ep->ackwait = 0;
1641                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1642                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1643                                         ep->ackwait = 1 + ep->double_buf;
1644                                 }
1645                                 /* NOTE:  assumes the host behaves sanely,
1646                                  * only clearing real halts.  Else we may
1647                                  * need to kill pending transfers and then
1648                                  * restart the queue... very messy for DMA!
1649                                  */
1650                         }
1651                         VDBG("%s halt cleared by host\n", ep->name);
1652                         goto ep0out_status_stage;
1653                 case USB_REQ_SET_FEATURE:
1654                         /* set endpoint halt */
1655                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1656                                 goto delegate;
1657                         if (w_value != USB_ENDPOINT_HALT
1658                                         || w_length != 0)
1659                                 goto do_stall;
1660                         ep = &udc->ep[w_index & 0xf];
1661                         if (w_index & USB_DIR_IN)
1662                                 ep += 16;
1663                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1664                                         || ep == ep0 || !ep->desc)
1665                                 goto do_stall;
1666                         if (use_dma && ep->has_dma) {
1667                                 /* this has rude side-effects (aborts) and
1668                                  * can't really work if DMA-IN is active
1669                                  */
1670                                 DBG("%s host set_halt, NYET \n", ep->name);
1671                                 goto do_stall;
1672                         }
1673                         use_ep(ep, 0);
1674                         /* can't halt if fifo isn't empty... */
1675                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1676                         omap_writew(UDC_SET_HALT, UDC_CTRL);
1677                         VDBG("%s halted by host\n", ep->name);
1678 ep0out_status_stage:
1679                         status = 0;
1680                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1681                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1682                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1683                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1684                         udc->ep0_pending = 0;
1685                         break;
1686                 case USB_REQ_GET_STATUS:
1687                         /* USB_ENDPOINT_HALT status? */
1688                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1689                                 goto intf_status;
1690
1691                         /* ep0 never stalls */
1692                         if (!(w_index & 0xf))
1693                                 goto zero_status;
1694
1695                         /* only active endpoints count */
1696                         ep = &udc->ep[w_index & 0xf];
1697                         if (w_index & USB_DIR_IN)
1698                                 ep += 16;
1699                         if (!ep->desc)
1700                                 goto do_stall;
1701
1702                         /* iso never stalls */
1703                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1704                                 goto zero_status;
1705
1706                         /* FIXME don't assume non-halted endpoints!! */
1707                         ERR("%s status, can't report\n", ep->ep.name);
1708                         goto do_stall;
1709
1710 intf_status:
1711                         /* return interface status.  if we were pedantic,
1712                          * we'd detect non-existent interfaces, and stall.
1713                          */
1714                         if (u.r.bRequestType
1715                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1716                                 goto delegate;
1717
1718 zero_status:
1719                         /* return two zero bytes */
1720                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1721                         omap_writew(0, UDC_DATA);
1722                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1723                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1724                         status = 0;
1725                         VDBG("GET_STATUS, interface %d\n", w_index);
1726                         /* next, status stage */
1727                         break;
1728                 default:
1729 delegate:
1730                         /* activate the ep0out fifo right away */
1731                         if (!udc->ep0_in && w_length) {
1732                                 omap_writew(0, UDC_EP_NUM);
1733                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1734                         }
1735
1736                         /* gadget drivers see class/vendor specific requests,
1737                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1738                          * and more
1739                          */
1740                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1741                                 u.r.bRequestType, u.r.bRequest,
1742                                 w_value, w_index, w_length);
1743
1744 #undef  w_value
1745 #undef  w_index
1746 #undef  w_length
1747
1748                         /* The gadget driver may return an error here,
1749                          * causing an immediate protocol stall.
1750                          *
1751                          * Else it must issue a response, either queueing a
1752                          * response buffer for the DATA stage, or halting ep0
1753                          * (causing a protocol stall, not a real halt).  A
1754                          * zero length buffer means no DATA stage.
1755                          *
1756                          * It's fine to issue that response after the setup()
1757                          * call returns, and this IRQ was handled.
1758                          */
1759                         udc->ep0_setup = 1;
1760                         spin_unlock(&udc->lock);
1761                         status = udc->driver->setup (&udc->gadget, &u.r);
1762                         spin_lock(&udc->lock);
1763                         udc->ep0_setup = 0;
1764                 }
1765
1766                 if (status < 0) {
1767 do_stall:
1768                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1769                                         u.r.bRequestType, u.r.bRequest, status);
1770                         if (udc->ep0_set_config) {
1771                                 if (udc->ep0_reset_config)
1772                                         WARNING("error resetting config?\n");
1773                                 else
1774                                         omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1775                         }
1776                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1777                         udc->ep0_pending = 0;
1778                 }
1779         }
1780 }
1781
1782 /*-------------------------------------------------------------------------*/
1783
1784 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1785
1786 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1787 {
1788         u16     devstat, change;
1789
1790         devstat = omap_readw(UDC_DEVSTAT);
1791         change = devstat ^ udc->devstat;
1792         udc->devstat = devstat;
1793
1794         if (change & (UDC_USB_RESET|UDC_ATT)) {
1795                 udc_quiesce(udc);
1796
1797                 if (change & UDC_ATT) {
1798                         /* driver for any external transceiver will
1799                          * have called omap_vbus_session() already
1800                          */
1801                         if (devstat & UDC_ATT) {
1802                                 udc->gadget.speed = USB_SPEED_FULL;
1803                                 VDBG("connect\n");
1804                                 if (!udc->transceiver)
1805                                         pullup_enable(udc);
1806                                 // if (driver->connect) call it
1807                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1808                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1809                                 if (!udc->transceiver)
1810                                         pullup_disable(udc);
1811                                 DBG("disconnect, gadget %s\n",
1812                                         udc->driver->driver.name);
1813                                 if (udc->driver->disconnect) {
1814                                         spin_unlock(&udc->lock);
1815                                         udc->driver->disconnect(&udc->gadget);
1816                                         spin_lock(&udc->lock);
1817                                 }
1818                         }
1819                         change &= ~UDC_ATT;
1820                 }
1821
1822                 if (change & UDC_USB_RESET) {
1823                         if (devstat & UDC_USB_RESET) {
1824                                 VDBG("RESET=1\n");
1825                         } else {
1826                                 udc->gadget.speed = USB_SPEED_FULL;
1827                                 INFO("USB reset done, gadget %s\n",
1828                                         udc->driver->driver.name);
1829                                 /* ep0 traffic is legal from now on */
1830                                 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1831                                                 UDC_IRQ_EN);
1832                         }
1833                         change &= ~UDC_USB_RESET;
1834                 }
1835         }
1836         if (change & UDC_SUS) {
1837                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1838                         // FIXME tell isp1301 to suspend/resume (?)
1839                         if (devstat & UDC_SUS) {
1840                                 VDBG("suspend\n");
1841                                 update_otg(udc);
1842                                 /* HNP could be under way already */
1843                                 if (udc->gadget.speed == USB_SPEED_FULL
1844                                                 && udc->driver->suspend) {
1845                                         spin_unlock(&udc->lock);
1846                                         udc->driver->suspend(&udc->gadget);
1847                                         spin_lock(&udc->lock);
1848                                 }
1849                                 if (udc->transceiver)
1850                                         otg_set_suspend(udc->transceiver, 1);
1851                         } else {
1852                                 VDBG("resume\n");
1853                                 if (udc->transceiver)
1854                                         otg_set_suspend(udc->transceiver, 0);
1855                                 if (udc->gadget.speed == USB_SPEED_FULL
1856                                                 && udc->driver->resume) {
1857                                         spin_unlock(&udc->lock);
1858                                         udc->driver->resume(&udc->gadget);
1859                                         spin_lock(&udc->lock);
1860                                 }
1861                         }
1862                 }
1863                 change &= ~UDC_SUS;
1864         }
1865         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1866                 update_otg(udc);
1867                 change &= ~OTG_FLAGS;
1868         }
1869
1870         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1871         if (change)
1872                 VDBG("devstat %03x, ignore change %03x\n",
1873                         devstat,  change);
1874
1875         omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1876 }
1877
1878 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1879 {
1880         struct omap_udc *udc = _udc;
1881         u16             irq_src;
1882         irqreturn_t     status = IRQ_NONE;
1883         unsigned long   flags;
1884
1885         spin_lock_irqsave(&udc->lock, flags);
1886         irq_src = omap_readw(UDC_IRQ_SRC);
1887
1888         /* Device state change (usb ch9 stuff) */
1889         if (irq_src & UDC_DS_CHG) {
1890                 devstate_irq(_udc, irq_src);
1891                 status = IRQ_HANDLED;
1892                 irq_src &= ~UDC_DS_CHG;
1893         }
1894
1895         /* EP0 control transfers */
1896         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1897                 ep0_irq(_udc, irq_src);
1898                 status = IRQ_HANDLED;
1899                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1900         }
1901
1902         /* DMA transfer completion */
1903         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1904                 dma_irq(_udc, irq_src);
1905                 status = IRQ_HANDLED;
1906                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1907         }
1908
1909         irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1910         if (irq_src)
1911                 DBG("udc_irq, unhandled %03x\n", irq_src);
1912         spin_unlock_irqrestore(&udc->lock, flags);
1913
1914         return status;
1915 }
1916
1917 /* workaround for seemingly-lost IRQs for RX ACKs... */
1918 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1919 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1920
1921 static void pio_out_timer(unsigned long _ep)
1922 {
1923         struct omap_ep  *ep = (void *) _ep;
1924         unsigned long   flags;
1925         u16             stat_flg;
1926
1927         spin_lock_irqsave(&ep->udc->lock, flags);
1928         if (!list_empty(&ep->queue) && ep->ackwait) {
1929                 use_ep(ep, UDC_EP_SEL);
1930                 stat_flg = omap_readw(UDC_STAT_FLG);
1931
1932                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1933                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1934                         struct omap_req *req;
1935
1936                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1937                         req = container_of(ep->queue.next,
1938                                         struct omap_req, queue);
1939                         (void) read_fifo(ep, req);
1940                         omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1941                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1942                         ep->ackwait = 1 + ep->double_buf;
1943                 } else
1944                         deselect_ep();
1945         }
1946         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1947         spin_unlock_irqrestore(&ep->udc->lock, flags);
1948 }
1949
1950 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1951 {
1952         u16             epn_stat, irq_src;
1953         irqreturn_t     status = IRQ_NONE;
1954         struct omap_ep  *ep;
1955         int             epnum;
1956         struct omap_udc *udc = _dev;
1957         struct omap_req *req;
1958         unsigned long   flags;
1959
1960         spin_lock_irqsave(&udc->lock, flags);
1961         epn_stat = omap_readw(UDC_EPN_STAT);
1962         irq_src = omap_readw(UDC_IRQ_SRC);
1963
1964         /* handle OUT first, to avoid some wasteful NAKs */
1965         if (irq_src & UDC_EPN_RX) {
1966                 epnum = (epn_stat >> 8) & 0x0f;
1967                 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1968                 status = IRQ_HANDLED;
1969                 ep = &udc->ep[epnum];
1970                 ep->irqs++;
1971
1972                 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1973                 ep->fnf = 0;
1974                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1975                         ep->ackwait--;
1976                         if (!list_empty(&ep->queue)) {
1977                                 int stat;
1978                                 req = container_of(ep->queue.next,
1979                                                 struct omap_req, queue);
1980                                 stat = read_fifo(ep, req);
1981                                 if (!ep->double_buf)
1982                                         ep->fnf = 1;
1983                         }
1984                 }
1985                 /* min 6 clock delay before clearing EP_SEL ... */
1986                 epn_stat = omap_readw(UDC_EPN_STAT);
1987                 epn_stat = omap_readw(UDC_EPN_STAT);
1988                 omap_writew(epnum, UDC_EP_NUM);
1989
1990                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1991                  * reduces lossage; timer still needed though (sigh).
1992                  */
1993                 if (ep->fnf) {
1994                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1995                         ep->ackwait = 1 + ep->double_buf;
1996                 }
1997                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1998         }
1999
2000         /* then IN transfers */
2001         else if (irq_src & UDC_EPN_TX) {
2002                 epnum = epn_stat & 0x0f;
2003                 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
2004                 status = IRQ_HANDLED;
2005                 ep = &udc->ep[16 + epnum];
2006                 ep->irqs++;
2007
2008                 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
2009                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
2010                         ep->ackwait = 0;
2011                         if (!list_empty(&ep->queue)) {
2012                                 req = container_of(ep->queue.next,
2013                                                 struct omap_req, queue);
2014                                 (void) write_fifo(ep, req);
2015                         }
2016                 }
2017                 /* min 6 clock delay before clearing EP_SEL ... */
2018                 epn_stat = omap_readw(UDC_EPN_STAT);
2019                 epn_stat = omap_readw(UDC_EPN_STAT);
2020                 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
2021                 /* then 6 clocks before it'd tx */
2022         }
2023
2024         spin_unlock_irqrestore(&udc->lock, flags);
2025         return status;
2026 }
2027
2028 #ifdef  USE_ISO
2029 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2030 {
2031         struct omap_udc *udc = _dev;
2032         struct omap_ep  *ep;
2033         int             pending = 0;
2034         unsigned long   flags;
2035
2036         spin_lock_irqsave(&udc->lock, flags);
2037
2038         /* handle all non-DMA ISO transfers */
2039         list_for_each_entry (ep, &udc->iso, iso) {
2040                 u16             stat;
2041                 struct omap_req *req;
2042
2043                 if (ep->has_dma || list_empty(&ep->queue))
2044                         continue;
2045                 req = list_entry(ep->queue.next, struct omap_req, queue);
2046
2047                 use_ep(ep, UDC_EP_SEL);
2048                 stat = omap_readw(UDC_STAT_FLG);
2049
2050                 /* NOTE: like the other controller drivers, this isn't
2051                  * currently reporting lost or damaged frames.
2052                  */
2053                 if (ep->bEndpointAddress & USB_DIR_IN) {
2054                         if (stat & UDC_MISS_IN)
2055                                 /* done(ep, req, -EPROTO) */;
2056                         else
2057                                 write_fifo(ep, req);
2058                 } else {
2059                         int     status = 0;
2060
2061                         if (stat & UDC_NO_RXPACKET)
2062                                 status = -EREMOTEIO;
2063                         else if (stat & UDC_ISO_ERR)
2064                                 status = -EILSEQ;
2065                         else if (stat & UDC_DATA_FLUSH)
2066                                 status = -ENOSR;
2067
2068                         if (status)
2069                                 /* done(ep, req, status) */;
2070                         else
2071                                 read_fifo(ep, req);
2072                 }
2073                 deselect_ep();
2074                 /* 6 wait states before next EP */
2075
2076                 ep->irqs++;
2077                 if (!list_empty(&ep->queue))
2078                         pending = 1;
2079         }
2080         if (!pending) {
2081                 u16 w;
2082
2083                 w = omap_readw(UDC_IRQ_EN);
2084                 w &= ~UDC_SOF_IE;
2085                 omap_writew(w, UDC_IRQ_EN);
2086         }
2087         omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2088
2089         spin_unlock_irqrestore(&udc->lock, flags);
2090         return IRQ_HANDLED;
2091 }
2092 #endif
2093
2094 /*-------------------------------------------------------------------------*/
2095
2096 static inline int machine_without_vbus_sense(void)
2097 {
2098         return (machine_is_omap_innovator()
2099                 || machine_is_omap_osk()
2100                 || machine_is_omap_apollon()
2101 #ifndef CONFIG_MACH_OMAP_H4_OTG
2102                 || machine_is_omap_h4()
2103 #endif
2104                 || machine_is_sx1()
2105                 || machine_is_omap_h6300()
2106                 );
2107 }
2108
2109 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2110 {
2111         int             status = -ENODEV;
2112         struct omap_ep  *ep;
2113         unsigned long   flags;
2114
2115         /* basic sanity tests */
2116         if (!udc)
2117                 return -ENODEV;
2118         if (!driver
2119                         // FIXME if otg, check:  driver->is_otg
2120                         || driver->speed < USB_SPEED_FULL
2121                         || !driver->bind
2122                         || !driver->setup)
2123                 return -EINVAL;
2124
2125         spin_lock_irqsave(&udc->lock, flags);
2126         if (udc->driver) {
2127                 spin_unlock_irqrestore(&udc->lock, flags);
2128                 return -EBUSY;
2129         }
2130
2131         /* reset state */
2132         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2133                 ep->irqs = 0;
2134                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2135                         continue;
2136                 use_ep(ep, 0);
2137                 omap_writew(UDC_SET_HALT, UDC_CTRL);
2138         }
2139         udc->ep0_pending = 0;
2140         udc->ep[0].irqs = 0;
2141         udc->softconnect = 1;
2142
2143         /* hook up the driver */
2144         driver->driver.bus = NULL;
2145         udc->driver = driver;
2146         udc->gadget.dev.driver = &driver->driver;
2147         spin_unlock_irqrestore(&udc->lock, flags);
2148
2149         if (udc->dc_clk != NULL)
2150                 omap_udc_enable_clock(1);
2151
2152         status = driver->bind (&udc->gadget);
2153         if (status) {
2154                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2155                 udc->gadget.dev.driver = NULL;
2156                 udc->driver = NULL;
2157                 goto done;
2158         }
2159         DBG("bound to driver %s\n", driver->driver.name);
2160
2161         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2162
2163         /* connect to bus through transceiver */
2164         if (udc->transceiver) {
2165                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2166                 if (status < 0) {
2167                         ERR("can't bind to transceiver\n");
2168                         if (driver->unbind) {
2169                                 driver->unbind (&udc->gadget);
2170                                 udc->gadget.dev.driver = NULL;
2171                                 udc->driver = NULL;
2172                         }
2173                         goto done;
2174                 }
2175         } else {
2176                 if (can_pullup(udc))
2177                         pullup_enable (udc);
2178                 else
2179                         pullup_disable (udc);
2180         }
2181
2182         /* boards that don't have VBUS sensing can't autogate 48MHz;
2183          * can't enter deep sleep while a gadget driver is active.
2184          */
2185         if (machine_without_vbus_sense())
2186                 omap_vbus_session(&udc->gadget, 1);
2187
2188 done:
2189         if (udc->dc_clk != NULL)
2190                 omap_udc_enable_clock(0);
2191         return status;
2192 }
2193 EXPORT_SYMBOL(usb_gadget_register_driver);
2194
2195 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2196 {
2197         unsigned long   flags;
2198         int             status = -ENODEV;
2199
2200         if (!udc)
2201                 return -ENODEV;
2202         if (!driver || driver != udc->driver || !driver->unbind)
2203                 return -EINVAL;
2204
2205         if (udc->dc_clk != NULL)
2206                 omap_udc_enable_clock(1);
2207
2208         if (machine_without_vbus_sense())
2209                 omap_vbus_session(&udc->gadget, 0);
2210
2211         if (udc->transceiver)
2212                 (void) otg_set_peripheral(udc->transceiver, NULL);
2213         else
2214                 pullup_disable(udc);
2215
2216         spin_lock_irqsave(&udc->lock, flags);
2217         udc_quiesce(udc);
2218         spin_unlock_irqrestore(&udc->lock, flags);
2219
2220         driver->unbind(&udc->gadget);
2221         udc->gadget.dev.driver = NULL;
2222         udc->driver = NULL;
2223
2224         if (udc->dc_clk != NULL)
2225                 omap_udc_enable_clock(0);
2226         DBG("unregistered driver '%s'\n", driver->driver.name);
2227         return status;
2228 }
2229 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2230
2231
2232 /*-------------------------------------------------------------------------*/
2233
2234 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2235
2236 #include <linux/seq_file.h>
2237
2238 static const char proc_filename[] = "driver/udc";
2239
2240 #define FOURBITS "%s%s%s%s"
2241 #define EIGHTBITS FOURBITS FOURBITS
2242
2243 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2244 {
2245         u16             stat_flg;
2246         struct omap_req *req;
2247         char            buf[20];
2248
2249         use_ep(ep, 0);
2250
2251         if (use_dma && ep->has_dma)
2252                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2253                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2254                         ep->dma_channel - 1, ep->lch);
2255         else
2256                 buf[0] = 0;
2257
2258         stat_flg = omap_readw(UDC_STAT_FLG);
2259         seq_printf(s,
2260                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2261                 ep->name, buf,
2262                 ep->double_buf ? "dbuf " : "",
2263                 ({char *s; switch(ep->ackwait){
2264                 case 0: s = ""; break;
2265                 case 1: s = "(ackw) "; break;
2266                 case 2: s = "(ackw2) "; break;
2267                 default: s = "(?) "; break;
2268                 } s;}),
2269                 ep->irqs, stat_flg,
2270                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2271                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2272                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2273                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2274                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2275                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2276                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2277                 (stat_flg & UDC_STALL) ? "STALL " : "",
2278                 (stat_flg & UDC_NAK) ? "NAK " : "",
2279                 (stat_flg & UDC_ACK) ? "ACK " : "",
2280                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2281                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2282                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2283
2284         if (list_empty (&ep->queue))
2285                 seq_printf(s, "\t(queue empty)\n");
2286         else
2287                 list_for_each_entry (req, &ep->queue, queue) {
2288                         unsigned        length = req->req.actual;
2289
2290                         if (use_dma && buf[0]) {
2291                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2292                                                 ? dma_src_len : dma_dest_len)
2293                                         (ep, req->req.dma + length);
2294                                 buf[0] = 0;
2295                         }
2296                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2297                                         &req->req, length,
2298                                         req->req.length, req->req.buf);
2299                 }
2300 }
2301
2302 static char *trx_mode(unsigned m, int enabled)
2303 {
2304         switch (m) {
2305         case 0:         return enabled ? "*6wire" : "unused";
2306         case 1:         return "4wire";
2307         case 2:         return "3wire";
2308         case 3:         return "6wire";
2309         default:        return "unknown";
2310         }
2311 }
2312
2313 static int proc_otg_show(struct seq_file *s)
2314 {
2315         u32             tmp;
2316         u32             trans;
2317         char            *ctrl_name;
2318
2319         tmp = omap_readl(OTG_REV);
2320         if (cpu_is_omap24xx()) {
2321                 /*
2322                  * REVISIT: Not clear how this works on OMAP2.  trans
2323                  * is ANDed to produce bits 7 and 8, which might make
2324                  * sense for USB_TRANSCEIVER_CTRL on OMAP1,
2325                  * but with CONTROL_DEVCONF, these bits have something to
2326                  * do with the frame adjustment counter and McBSP2.
2327                  */
2328                 ctrl_name = "control_devconf";
2329                 trans = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
2330         } else {
2331                 ctrl_name = "tranceiver_ctrl";
2332                 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2333         }
2334         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2335                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2336         tmp = omap_readw(OTG_SYSCON_1);
2337         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2338                         FOURBITS "\n", tmp,
2339                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2340                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2341                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2342                         ? "internal"
2343                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2344                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2345                 (tmp & HST_IDLE_EN) ? " !host" : "",
2346                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2347                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2348         tmp = omap_readl(OTG_SYSCON_2);
2349         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2350                         " b_ase_brst=%d hmc=%d\n", tmp,
2351                 (tmp & OTG_EN) ? " otg_en" : "",
2352                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2353                 // much more SRP stuff
2354                 (tmp & SRP_DATA) ? " srp_data" : "",
2355                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2356                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2357                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2358                 (tmp & UHOST_EN) ? " uhost_en" : "",
2359                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2360                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2361                 B_ASE_BRST(tmp),
2362                 OTG_HMC(tmp));
2363         tmp = omap_readl(OTG_CTRL);
2364         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2365                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2366                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2367                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2368                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2369                 (tmp & OTG_ID) ? " id" : "",
2370                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2371                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2372                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2373                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2374                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2375                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2376                 (tmp & OTG_PULLDOWN) ? " down" : "",
2377                 (tmp & OTG_PULLUP) ? " up" : "",
2378                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2379                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2380                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2381                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2382                 );
2383         tmp = omap_readw(OTG_IRQ_EN);
2384         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2385         tmp = omap_readw(OTG_IRQ_SRC);
2386         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2387         tmp = omap_readw(OTG_OUTCTRL);
2388         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2389         tmp = omap_readw(OTG_TEST);
2390         seq_printf(s, "otg_test    %04x" "\n", tmp);
2391         return 0;
2392 }
2393
2394 static int proc_udc_show(struct seq_file *s, void *_)
2395 {
2396         u32             tmp;
2397         struct omap_ep  *ep;
2398         unsigned long   flags;
2399
2400         spin_lock_irqsave(&udc->lock, flags);
2401
2402         seq_printf(s, "%s, version: " DRIVER_VERSION
2403 #ifdef  USE_ISO
2404                 " (iso)"
2405 #endif
2406                 "%s\n",
2407                 driver_desc,
2408                 use_dma ?  " (dma)" : "");
2409
2410         tmp = omap_readw(UDC_REV) & 0xff;
2411         seq_printf(s,
2412                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2413                 "hmc %d, transceiver %s\n",
2414                 tmp >> 4, tmp & 0xf,
2415                 fifo_mode,
2416                 udc->driver ? udc->driver->driver.name : "(none)",
2417                 HMC,
2418                 udc->transceiver
2419                         ? udc->transceiver->label
2420                         : ((cpu_is_omap1710() || cpu_is_omap24xx())
2421                                 ? "external" : "(none)"));
2422         if (cpu_class_is_omap1()) {
2423                 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2424                         omap_readw(ULPD_CLOCK_CTRL),
2425                         omap_readw(ULPD_SOFT_REQ),
2426                         omap_readw(ULPD_STATUS_REQ));
2427         }
2428
2429         /* OTG controller registers */
2430         if (!cpu_is_omap15xx())
2431                 proc_otg_show(s);
2432
2433         tmp = omap_readw(UDC_SYSCON1);
2434         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2435                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2436                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2437                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2438                 (tmp & UDC_NAK_EN) ? " nak" : "",
2439                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2440                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2441                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2442                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2443         // syscon2 is write-only
2444
2445         /* UDC controller registers */
2446         if (!(tmp & UDC_PULLUP_EN)) {
2447                 seq_printf(s, "(suspended)\n");
2448                 spin_unlock_irqrestore(&udc->lock, flags);
2449                 return 0;
2450         }
2451
2452         tmp = omap_readw(UDC_DEVSTAT);
2453         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2454                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2455                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2456                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2457                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2458                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2459                 (tmp & UDC_SUS) ? " SUS" : "",
2460                 (tmp & UDC_CFG) ? " CFG" : "",
2461                 (tmp & UDC_ADD) ? " ADD" : "",
2462                 (tmp & UDC_DEF) ? " DEF" : "",
2463                 (tmp & UDC_ATT) ? " ATT" : "");
2464         seq_printf(s, "sof         %04x\n", omap_readw(UDC_SOF));
2465         tmp = omap_readw(UDC_IRQ_EN);
2466         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2467                 (tmp & UDC_SOF_IE) ? " sof" : "",
2468                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2469                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2470                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2471                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2472         tmp = omap_readw(UDC_IRQ_SRC);
2473         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2474                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2475                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2476                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2477                 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2478                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2479                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2480                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2481                 (tmp & UDC_SETUP) ? " setup" : "",
2482                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2483                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2484         if (use_dma) {
2485                 unsigned i;
2486
2487                 tmp = omap_readw(UDC_DMA_IRQ_EN);
2488                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2489                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2490                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2491                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2492
2493                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2494                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2495                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2496
2497                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2498                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2499                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2500
2501                 tmp = omap_readw(UDC_RXDMA_CFG);
2502                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2503                 if (tmp) {
2504                         for (i = 0; i < 3; i++) {
2505                                 if ((tmp & (0x0f << (i * 4))) == 0)
2506                                         continue;
2507                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2508                                                 omap_readw(UDC_RXDMA(i + 1)));
2509                         }
2510                 }
2511                 tmp = omap_readw(UDC_TXDMA_CFG);
2512                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2513                 if (tmp) {
2514                         for (i = 0; i < 3; i++) {
2515                                 if (!(tmp & (0x0f << (i * 4))))
2516                                         continue;
2517                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2518                                                 omap_readw(UDC_TXDMA(i + 1)));
2519                         }
2520                 }
2521         }
2522
2523         tmp = omap_readw(UDC_DEVSTAT);
2524         if (tmp & UDC_ATT) {
2525                 proc_ep_show(s, &udc->ep[0]);
2526                 if (tmp & UDC_ADD) {
2527                         list_for_each_entry (ep, &udc->gadget.ep_list,
2528                                         ep.ep_list) {
2529                                 if (ep->desc)
2530                                         proc_ep_show(s, ep);
2531                         }
2532                 }
2533         }
2534         spin_unlock_irqrestore(&udc->lock, flags);
2535         return 0;
2536 }
2537
2538 static int proc_udc_open(struct inode *inode, struct file *file)
2539 {
2540         return single_open(file, proc_udc_show, NULL);
2541 }
2542
2543 static const struct file_operations proc_ops = {
2544         .owner          = THIS_MODULE,
2545         .open           = proc_udc_open,
2546         .read           = seq_read,
2547         .llseek         = seq_lseek,
2548         .release        = single_release,
2549 };
2550
2551 static void create_proc_file(void)
2552 {
2553         proc_create(proc_filename, 0, NULL, &proc_ops);
2554 }
2555
2556 static void remove_proc_file(void)
2557 {
2558         remove_proc_entry(proc_filename, NULL);
2559 }
2560
2561 #else
2562
2563 static inline void create_proc_file(void) {}
2564 static inline void remove_proc_file(void) {}
2565
2566 #endif
2567
2568 /*-------------------------------------------------------------------------*/
2569
2570 /* Before this controller can enumerate, we need to pick an endpoint
2571  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2572  * buffer space among the endpoints we'll be operating.
2573  *
2574  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2575  * UDC_SYSCON_1.CFG_LOCK is set can now work.  We won't use that
2576  * capability yet though.
2577  */
2578 static unsigned __init
2579 omap_ep_setup(char *name, u8 addr, u8 type,
2580                 unsigned buf, unsigned maxp, int dbuf)
2581 {
2582         struct omap_ep  *ep;
2583         u16             epn_rxtx = 0;
2584
2585         /* OUT endpoints first, then IN */
2586         ep = &udc->ep[addr & 0xf];
2587         if (addr & USB_DIR_IN)
2588                 ep += 16;
2589
2590         /* in case of ep init table bugs */
2591         BUG_ON(ep->name[0]);
2592
2593         /* chip setup ... bit values are same for IN, OUT */
2594         if (type == USB_ENDPOINT_XFER_ISOC) {
2595                 switch (maxp) {
2596                 case 8:         epn_rxtx = 0 << 12; break;
2597                 case 16:        epn_rxtx = 1 << 12; break;
2598                 case 32:        epn_rxtx = 2 << 12; break;
2599                 case 64:        epn_rxtx = 3 << 12; break;
2600                 case 128:       epn_rxtx = 4 << 12; break;
2601                 case 256:       epn_rxtx = 5 << 12; break;
2602                 case 512:       epn_rxtx = 6 << 12; break;
2603                 default:        BUG();
2604                 }
2605                 epn_rxtx |= UDC_EPN_RX_ISO;
2606                 dbuf = 1;
2607         } else {
2608                 /* double-buffering "not supported" on 15xx,
2609                  * and ignored for PIO-IN on newer chips
2610                  * (for more reliable behavior)
2611                  */
2612                 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2613                         dbuf = 0;
2614
2615                 switch (maxp) {
2616                 case 8:         epn_rxtx = 0 << 12; break;
2617                 case 16:        epn_rxtx = 1 << 12; break;
2618                 case 32:        epn_rxtx = 2 << 12; break;
2619                 case 64:        epn_rxtx = 3 << 12; break;
2620                 default:        BUG();
2621                 }
2622                 if (dbuf && addr)
2623                         epn_rxtx |= UDC_EPN_RX_DB;
2624                 init_timer(&ep->timer);
2625                 ep->timer.function = pio_out_timer;
2626                 ep->timer.data = (unsigned long) ep;
2627         }
2628         if (addr)
2629                 epn_rxtx |= UDC_EPN_RX_VALID;
2630         BUG_ON(buf & 0x07);
2631         epn_rxtx |= buf >> 3;
2632
2633         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2634                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2635
2636         if (addr & USB_DIR_IN)
2637                 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2638         else
2639                 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2640
2641         /* next endpoint's buffer starts after this one's */
2642         buf += maxp;
2643         if (dbuf)
2644                 buf += maxp;
2645         BUG_ON(buf > 2048);
2646
2647         /* set up driver data structures */
2648         BUG_ON(strlen(name) >= sizeof ep->name);
2649         strlcpy(ep->name, name, sizeof ep->name);
2650         INIT_LIST_HEAD(&ep->queue);
2651         INIT_LIST_HEAD(&ep->iso);
2652         ep->bEndpointAddress = addr;
2653         ep->bmAttributes = type;
2654         ep->double_buf = dbuf;
2655         ep->udc = udc;
2656
2657         ep->ep.name = ep->name;
2658         ep->ep.ops = &omap_ep_ops;
2659         ep->ep.maxpacket = ep->maxpacket = maxp;
2660         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2661
2662         return buf;
2663 }
2664
2665 static void omap_udc_release(struct device *dev)
2666 {
2667         complete(udc->done);
2668         kfree (udc);
2669         udc = NULL;
2670 }
2671
2672 static int __init
2673 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2674 {
2675         unsigned        tmp, buf;
2676
2677         /* abolish any previous hardware state */
2678         omap_writew(0, UDC_SYSCON1);
2679         omap_writew(0, UDC_IRQ_EN);
2680         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2681         omap_writew(0, UDC_DMA_IRQ_EN);
2682         omap_writew(0, UDC_RXDMA_CFG);
2683         omap_writew(0, UDC_TXDMA_CFG);
2684
2685         /* UDC_PULLUP_EN gates the chip clock */
2686         // OTG_SYSCON_1 |= DEV_IDLE_EN;
2687
2688         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2689         if (!udc)
2690                 return -ENOMEM;
2691
2692         spin_lock_init (&udc->lock);
2693
2694         udc->gadget.ops = &omap_gadget_ops;
2695         udc->gadget.ep0 = &udc->ep[0].ep;
2696         INIT_LIST_HEAD(&udc->gadget.ep_list);
2697         INIT_LIST_HEAD(&udc->iso);
2698         udc->gadget.speed = USB_SPEED_UNKNOWN;
2699         udc->gadget.name = driver_name;
2700
2701         device_initialize(&udc->gadget.dev);
2702         dev_set_name(&udc->gadget.dev, "gadget");
2703         udc->gadget.dev.release = omap_udc_release;
2704         udc->gadget.dev.parent = &odev->dev;
2705         if (use_dma)
2706                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2707
2708         udc->transceiver = xceiv;
2709
2710         /* ep0 is special; put it right after the SETUP buffer */
2711         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2712                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2713         list_del_init(&udc->ep[0].ep.ep_list);
2714
2715         /* initially disable all non-ep0 endpoints */
2716         for (tmp = 1; tmp < 15; tmp++) {
2717                 omap_writew(0, UDC_EP_RX(tmp));
2718                 omap_writew(0, UDC_EP_TX(tmp));
2719         }
2720
2721 #define OMAP_BULK_EP(name,addr) \
2722         buf = omap_ep_setup(name "-bulk", addr, \
2723                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2724 #define OMAP_INT_EP(name,addr, maxp) \
2725         buf = omap_ep_setup(name "-int", addr, \
2726                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2727 #define OMAP_ISO_EP(name,addr, maxp) \
2728         buf = omap_ep_setup(name "-iso", addr, \
2729                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2730
2731         switch (fifo_mode) {
2732         case 0:
2733                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2734                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2735                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2736                 break;
2737         case 1:
2738                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2739                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2740                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2741
2742                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2743                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2744                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2745
2746                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2747                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2748                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2749
2750                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2751                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2752                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2753
2754                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2755                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2756                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2757                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2758
2759                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2760                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2761                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2762                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2763
2764                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2765                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2766
2767                 break;
2768
2769 #ifdef  USE_ISO
2770         case 2:                 /* mixed iso/bulk */
2771                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2772                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2773                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2774                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2775
2776                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2777
2778                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2779                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2780                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2781                 break;
2782         case 3:                 /* mixed bulk/iso */
2783                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2784                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2785                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2786
2787                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2788                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2789                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2790
2791                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2792                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2793                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2794                 break;
2795 #endif
2796
2797         /* add more modes as needed */
2798
2799         default:
2800                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2801                 return -ENODEV;
2802         }
2803         omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2804         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2805         return 0;
2806 }
2807
2808 static int __init omap_udc_probe(struct platform_device *pdev)
2809 {
2810         int                     status = -ENODEV;
2811         int                     hmc;
2812         struct otg_transceiver  *xceiv = NULL;
2813         const char              *type = NULL;
2814         struct omap_usb_config  *config = pdev->dev.platform_data;
2815         struct clk              *dc_clk;
2816         struct clk              *hhc_clk;
2817
2818         /* NOTE:  "knows" the order of the resources! */
2819         if (!request_mem_region(pdev->resource[0].start,
2820                         pdev->resource[0].end - pdev->resource[0].start + 1,
2821                         driver_name)) {
2822                 DBG("request_mem_region failed\n");
2823                 return -EBUSY;
2824         }
2825
2826         if (cpu_is_omap16xx()) {
2827                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2828                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2829                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2830                 /* can't use omap_udc_enable_clock yet */
2831                 clk_enable(dc_clk);
2832                 clk_enable(hhc_clk);
2833                 udelay(100);
2834         }
2835
2836         if (cpu_is_omap24xx()) {
2837                 dc_clk = clk_get(&pdev->dev, "usb_fck");
2838                 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2839                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2840                 /* can't use omap_udc_enable_clock yet */
2841                 clk_enable(dc_clk);
2842                 clk_enable(hhc_clk);
2843                 udelay(100);
2844         }
2845
2846         INFO("OMAP UDC rev %d.%d%s\n",
2847                 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2848                 config->otg ? ", Mini-AB" : "");
2849
2850         /* use the mode given to us by board init code */
2851         if (cpu_is_omap15xx()) {
2852                 hmc = HMC_1510;
2853                 type = "(unknown)";
2854
2855                 if (machine_without_vbus_sense()) {
2856                         /* just set up software VBUS detect, and then
2857                          * later rig it so we always report VBUS.
2858                          * FIXME without really sensing VBUS, we can't
2859                          * know when to turn PULLUP_EN on/off; and that
2860                          * means we always "need" the 48MHz clock.
2861                          */
2862                         u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2863                         tmp &= ~VBUS_CTRL_1510;
2864                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2865                         tmp |= VBUS_MODE_1510;
2866                         tmp &= ~VBUS_CTRL_1510;
2867                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2868                 }
2869         } else {
2870                 /* The transceiver may package some GPIO logic or handle
2871                  * loopback and/or transceiverless setup; if we find one,
2872                  * use it.  Except for OTG, we don't _need_ to talk to one;
2873                  * but not having one probably means no VBUS detection.
2874                  */
2875                 xceiv = otg_get_transceiver();
2876                 if (xceiv)
2877                         type = xceiv->label;
2878                 else if (config->otg) {
2879                         DBG("OTG requires external transceiver!\n");
2880                         goto cleanup0;
2881                 }
2882
2883                 hmc = HMC_1610;
2884
2885                 if (cpu_is_omap24xx()) {
2886                         /* this could be transceiverless in one of the
2887                          * "we don't need to know" modes.
2888                          */
2889                         type = "external";
2890                         goto known;
2891                 }
2892
2893                 switch (hmc) {
2894                 case 0:                 /* POWERUP DEFAULT == 0 */
2895                 case 4:
2896                 case 12:
2897                 case 20:
2898                         if (!cpu_is_omap1710()) {
2899                                 type = "integrated";
2900                                 break;
2901                         }
2902                         /* FALL THROUGH */
2903                 case 3:
2904                 case 11:
2905                 case 16:
2906                 case 19:
2907                 case 25:
2908                         if (!xceiv) {
2909                                 DBG("external transceiver not registered!\n");
2910                                 type = "unknown";
2911                         }
2912                         break;
2913                 case 21:                        /* internal loopback */
2914                         type = "loopback";
2915                         break;
2916                 case 14:                        /* transceiverless */
2917                         if (cpu_is_omap1710())
2918                                 goto bad_on_1710;
2919                         /* FALL THROUGH */
2920                 case 13:
2921                 case 15:
2922                         type = "no";
2923                         break;
2924
2925                 default:
2926 bad_on_1710:
2927                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2928                         goto cleanup0;
2929                 }
2930         }
2931 known:
2932         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2933
2934         /* a "gadget" abstracts/virtualizes the controller */
2935         status = omap_udc_setup(pdev, xceiv);
2936         if (status) {
2937                 goto cleanup0;
2938         }
2939         xceiv = NULL;
2940         // "udc" is now valid
2941         pullup_disable(udc);
2942 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2943         udc->gadget.is_otg = (config->otg != 0);
2944 #endif
2945
2946         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2947         if (omap_readw(UDC_REV) >= 0x61)
2948                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2949         else
2950                 udc->clr_halt = UDC_RESET_EP;
2951
2952         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2953         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2954                         IRQF_SAMPLE_RANDOM, driver_name, udc);
2955         if (status != 0) {
2956                 ERR("can't get irq %d, err %d\n",
2957                         (int) pdev->resource[1].start, status);
2958                 goto cleanup1;
2959         }
2960
2961         /* USB "non-iso" IRQ (PIO for all but ep0) */
2962         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2963                         IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2964         if (status != 0) {
2965                 ERR("can't get irq %d, err %d\n",
2966                         (int) pdev->resource[2].start, status);
2967                 goto cleanup2;
2968         }
2969 #ifdef  USE_ISO
2970         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2971                         IRQF_DISABLED, "omap_udc iso", udc);
2972         if (status != 0) {
2973                 ERR("can't get irq %d, err %d\n",
2974                         (int) pdev->resource[3].start, status);
2975                 goto cleanup3;
2976         }
2977 #endif
2978         if (cpu_is_omap16xx()) {
2979                 udc->dc_clk = dc_clk;
2980                 udc->hhc_clk = hhc_clk;
2981                 clk_disable(hhc_clk);
2982                 clk_disable(dc_clk);
2983         }
2984
2985         if (cpu_is_omap24xx()) {
2986                 udc->dc_clk = dc_clk;
2987                 udc->hhc_clk = hhc_clk;
2988                 /* FIXME OMAP2 don't release hhc & dc clock */
2989 #if 0
2990                 clk_disable(hhc_clk);
2991                 clk_disable(dc_clk);
2992 #endif
2993         }
2994
2995         create_proc_file();
2996         status = device_add(&udc->gadget.dev);
2997         if (!status)
2998                 return status;
2999         /* If fail, fall through */
3000 #ifdef  USE_ISO
3001 cleanup3:
3002         free_irq(pdev->resource[2].start, udc);
3003 #endif
3004
3005 cleanup2:
3006         free_irq(pdev->resource[1].start, udc);
3007
3008 cleanup1:
3009         kfree (udc);
3010         udc = NULL;
3011
3012 cleanup0:
3013         if (xceiv)
3014                 otg_put_transceiver(xceiv);
3015
3016         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
3017                 clk_disable(hhc_clk);
3018                 clk_disable(dc_clk);
3019                 clk_put(hhc_clk);
3020                 clk_put(dc_clk);
3021         }
3022
3023         release_mem_region(pdev->resource[0].start,
3024                         pdev->resource[0].end - pdev->resource[0].start + 1);
3025
3026         return status;
3027 }
3028
3029 static int __exit omap_udc_remove(struct platform_device *pdev)
3030 {
3031         DECLARE_COMPLETION_ONSTACK(done);
3032
3033         if (!udc)
3034                 return -ENODEV;
3035         if (udc->driver)
3036                 return -EBUSY;
3037
3038         udc->done = &done;
3039
3040         pullup_disable(udc);
3041         if (udc->transceiver) {
3042                 otg_put_transceiver(udc->transceiver);
3043                 udc->transceiver = NULL;
3044         }
3045         omap_writew(0, UDC_SYSCON1);
3046
3047         remove_proc_file();
3048
3049 #ifdef  USE_ISO
3050         free_irq(pdev->resource[3].start, udc);
3051 #endif
3052         free_irq(pdev->resource[2].start, udc);
3053         free_irq(pdev->resource[1].start, udc);
3054
3055         if (udc->dc_clk) {
3056                 if (udc->clk_requested)
3057                         omap_udc_enable_clock(0);
3058                 clk_put(udc->hhc_clk);
3059                 clk_put(udc->dc_clk);
3060         }
3061
3062         release_mem_region(pdev->resource[0].start,
3063                         pdev->resource[0].end - pdev->resource[0].start + 1);
3064
3065         device_unregister(&udc->gadget.dev);
3066         wait_for_completion(&done);
3067
3068         return 0;
3069 }
3070
3071 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3072  * system is forced into deep sleep
3073  *
3074  * REVISIT we should probably reject suspend requests when there's a host
3075  * session active, rather than disconnecting, at least on boards that can
3076  * report VBUS irqs (UDC_DEVSTAT.UDC_ATT).  And in any case, we need to
3077  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3078  * may involve talking to an external transceiver (e.g. isp1301).
3079  */
3080
3081 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3082 {
3083         u32     devstat;
3084
3085         devstat = omap_readw(UDC_DEVSTAT);
3086
3087         /* we're requesting 48 MHz clock if the pullup is enabled
3088          * (== we're attached to the host) and we're not suspended,
3089          * which would prevent entry to deep sleep...
3090          */
3091         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3092                 WARNING("session active; suspend requires disconnect\n");
3093                 omap_pullup(&udc->gadget, 0);
3094         }
3095
3096         return 0;
3097 }
3098
3099 static int omap_udc_resume(struct platform_device *dev)
3100 {
3101         DBG("resume + wakeup/SRP\n");
3102         omap_pullup(&udc->gadget, 1);
3103
3104         /* maybe the host would enumerate us if we nudged it */
3105         msleep(100);
3106         return omap_wakeup(&udc->gadget);
3107 }
3108
3109 /*-------------------------------------------------------------------------*/
3110
3111 static struct platform_driver udc_driver = {
3112         .probe          = omap_udc_probe,
3113         .remove         = __exit_p(omap_udc_remove),
3114         .suspend        = omap_udc_suspend,
3115         .resume         = omap_udc_resume,
3116         .driver         = {
3117                 .owner  = THIS_MODULE,
3118                 .name   = (char *) driver_name,
3119         },
3120 };
3121
3122 static int __init udc_init(void)
3123 {
3124         INFO("%s, version: " DRIVER_VERSION
3125 #ifdef  USE_ISO
3126                 " (iso)"
3127 #endif
3128                 "%s\n", driver_desc,
3129                 use_dma ?  " (dma)" : "");
3130         return platform_driver_register(&udc_driver);
3131 }
3132 module_init(udc_init);
3133
3134 static void __exit udc_exit(void)
3135 {
3136         platform_driver_unregister(&udc_driver);
3137 }
3138 module_exit(udc_exit);
3139
3140 MODULE_DESCRIPTION(DRIVER_DESC);
3141 MODULE_LICENSE("GPL");
3142 MODULE_ALIAS("platform:omap_udc");