drivers/staging/et131x/et1310_phy.c

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright © 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  *------------------------------------------------------------------------------
  10  *
  11  * et1310_phy.c - Routines for configuring and accessing the PHY
  12  *
  13  *------------------------------------------------------------------------------
  14  *
  15  * SOFTWARE LICENSE
  16  *
  17  * This software is provided subject to the following terms and conditions,
  18  * which you should read carefully before using the software.  Using this
  19  * software indicates your acceptance of these terms and conditions.  If you do
  20  * not agree with these terms and conditions, do not use the software.
  21  *
  22  * Copyright © 2005 Agere Systems Inc.
  23  * All rights reserved.
  24  *
  25  * Redistribution and use in source or binary forms, with or without
  26  * modifications, are permitted provided that the following conditions are met:
  27  *
  28  * . Redistributions of source code must retain the above copyright notice, this
  29  *    list of conditions and the following Disclaimer as comments in the code as
  30  *    well as in the documentation and/or other materials provided with the
  31  *    distribution.
  32  *
  33  * . Redistributions in binary form must reproduce the above copyright notice,
  34  *    this list of conditions and the following Disclaimer in the documentation
  35  *    and/or other materials provided with the distribution.
  36  *
  37  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  38  *    may be used to endorse or promote products derived from this software
  39  *    without specific prior written permission.
  40  *
  41  * Disclaimer
  42  *
  43  * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
  44  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  45  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  46  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  47  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  48  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  49  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  50  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  51  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  52  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  53  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  54  * DAMAGE.
  55  *
  56  */
  57
  58 #include "et131x_version.h"
  59 #include "et131x_debug.h"
  60 #include "et131x_defs.h"
  61
  62 #include <linux/pci.h>
  63 #include <linux/init.h>
  64 #include <linux/module.h>
  65 #include <linux/types.h>
  66 #include <linux/kernel.h>
  67
  68 #include <linux/sched.h>
  69 #include <linux/ptrace.h>
  70 #include <linux/slab.h>
  71 #include <linux/ctype.h>
  72 #include <linux/string.h>
  73 #include <linux/timer.h>
  74 #include <linux/interrupt.h>
  75 #include <linux/in.h>
  76 #include <linux/delay.h>
  77 #include <asm/io.h>
  78 #include <asm/system.h>
  79 #include <asm/bitops.h>
  80
  81 #include <linux/netdevice.h>
  82 #include <linux/etherdevice.h>
  83 #include <linux/skbuff.h>
  84 #include <linux/if_arp.h>
  85 #include <linux/ioport.h>
  86 #include <linux/random.h>
  87 #include <linux/delay.h>
  88
  89 #include "et1310_phy.h"
  90 #include "et1310_pm.h"
  91 #include "et1310_jagcore.h"
  92
  93 #include "et131x_adapter.h"
  94 #include "et131x_netdev.h"
  95 #include "et131x_initpci.h"
  96
  97 #include "et1310_address_map.h"
  98 #include "et1310_jagcore.h"
  99 #include "et1310_tx.h"
 100 #include "et1310_rx.h"
 101 #include "et1310_mac.h"
 102
 103 /* Data for debugging facilities */
 104 #ifdef CONFIG_ET131X_DEBUG
 105 extern dbg_info_t *et131x_dbginfo;
 106 #endif /* CONFIG_ET131X_DEBUG */
 107
 108 /* Prototypes for functions with local scope */
 109 static int et131x_xcvr_init(struct et131x_adapter *adapter);
 110
 111 /**
 112  * PhyMiRead - Read from the PHY through the MII Interface on the MAC
 113  * @adapter: pointer to our private adapter structure
 114  * @xcvrAddr: the address of the transciever
 115  * @xcvrReg: the register to read
 116  * @value: pointer to a 16-bit value in which the value will be stored
 117  *
 118  * Returns 0 on success, errno on failure (as defined in errno.h)
 119  */
 120 int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr,
 121               uint8_t xcvrReg, uint16_t *value)
 122 {
 123         struct _MAC_t __iomem *mac = &adapter->CSRAddress->mac;
 124         int status = 0;
 125         uint32_t delay;
 126         MII_MGMT_ADDR_t miiAddr;
 127         MII_MGMT_CMD_t miiCmd;
 128         MII_MGMT_INDICATOR_t miiIndicator;
 129
 130         /* Save a local copy of the registers we are dealing with so we can
 131          * set them back
 132          */
 133         miiAddr.value = readl(&mac->mii_mgmt_addr.value);
 134         miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
 135
 136         /* Stop the current operation */
 137         writel(0, &mac->mii_mgmt_cmd.value);
 138
 139         /* Set up the register we need to read from on the correct PHY */
 140         {
 141                 MII_MGMT_ADDR_t mii_mgmt_addr = { 0 };
 142
 143                 mii_mgmt_addr.bits.phy_addr = xcvrAddr;
 144                 mii_mgmt_addr.bits.reg_addr = xcvrReg;
 145                 writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
 146         }
 147
 148         /* Kick the read cycle off */
 149         delay = 0;
 150
 151         writel(0x1, &mac->mii_mgmt_cmd.value);
 152
 153         do {
 154                 udelay(50);
 155                 delay++;
 156                 miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
 157         } while ((miiIndicator.bits.not_valid || miiIndicator.bits.busy) &&
 158                  delay < 50);
 159
 160         /* If we hit the max delay, we could not read the register */
 161         if (delay >= 50) {
 162                 DBG_WARNING(et131x_dbginfo,
 163                             "xcvrReg 0x%08x could not be read\n", xcvrReg);
 164                 DBG_WARNING(et131x_dbginfo, "status is  0x%08x\n",
 165                             miiIndicator.value);
 166
 167                 status = -EIO;
 168         }
 169
 170         /* If we hit here we were able to read the register and we need to
 171          * return the value to the caller
 172          */
 173         /* TODO: make this stuff a simple readw()?! */
 174         {
 175                 MII_MGMT_STAT_t mii_mgmt_stat;
 176
 177                 mii_mgmt_stat.value = readl(&mac->mii_mgmt_stat.value);
 178                 *value = (uint16_t) mii_mgmt_stat.bits.phy_stat;
 179         }
 180
 181         /* Stop the read operation */
 182         writel(0, &mac->mii_mgmt_cmd.value);
 183
 184         DBG_VERBOSE(et131x_dbginfo, "  xcvr_addr = 0x%02x, "
 185                     "xcvr_reg  = 0x%02x, "
 186                     "value     = 0x%04x.\n", xcvrAddr, xcvrReg, *value);
 187
 188         /* set the registers we touched back to the state at which we entered
 189          * this function
 190          */
 191         writel(miiAddr.value, &mac->mii_mgmt_addr.value);
 192         writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
 193
 194         return status;
 195 }
 196
 197 /**
 198  * MiWrite - Write to a PHY register through the MII interface of the MAC
 199  * @adapter: pointer to our private adapter structure
 200  * @xcvrReg: the register to read
 201  * @value: 16-bit value to write
 202  *
 203  * Return 0 on success, errno on failure (as defined in errno.h)
 204  */
 205 int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value)
 206 {
 207         struct _MAC_t __iomem *mac = &adapter->CSRAddress->mac;
 208         int status = 0;
 209         uint8_t xcvrAddr = adapter->Stats.xcvr_addr;
 210         uint32_t delay;
 211         MII_MGMT_ADDR_t miiAddr;
 212         MII_MGMT_CMD_t miiCmd;
 213         MII_MGMT_INDICATOR_t miiIndicator;
 214
 215         /* Save a local copy of the registers we are dealing with so we can
 216          * set them back
 217          */
 218         miiAddr.value = readl(&mac->mii_mgmt_addr.value);
 219         miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
 220
 221         /* Stop the current operation */
 222         writel(0, &mac->mii_mgmt_cmd.value);
 223
 224         /* Set up the register we need to write to on the correct PHY */
 225         {
 226                 MII_MGMT_ADDR_t mii_mgmt_addr;
 227
 228                 mii_mgmt_addr.bits.phy_addr = xcvrAddr;
 229                 mii_mgmt_addr.bits.reg_addr = xcvrReg;
 230                 writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
 231         }
 232
 233         /* Add the value to write to the registers to the mac */
 234         writel(value, &mac->mii_mgmt_ctrl.value);
 235         delay = 0;
 236
 237         do {
 238                 udelay(50);
 239                 delay++;
 240                 miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
 241         } while (miiIndicator.bits.busy && delay < 100);
 242
 243         /* If we hit the max delay, we could not write the register */
 244         if (delay == 100) {
 245                 uint16_t TempValue;
 246
 247                 DBG_WARNING(et131x_dbginfo,
 248                             "xcvrReg 0x%08x could not be written", xcvrReg);
 249                 DBG_WARNING(et131x_dbginfo, "status is  0x%08x\n",
 250                             miiIndicator.value);
 251                 DBG_WARNING(et131x_dbginfo, "command is  0x%08x\n",
 252                             readl(&mac->mii_mgmt_cmd.value));
 253
 254                 MiRead(adapter, xcvrReg, &TempValue);
 255
 256                 status = -EIO;
 257         }
 258
 259         /* Stop the write operation */
 260         writel(0, &mac->mii_mgmt_cmd.value);
 261
 262         /* set the registers we touched back to the state at which we entered
 263          * this function
 264          */
 265         writel(miiAddr.value, &mac->mii_mgmt_addr.value);
 266         writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
 267
 268         DBG_VERBOSE(et131x_dbginfo, " xcvr_addr = 0x%02x, "
 269                     "xcvr_reg  = 0x%02x, "
 270                     "value     = 0x%04x.\n", xcvrAddr, xcvrReg, value);
 271
 272         return status;
 273 }
 274
 275 /**
 276  * et131x_xcvr_find - Find the PHY ID
 277  * @adapter: pointer to our private adapter structure
 278  *
 279  * Returns 0 on success, errno on failure (as defined in errno.h)
 280  */
 281 int et131x_xcvr_find(struct et131x_adapter *adapter)
 282 {
 283         int status = -ENODEV;
 284         uint8_t xcvr_addr;
 285         MI_IDR1_t idr1;
 286         MI_IDR2_t idr2;
 287         uint32_t xcvr_id;
 288
 289         DBG_ENTER(et131x_dbginfo);
 290
 291         /* We need to get xcvr id and address we just get the first one */
 292         for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
 293                 /* Read the ID from the PHY */
 294                 PhyMiRead(adapter, xcvr_addr,
 295                           (uint8_t) offsetof(MI_REGS_t, idr1),
 296                           &idr1.value);
 297                 PhyMiRead(adapter, xcvr_addr,
 298                           (uint8_t) offsetof(MI_REGS_t, idr2),
 299                           &idr2.value);
 300
 301                 xcvr_id = (uint32_t) ((idr1.value << 16) | idr2.value);
 302
 303                 if ((idr1.value != 0) && (idr1.value != 0xffff)) {
 304                         DBG_TRACE(et131x_dbginfo,
 305                                   "Xcvr addr: 0x%02x\tXcvr_id: 0x%08x\n",
 306                                   xcvr_addr, xcvr_id);
 307
 308                         adapter->Stats.xcvr_id = xcvr_id;
 309                         adapter->Stats.xcvr_addr = xcvr_addr;
 310
 311                         status = 0;
 312                         break;
 313                 }
 314         }
 315
 316         DBG_LEAVE(et131x_dbginfo);
 317         return status;
 318 }
 319
 320 /**
 321  * et131x_setphy_normal - Set PHY for normal operation.
 322  * @adapter: pointer to our private adapter structure
 323  *
 324  * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
 325  * when going to D3 in WOL mode. Also used during initialization to set the
 326  * PHY for normal operation.
 327  */
 328 int et131x_setphy_normal(struct et131x_adapter *adapter)
 329 {
 330         int status;
 331
 332         DBG_ENTER(et131x_dbginfo);
 333
 334         /* Make sure the PHY is powered up */
 335         ET1310_PhyPowerDown(adapter, 0);
 336         status = et131x_xcvr_init(adapter);
 337
 338         DBG_LEAVE(et131x_dbginfo);
 339         return status;
 340 }
 341
 342 /**
 343  * et131x_xcvr_init - Init the phy if we are setting it into force mode
 344  * @adapter: pointer to our private adapter structure
 345  *
 346  * Returns 0 on success, errno on failure (as defined in errno.h)
 347  */
 348 static int et131x_xcvr_init(struct et131x_adapter *adapter)
 349 {
 350         int status = 0;
 351         MI_IMR_t imr;
 352         MI_ISR_t isr;
 353         MI_LCR2_t lcr2;
 354
 355         DBG_ENTER(et131x_dbginfo);
 356
 357         /* Zero out the adapter structure variable representing BMSR */
 358         adapter->Bmsr.value = 0;
 359
 360         MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, isr), &isr.value);
 361
 362         MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, imr), &imr.value);
 363
 364         /* Set the link status interrupt only.  Bad behavior when link status
 365          * and auto neg are set, we run into a nested interrupt problem
 366          */
 367         imr.bits.int_en = 0x1;
 368         imr.bits.link_status = 0x1;
 369         imr.bits.autoneg_status = 0x1;
 370
 371         MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, imr), imr.value);
 372
 373         /* Set the LED behavior such that LED 1 indicates speed (off =
 374          * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
 375          * link and activity (on for link, blink off for activity).
 376          *
 377          * NOTE: Some customizations have been added here for specific
 378          * vendors; The LED behavior is now determined by vendor data in the
 379          * EEPROM. However, the above description is the default.
 380          */
 381         if ((adapter->eepromData[1] & 0x4) == 0) {
 382                 MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
 383                        &lcr2.value);
 384                 if ((adapter->eepromData[1] & 0x8) == 0)
 385                         lcr2.bits.led_tx_rx = 0x3;
 386                 else
 387                         lcr2.bits.led_tx_rx = 0x4;
 388                 lcr2.bits.led_link = 0xa;
 389                 MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
 390                         lcr2.value);
 391         }
 392
 393         /* Determine if we need to go into a force mode and set it */
 394         if (adapter->AiForceSpeed == 0 && adapter->AiForceDpx == 0) {
 395                 if ((adapter->RegistryFlowControl == TxOnly) ||
 396                     (adapter->RegistryFlowControl == Both)) {
 397                         ET1310_PhyAccessMiBit(adapter,
 398                                               TRUEPHY_BIT_SET, 4, 11, NULL);
 399                 } else {
 400                         ET1310_PhyAccessMiBit(adapter,
 401                                               TRUEPHY_BIT_CLEAR, 4, 11, NULL);
 402                 }
 403
 404                 if (adapter->RegistryFlowControl == Both) {
 405                         ET1310_PhyAccessMiBit(adapter,
 406                                               TRUEPHY_BIT_SET, 4, 10, NULL);
 407                 } else {
 408                         ET1310_PhyAccessMiBit(adapter,
 409                                               TRUEPHY_BIT_CLEAR, 4, 10, NULL);
 410                 }
 411
 412                 /* Set the phy to autonegotiation */
 413                 ET1310_PhyAutoNeg(adapter, true);
 414
 415                 /* NOTE - Do we need this? */
 416                 ET1310_PhyAccessMiBit(adapter, TRUEPHY_BIT_SET, 0, 9, NULL);
 417
 418                 DBG_LEAVE(et131x_dbginfo);
 419                 return status;
 420         } else {
 421                 ET1310_PhyAutoNeg(adapter, false);
 422
 423                 /* Set to the correct force mode. */
 424                 if (adapter->AiForceDpx != 1) {
 425                         if ((adapter->RegistryFlowControl == TxOnly) ||
 426                             (adapter->RegistryFlowControl == Both)) {
 427                                 ET1310_PhyAccessMiBit(adapter,
 428                                                       TRUEPHY_BIT_SET, 4, 11,
 429                                                       NULL);
 430                         } else {
 431                                 ET1310_PhyAccessMiBit(adapter,
 432                                                       TRUEPHY_BIT_CLEAR, 4, 11,
 433                                                       NULL);
 434                         }
 435
 436                         if (adapter->RegistryFlowControl == Both) {
 437                                 ET1310_PhyAccessMiBit(adapter,
 438                                                       TRUEPHY_BIT_SET, 4, 10,
 439                                                       NULL);
 440                         } else {
 441                                 ET1310_PhyAccessMiBit(adapter,
 442                                                       TRUEPHY_BIT_CLEAR, 4, 10,
 443                                                       NULL);
 444                         }
 445                 } else {
 446                         ET1310_PhyAccessMiBit(adapter,
 447                                               TRUEPHY_BIT_CLEAR, 4, 10, NULL);
 448                         ET1310_PhyAccessMiBit(adapter,
 449                                               TRUEPHY_BIT_CLEAR, 4, 11, NULL);
 450                 }
 451
 452                 switch (adapter->AiForceSpeed) {
 453                 case 10:
 454                         if (adapter->AiForceDpx == 1) {
 455                                 TPAL_SetPhy10HalfDuplex(adapter);
 456                         } else if (adapter->AiForceDpx == 2) {
 457                                 TPAL_SetPhy10FullDuplex(adapter);
 458                         } else {
 459                                 TPAL_SetPhy10Force(adapter);
 460                         }
 461                         break;
 462                 case 100:
 463                         if (adapter->AiForceDpx == 1) {
 464                                 TPAL_SetPhy100HalfDuplex(adapter);
 465                         } else if (adapter->AiForceDpx == 2) {
 466                                 TPAL_SetPhy100FullDuplex(adapter);
 467                         } else {
 468                                 TPAL_SetPhy100Force(adapter);
 469                         }
 470                         break;
 471                 case 1000:
 472                         TPAL_SetPhy1000FullDuplex(adapter);
 473                         break;
 474                 }
 475
 476                 DBG_LEAVE(et131x_dbginfo);
 477                 return status;
 478         }
 479 }
 480
 481 void et131x_Mii_check(struct et131x_adapter *pAdapter,
 482                       MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints)
 483 {
 484         uint8_t ucLinkStatus;
 485         uint32_t uiAutoNegStatus;
 486         uint32_t uiSpeed;
 487         uint32_t uiDuplex;
 488         uint32_t uiMdiMdix;
 489         uint32_t uiMasterSlave;
 490         uint32_t uiPolarity;
 491         unsigned long lockflags;
 492
 493         DBG_ENTER(et131x_dbginfo);
 494
 495         if (bmsr_ints.bits.link_status) {
 496                 if (bmsr.bits.link_status) {
 497                         pAdapter->PoMgmt.TransPhyComaModeOnBoot = 20;
 498
 499                         /* Update our state variables and indicate the
 500                          * connected state
 501                          */
 502                         spin_lock_irqsave(&pAdapter->Lock, lockflags);
 503
 504                         pAdapter->MediaState = NETIF_STATUS_MEDIA_CONNECT;
 505                         MP_CLEAR_FLAG(pAdapter, fMP_ADAPTER_LINK_DETECTION);
 506
 507                         spin_unlock_irqrestore(&pAdapter->Lock, lockflags);
 508
 509                         /* Don't indicate state if we're in loopback mode */
 510                         if (pAdapter->RegistryPhyLoopbk == false) {
 511                                 netif_carrier_on(pAdapter->netdev);
 512                         }
 513                 } else {
 514                         DBG_WARNING(et131x_dbginfo,
 515                                     "Link down cable problem\n");
 516
 517                         if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_10MBPS) {
 518                                 // NOTE - Is there a way to query this without TruePHY?
 519                                 // && TRU_QueryCoreType(pAdapter->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
 520                                 uint16_t Register18;
 521
 522                                 MiRead(pAdapter, 0x12, &Register18);
 523                                 MiWrite(pAdapter, 0x12, Register18 | 0x4);
 524                                 MiWrite(pAdapter, 0x10, Register18 | 0x8402);
 525                                 MiWrite(pAdapter, 0x11, Register18 | 511);
 526                                 MiWrite(pAdapter, 0x12, Register18);
 527                         }
 528
 529                         /* For the first N seconds of life, we are in "link
 530                          * detection" When we are in this state, we should
 531                          * only report "connected". When the LinkDetection
 532                          * Timer expires, we can report disconnected (handled
 533                          * in the LinkDetectionDPC).
 534                          */
 535                         if ((MP_IS_FLAG_CLEAR
 536                              (pAdapter, fMP_ADAPTER_LINK_DETECTION))
 537                             || (pAdapter->MediaState ==
 538                                 NETIF_STATUS_MEDIA_DISCONNECT)) {
 539                                 spin_lock_irqsave(&pAdapter->Lock, lockflags);
 540                                 pAdapter->MediaState =
 541                                     NETIF_STATUS_MEDIA_DISCONNECT;
 542                                 spin_unlock_irqrestore(&pAdapter->Lock,
 543                                                        lockflags);
 544
 545                                 /* Only indicate state if we're in loopback
 546                                  * mode
 547                                  */
 548                                 if (pAdapter->RegistryPhyLoopbk == false) {
 549                                         netif_carrier_off(pAdapter->netdev);
 550                                 }
 551                         }
 552
 553                         pAdapter->uiLinkSpeed = 0;
 554                         pAdapter->uiDuplexMode = 0;
 555
 556                         /* Free the packets being actively sent & stopped */
 557                         et131x_free_busy_send_packets(pAdapter);
 558
 559                         /* Re-initialize the send structures */
 560                         et131x_init_send(pAdapter);
 561
 562                         /* Reset the RFD list and re-start RU */
 563                         et131x_reset_recv(pAdapter);
 564
 565                         /*
 566                          * Bring the device back to the state it was during
 567                          * init prior to autonegotiation being complete. This
 568                          * way, when we get the auto-neg complete interrupt,
 569                          * we can complete init by calling ConfigMacREGS2.
 570                          */
 571                         et131x_soft_reset(pAdapter);
 572
 573                         /* Setup ET1310 as per the documentation */
 574                         et131x_adapter_setup(pAdapter);
 575
 576                         /* Setup the PHY into coma mode until the cable is
 577                          * plugged back in
 578                          */
 579                         if (pAdapter->RegistryPhyComa == 1) {
 580                                 EnablePhyComa(pAdapter);
 581                         }
 582                 }
 583         }
 584
 585         if (bmsr_ints.bits.auto_neg_complete ||
 586             ((pAdapter->AiForceDpx == 3) && (bmsr_ints.bits.link_status))) {
 587                 if (bmsr.bits.auto_neg_complete || (pAdapter->AiForceDpx == 3)) {
 588                         ET1310_PhyLinkStatus(pAdapter,
 589                                              &ucLinkStatus, &uiAutoNegStatus,
 590                                              &uiSpeed, &uiDuplex, &uiMdiMdix,
 591                                              &uiMasterSlave, &uiPolarity);
 592
 593                         pAdapter->uiLinkSpeed = uiSpeed;
 594                         pAdapter->uiDuplexMode = uiDuplex;
 595
 596                         DBG_TRACE(et131x_dbginfo,
 597                                   "pAdapter->uiLinkSpeed 0x%04x, pAdapter->uiDuplex 0x%08x\n",
 598                                   pAdapter->uiLinkSpeed,
 599                                   pAdapter->uiDuplexMode);
 600
 601                         pAdapter->PoMgmt.TransPhyComaModeOnBoot = 20;
 602
 603                         if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_10MBPS) {
 604                                 // NOTE - Is there a way to query this without TruePHY?
 605                                 // && TRU_QueryCoreType(pAdapter->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
 606                                 uint16_t Register18;
 607
 608                                 MiRead(pAdapter, 0x12, &Register18);
 609                                 MiWrite(pAdapter, 0x12, Register18 | 0x4);
 610                                 MiWrite(pAdapter, 0x10, Register18 | 0x8402);
 611                                 MiWrite(pAdapter, 0x11, Register18 | 511);
 612                                 MiWrite(pAdapter, 0x12, Register18);
 613                         }
 614
 615                         ConfigFlowControl(pAdapter);
 616
 617                         if ((pAdapter->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) &&
 618                             (pAdapter->RegistryJumboPacket > 2048))
 619                         {
 620                                 ET1310_PhyAndOrReg(pAdapter, 0x16, 0xcfff,
 621                                                    0x2000);
 622                         }
 623
 624                         SetRxDmaTimer(pAdapter);
 625                         ConfigMACRegs2(pAdapter);
 626                 }
 627         }
 628
 629         DBG_LEAVE(et131x_dbginfo);
 630 }
 631
 632 /**
 633  * TPAL_SetPhy10HalfDuplex - Force the phy into 10 Base T Half Duplex mode.
 634  * @pAdapter: pointer to the adapter structure
 635  *
 636  * Also sets the MAC so it is syncd up properly
 637  */
 638 void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *pAdapter)
 639 {
 640         DBG_ENTER(et131x_dbginfo);
 641
 642         /* Power down PHY */
 643         ET1310_PhyPowerDown(pAdapter, 1);
 644
 645         /* First we need to turn off all other advertisement */
 646         ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 647
 648         ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 649
 650         /* Set our advertise values accordingly */
 651         ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_HALF);
 652
 653         /* Power up PHY */
 654         ET1310_PhyPowerDown(pAdapter, 0);
 655
 656         DBG_LEAVE(et131x_dbginfo);
 657 }
 658
 659 /**
 660  * TPAL_SetPhy10FullDuplex - Force the phy into 10 Base T Full Duplex mode.
 661  * @pAdapter: pointer to the adapter structure
 662  *
 663  * Also sets the MAC so it is syncd up properly
 664  */
 665 void TPAL_SetPhy10FullDuplex(struct et131x_adapter *pAdapter)
 666 {
 667         DBG_ENTER(et131x_dbginfo);
 668
 669         /* Power down PHY */
 670         ET1310_PhyPowerDown(pAdapter, 1);
 671
 672         /* First we need to turn off all other advertisement */
 673         ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 674
 675         ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 676
 677         /* Set our advertise values accordingly */
 678         ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
 679
 680         /* Power up PHY */
 681         ET1310_PhyPowerDown(pAdapter, 0);
 682
 683         DBG_LEAVE(et131x_dbginfo);
 684 }
 685
 686 /**
 687  * TPAL_SetPhy10Force - Force Base-T FD mode WITHOUT using autonegotiation
 688  * @pAdapter: pointer to the adapter structure
 689  */
 690 void TPAL_SetPhy10Force(struct et131x_adapter *pAdapter)
 691 {
 692         DBG_ENTER(et131x_dbginfo);
 693
 694         /* Power down PHY */
 695         ET1310_PhyPowerDown(pAdapter, 1);
 696
 697         /* Disable autoneg */
 698         ET1310_PhyAutoNeg(pAdapter, false);
 699
 700         /* Disable all advertisement */
 701         ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 702         ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 703         ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 704
 705         /* Force 10 Mbps */
 706         ET1310_PhySpeedSelect(pAdapter, TRUEPHY_SPEED_10MBPS);
 707
 708         /* Force Full duplex */
 709         ET1310_PhyDuplexMode(pAdapter, TRUEPHY_DUPLEX_FULL);
 710
 711         /* Power up PHY */
 712         ET1310_PhyPowerDown(pAdapter, 0);
 713
 714         DBG_LEAVE(et131x_dbginfo);
 715 }
 716
 717 /**
 718  * TPAL_SetPhy100HalfDuplex - Force 100 Base T Half Duplex mode.
 719  * @pAdapter: pointer to the adapter structure
 720  *
 721  * Also sets the MAC so it is syncd up properly.
 722  */
 723 void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *pAdapter)
 724 {
 725         DBG_ENTER(et131x_dbginfo);
 726
 727         /* Power down PHY */
 728         ET1310_PhyPowerDown(pAdapter, 1);
 729
 730         /* first we need to turn off all other advertisement */
 731         ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 732
 733         ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 734
 735         /* Set our advertise values accordingly */
 736         ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_HALF);
 737
 738         /* Set speed */
 739         ET1310_PhySpeedSelect(pAdapter, TRUEPHY_SPEED_100MBPS);
 740
 741         /* Power up PHY */
 742         ET1310_PhyPowerDown(pAdapter, 0);
 743
 744         DBG_LEAVE(et131x_dbginfo);
 745 }
 746
 747 /**
 748  * TPAL_SetPhy100FullDuplex - Force 100 Base T Full Duplex mode.
 749  * @pAdapter: pointer to the adapter structure
 750  *
 751  * Also sets the MAC so it is syncd up properly
 752  */
 753 void TPAL_SetPhy100FullDuplex(struct et131x_adapter *pAdapter)
 754 {
 755         DBG_ENTER(et131x_dbginfo);
 756
 757         /* Power down PHY */
 758         ET1310_PhyPowerDown(pAdapter, 1);
 759
 760         /* First we need to turn off all other advertisement */
 761         ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 762
 763         ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 764
 765         /* Set our advertise values accordingly */
 766         ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
 767
 768         /* Power up PHY */
 769         ET1310_PhyPowerDown(pAdapter, 0);
 770
 771         DBG_LEAVE(et131x_dbginfo);
 772 }
 773
 774 /**
 775  * TPAL_SetPhy100Force - Force 100 BaseT FD mode WITHOUT using autonegotiation
 776  * @pAdapter: pointer to the adapter structure
 777  */
 778 void TPAL_SetPhy100Force(struct et131x_adapter *pAdapter)
 779 {
 780         DBG_ENTER(et131x_dbginfo);
 781
 782         /* Power down PHY */
 783         ET1310_PhyPowerDown(pAdapter, 1);
 784
 785         /* Disable autoneg */
 786         ET1310_PhyAutoNeg(pAdapter, false);
 787
 788         /* Disable all advertisement */
 789         ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 790         ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 791         ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 792
 793         /* Force 100 Mbps */
 794         ET1310_PhySpeedSelect(pAdapter, TRUEPHY_SPEED_100MBPS);
 795
 796         /* Force Full duplex */
 797         ET1310_PhyDuplexMode(pAdapter, TRUEPHY_DUPLEX_FULL);
 798
 799         /* Power up PHY */
 800         ET1310_PhyPowerDown(pAdapter, 0);
 801
 802         DBG_LEAVE(et131x_dbginfo);
 803 }
 804
 805 /**
 806  * TPAL_SetPhy1000FullDuplex - Force 1000 Base T Full Duplex mode
 807  * @pAdapter: pointer to the adapter structure
 808  *
 809  * Also sets the MAC so it is syncd up properly.
 810  */
 811 void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *pAdapter)
 812 {
 813         DBG_ENTER(et131x_dbginfo);
 814
 815         /* Power down PHY */
 816         ET1310_PhyPowerDown(pAdapter, 1);
 817
 818         /* first we need to turn off all other advertisement */
 819         ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 820
 821         ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 822
 823         /* set our advertise values accordingly */
 824         ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
 825
 826         /* power up PHY */
 827         ET1310_PhyPowerDown(pAdapter, 0);
 828
 829         DBG_LEAVE(et131x_dbginfo);
 830 }
 831
 832 /**
 833  * TPAL_SetPhyAutoNeg - Set phy to autonegotiation mode.
 834  * @pAdapter: pointer to the adapter structure
 835  */
 836 void TPAL_SetPhyAutoNeg(struct et131x_adapter *pAdapter)
 837 {
 838         DBG_ENTER(et131x_dbginfo);
 839
 840         /* Power down PHY */
 841         ET1310_PhyPowerDown(pAdapter, 1);
 842
 843         /* Turn on advertisement of all capabilities */
 844         ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_BOTH);
 845
 846         ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_BOTH);
 847
 848         if (pAdapter->DeviceID != ET131X_PCI_DEVICE_ID_FAST) {
 849                 ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
 850         } else {
 851                 ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
 852         }
 853
 854         /* Make sure auto-neg is ON (it is disabled in FORCE modes) */
 855         ET1310_PhyAutoNeg(pAdapter, true);
 856
 857         /* Power up PHY */
 858         ET1310_PhyPowerDown(pAdapter, 0);
 859
 860         DBG_LEAVE(et131x_dbginfo);
 861 }
 862
 863
 864 /*
 865  * The routines which follow provide low-level access to the PHY, and are used
 866  * primarily by the routines above (although there are a few places elsewhere
 867  * in the driver where this level of access is required).
 868  */
 869
 870 static const uint16_t ConfigPhy[25][2] = {
 871         /* Reg      Value      Register */
 872         /* Addr                         */
 873         {0x880B, 0x0926},       /* AfeIfCreg4B1000Msbs */
 874         {0x880C, 0x0926},       /* AfeIfCreg4B100Msbs */
 875         {0x880D, 0x0926},       /* AfeIfCreg4B10Msbs */
 876
 877         {0x880E, 0xB4D3},       /* AfeIfCreg4B1000Lsbs */
 878         {0x880F, 0xB4D3},       /* AfeIfCreg4B100Lsbs */
 879         {0x8810, 0xB4D3},       /* AfeIfCreg4B10Lsbs */
 880
 881         {0x8805, 0xB03E},       /* AfeIfCreg3B1000Msbs */
 882         {0x8806, 0xB03E},       /* AfeIfCreg3B100Msbs */
 883         {0x8807, 0xFF00},       /* AfeIfCreg3B10Msbs */
 884
 885         {0x8808, 0xE090},       /* AfeIfCreg3B1000Lsbs */
 886         {0x8809, 0xE110},       /* AfeIfCreg3B100Lsbs */
 887         {0x880A, 0x0000},       /* AfeIfCreg3B10Lsbs */
 888
 889         {0x300D, 1},            /* DisableNorm */
 890
 891         {0x280C, 0x0180},       /* LinkHoldEnd */
 892
 893         {0x1C21, 0x0002},       /* AlphaM */
 894
 895         {0x3821, 6},            /* FfeLkgTx0 */
 896         {0x381D, 1},            /* FfeLkg1g4 */
 897         {0x381E, 1},            /* FfeLkg1g5 */
 898         {0x381F, 1},            /* FfeLkg1g6 */
 899         {0x3820, 1},            /* FfeLkg1g7 */
 900
 901         {0x8402, 0x01F0},       /* Btinact */
 902         {0x800E, 20},           /* LftrainTime */
 903         {0x800F, 24},           /* DvguardTime */
 904         {0x8010, 46},           /* IdlguardTime */
 905
 906         {0, 0}
 907
 908 };
 909
 910 /* condensed version of the phy initialization routine */
 911 void ET1310_PhyInit(struct et131x_adapter *pAdapter)
 912 {
 913         uint16_t usData, usIndex;
 914
 915         if (pAdapter == NULL) {
 916                 return;
 917         }
 918
 919         // get the identity (again ?)
 920         MiRead(pAdapter, PHY_ID_1, &usData);
 921         MiRead(pAdapter, PHY_ID_2, &usData);
 922
 923         // what does this do/achieve ?
 924         MiRead(pAdapter, PHY_MPHY_CONTROL_REG, &usData);        // should read 0002
 925         MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0006);
 926
 927         // read modem register 0402, should I do something with the return data ?
 928         MiWrite(pAdapter, PHY_INDEX_REG, 0x0402);
 929         MiRead(pAdapter, PHY_DATA_REG, &usData);
 930
 931         // what does this do/achieve ?
 932         MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0002);
 933
 934         // get the identity (again ?)
 935         MiRead(pAdapter, PHY_ID_1, &usData);
 936         MiRead(pAdapter, PHY_ID_2, &usData);
 937
 938         // what does this achieve ?
 939         MiRead(pAdapter, PHY_MPHY_CONTROL_REG, &usData);        // should read 0002
 940         MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0006);
 941
 942         // read modem register 0402, should I do something with the return data?
 943         MiWrite(pAdapter, PHY_INDEX_REG, 0x0402);
 944         MiRead(pAdapter, PHY_DATA_REG, &usData);
 945
 946         MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0002);
 947
 948         // what does this achieve (should return 0x1040)
 949         MiRead(pAdapter, PHY_CONTROL, &usData);
 950         MiRead(pAdapter, PHY_MPHY_CONTROL_REG, &usData);        // should read 0002
 951         MiWrite(pAdapter, PHY_CONTROL, 0x1840);
 952
 953         MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0007);
 954
 955         // here the writing of the array starts....
 956         usIndex = 0;
 957         while (ConfigPhy[usIndex][0] != 0x0000) {
 958                 // write value
 959                 MiWrite(pAdapter, PHY_INDEX_REG, ConfigPhy[usIndex][0]);
 960                 MiWrite(pAdapter, PHY_DATA_REG, ConfigPhy[usIndex][1]);
 961
 962                 // read it back
 963                 MiWrite(pAdapter, PHY_INDEX_REG, ConfigPhy[usIndex][0]);
 964                 MiRead(pAdapter, PHY_DATA_REG, &usData);
 965
 966                 // do a check on the value read back ?
 967                 usIndex++;
 968         }
 969         // here the writing of the array ends...
 970
 971         MiRead(pAdapter, PHY_CONTROL, &usData); // 0x1840
 972         MiRead(pAdapter, PHY_MPHY_CONTROL_REG, &usData);        // should read 0007
 973         MiWrite(pAdapter, PHY_CONTROL, 0x1040);
 974         MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0002);
 975 }
 976
 977 void ET1310_PhyReset(struct et131x_adapter *pAdapter)
 978 {
 979         MiWrite(pAdapter, PHY_CONTROL, 0x8000);
 980 }
 981
 982 void ET1310_PhyPowerDown(struct et131x_adapter *pAdapter, bool down)
 983 {
 984         uint16_t usData;
 985
 986         MiRead(pAdapter, PHY_CONTROL, &usData);
 987
 988         if (down == false) {
 989                 // Power UP
 990                 usData &= ~0x0800;
 991                 MiWrite(pAdapter, PHY_CONTROL, usData);
 992         } else {
 993                 // Power DOWN
 994                 usData |= 0x0800;
 995                 MiWrite(pAdapter, PHY_CONTROL, usData);
 996         }
 997 }
 998
 999 void ET1310_PhyAutoNeg(struct et131x_adapter *pAdapter, bool enable)
1000 {
1001         uint16_t usData;
1002
1003         MiRead(pAdapter, PHY_CONTROL, &usData);
1004
1005         if (enable == true) {
1006                 // Autonegotiation ON
1007                 usData |= 0x1000;
1008                 MiWrite(pAdapter, PHY_CONTROL, usData);
1009         } else {
1010                 // Autonegotiation OFF
1011                 usData &= ~0x1000;
1012                 MiWrite(pAdapter, PHY_CONTROL, usData);
1013         }
1014 }
1015
1016 void ET1310_PhyDuplexMode(struct et131x_adapter *pAdapter, uint16_t duplex)
1017 {
1018         uint16_t usData;
1019
1020         MiRead(pAdapter, PHY_CONTROL, &usData);
1021
1022         if (duplex == TRUEPHY_DUPLEX_FULL) {
1023                 // Set Full Duplex
1024                 usData |= 0x100;
1025                 MiWrite(pAdapter, PHY_CONTROL, usData);
1026         } else {
1027                 // Set Half Duplex
1028                 usData &= ~0x100;
1029                 MiWrite(pAdapter, PHY_CONTROL, usData);
1030         }
1031 }
1032
1033 void ET1310_PhySpeedSelect(struct et131x_adapter *pAdapter, uint16_t speed)
1034 {
1035         uint16_t usData;
1036
1037         // Read the PHY control register
1038         MiRead(pAdapter, PHY_CONTROL, &usData);
1039
1040         // Clear all Speed settings (Bits 6, 13)
1041         usData &= ~0x2040;
1042
1043         // Reset the speed bits based on user selection
1044         switch (speed) {
1045         case TRUEPHY_SPEED_10MBPS:
1046                 // Bits already cleared above, do nothing
1047                 break;
1048
1049         case TRUEPHY_SPEED_100MBPS:
1050                 // 100M == Set bit 13
1051                 usData |= 0x2000;
1052                 break;
1053
1054         case TRUEPHY_SPEED_1000MBPS:
1055         default:
1056                 usData |= 0x0040;
1057                 break;
1058         }
1059
1060         // Write back the new speed
1061         MiWrite(pAdapter, PHY_CONTROL, usData);
1062 }
1063
1064 void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *pAdapter,
1065                                   uint16_t duplex)
1066 {
1067         uint16_t usData;
1068
1069         // Read the PHY 1000 Base-T Control Register
1070         MiRead(pAdapter, PHY_1000_CONTROL, &usData);
1071
1072         // Clear Bits 8,9
1073         usData &= ~0x0300;
1074
1075         switch (duplex) {
1076         case TRUEPHY_ADV_DUPLEX_NONE:
1077                 // Duplex already cleared, do nothing
1078                 break;
1079
1080         case TRUEPHY_ADV_DUPLEX_FULL:
1081                 // Set Bit 9
1082                 usData |= 0x0200;
1083                 break;
1084
1085         case TRUEPHY_ADV_DUPLEX_HALF:
1086                 // Set Bit 8
1087                 usData |= 0x0100;
1088                 break;
1089
1090         case TRUEPHY_ADV_DUPLEX_BOTH:
1091         default:
1092                 usData |= 0x0300;
1093                 break;
1094         }
1095
1096         // Write back advertisement
1097         MiWrite(pAdapter, PHY_1000_CONTROL, usData);
1098 }
1099
1100 void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *pAdapter,
1101                                  uint16_t duplex)
1102 {
1103         uint16_t usData;
1104
1105         // Read the Autonegotiation Register (10/100)
1106         MiRead(pAdapter, PHY_AUTO_ADVERTISEMENT, &usData);
1107
1108         // Clear bits 7,8
1109         usData &= ~0x0180;
1110
1111         switch (duplex) {
1112         case TRUEPHY_ADV_DUPLEX_NONE:
1113                 // Duplex already cleared, do nothing
1114                 break;
1115
1116         case TRUEPHY_ADV_DUPLEX_FULL:
1117                 // Set Bit 8
1118                 usData |= 0x0100;
1119                 break;
1120
1121         case TRUEPHY_ADV_DUPLEX_HALF:
1122                 // Set Bit 7
1123                 usData |= 0x0080;
1124                 break;
1125
1126         case TRUEPHY_ADV_DUPLEX_BOTH:
1127         default:
1128                 // Set Bits 7,8
1129                 usData |= 0x0180;
1130                 break;
1131         }
1132
1133         // Write back advertisement
1134         MiWrite(pAdapter, PHY_AUTO_ADVERTISEMENT, usData);
1135 }
1136
1137 void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *pAdapter,
1138                                 uint16_t duplex)
1139 {
1140         uint16_t usData;
1141
1142         // Read the Autonegotiation Register (10/100)
1143         MiRead(pAdapter, PHY_AUTO_ADVERTISEMENT, &usData);
1144
1145         // Clear bits 5,6
1146         usData &= ~0x0060;
1147
1148         switch (duplex) {
1149         case TRUEPHY_ADV_DUPLEX_NONE:
1150                 // Duplex already cleared, do nothing
1151                 break;
1152
1153         case TRUEPHY_ADV_DUPLEX_FULL:
1154                 // Set Bit 6
1155                 usData |= 0x0040;
1156                 break;
1157
1158         case TRUEPHY_ADV_DUPLEX_HALF:
1159                 // Set Bit 5
1160                 usData |= 0x0020;
1161                 break;
1162
1163         case TRUEPHY_ADV_DUPLEX_BOTH:
1164         default:
1165                 // Set Bits 5,6
1166                 usData |= 0x0060;
1167                 break;
1168         }
1169
1170         // Write back advertisement
1171         MiWrite(pAdapter, PHY_AUTO_ADVERTISEMENT, usData);
1172 }
1173
1174 void ET1310_PhyLinkStatus(struct et131x_adapter *pAdapter,
1175                           uint8_t *ucLinkStatus,
1176                           uint32_t *uiAutoNeg,
1177                           uint32_t *uiLinkSpeed,
1178                           uint32_t *uiDuplexMode,
1179                           uint32_t *uiMdiMdix,
1180                           uint32_t *uiMasterSlave, uint32_t *uiPolarity)
1181 {
1182         uint16_t usMiStatus = 0;
1183         uint16_t us1000BaseT = 0;
1184         uint16_t usVmiPhyStatus = 0;
1185         uint16_t usControl = 0;
1186
1187         MiRead(pAdapter, PHY_STATUS, &usMiStatus);
1188         MiRead(pAdapter, PHY_1000_STATUS, &us1000BaseT);
1189         MiRead(pAdapter, PHY_PHY_STATUS, &usVmiPhyStatus);
1190         MiRead(pAdapter, PHY_CONTROL, &usControl);
1191
1192         if (ucLinkStatus) {
1193                 *ucLinkStatus =
1194                     (unsigned char)((usVmiPhyStatus & 0x0040) ? 1 : 0);
1195         }
1196
1197         if (uiAutoNeg) {
1198                 *uiAutoNeg =
1199                     (usControl & 0x1000) ? ((usVmiPhyStatus & 0x0020) ?
1200                                             TRUEPHY_ANEG_COMPLETE :
1201                                             TRUEPHY_ANEG_NOT_COMPLETE) :
1202                     TRUEPHY_ANEG_DISABLED;
1203         }
1204
1205         if (uiLinkSpeed) {
1206                 *uiLinkSpeed = (usVmiPhyStatus & 0x0300) >> 8;
1207         }
1208
1209         if (uiDuplexMode) {
1210                 *uiDuplexMode = (usVmiPhyStatus & 0x0080) >> 7;
1211         }
1212
1213         if (uiMdiMdix) {
1214                 /* NOTE: Need to complete this */
1215                 *uiMdiMdix = 0;
1216         }
1217
1218         if (uiMasterSlave) {
1219                 *uiMasterSlave =
1220                     (us1000BaseT & 0x4000) ? TRUEPHY_CFG_MASTER :
1221                     TRUEPHY_CFG_SLAVE;
1222         }
1223
1224         if (uiPolarity) {
1225                 *uiPolarity =
1226                     (usVmiPhyStatus & 0x0400) ? TRUEPHY_POLARITY_INVERTED :
1227                     TRUEPHY_POLARITY_NORMAL;
1228         }
1229 }
1230
1231 void ET1310_PhyAndOrReg(struct et131x_adapter *pAdapter,
1232                         uint16_t regnum, uint16_t andMask, uint16_t orMask)
1233 {
1234         uint16_t reg;
1235
1236         // Read the requested register
1237         MiRead(pAdapter, regnum, &reg);
1238
1239         // Apply the AND mask
1240         reg &= andMask;
1241
1242         // Apply the OR mask
1243         reg |= orMask;
1244
1245         // Write the value back to the register
1246         MiWrite(pAdapter, regnum, reg);
1247 }
1248
1249 void ET1310_PhyAccessMiBit(struct et131x_adapter *pAdapter, uint16_t action,
1250                            uint16_t regnum, uint16_t bitnum, uint8_t *value)
1251 {
1252         uint16_t reg;
1253         uint16_t mask = 0;
1254
1255         // Create a mask to isolate the requested bit
1256         mask = 0x0001 << bitnum;
1257
1258         // Read the requested register
1259         MiRead(pAdapter, regnum, &reg);
1260
1261         switch (action) {
1262         case TRUEPHY_BIT_READ:
1263                 if (value != NULL) {
1264                         *value = (reg & mask) >> bitnum;
1265                 }
1266                 break;
1267
1268         case TRUEPHY_BIT_SET:
1269                 reg |= mask;
1270                 MiWrite(pAdapter, regnum, reg);
1271                 break;
1272
1273         case TRUEPHY_BIT_CLEAR:
1274                 reg &= ~mask;
1275                 MiWrite(pAdapter, regnum, reg);
1276                 break;
1277
1278         default:
1279                 break;
1280         }
1281 }