drivers/net/smc911x.h

   1 /*------------------------------------------------------------------------
   2  . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
   3  .
   4  . Copyright (C) 2005 Sensoria Corp.
   5  . Derived from the unified SMC91x driver by Nicolas Pitre
   6  .
   7  . This program is free software; you can redistribute it and/or modify
   8  . it under the terms of the GNU General Public License as published by
   9  . the Free Software Foundation; either version 2 of the License, or
  10  . (at your option) any later version.
  11  .
  12  . This program is distributed in the hope that it will be useful,
  13  . but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  . GNU General Public License for more details.
  16  .
  17  . You should have received a copy of the GNU General Public License
  18  . along with this program; if not, write to the Free Software
  19  . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  .
  21  . Information contained in this file was obtained from the LAN9118
  22  . manual from SMC.  To get a copy, if you really want one, you can find
  23  . information under www.smsc.com.
  24  .
  25  . Authors
  26  .       Dustin McIntire                 <dustin@sensoria.com>
  27  .
  28  ---------------------------------------------------------------------------*/
  29 #ifndef _SMC911X_H_
  30 #define _SMC911X_H_
  31
  32 /*
  33  * Use the DMA feature on PXA chips
  34  */
  35 #ifdef CONFIG_ARCH_PXA
  36   #define SMC_USE_PXA_DMA       1
  37   #define SMC_USE_16BIT         0
  38   #define SMC_USE_32BIT         1
  39   #define SMC_IRQ_SENSE         IRQF_TRIGGER_FALLING
  40 #elif defined(CONFIG_SH_MAGIC_PANEL_R2)
  41   #define SMC_USE_SH_DMA        0
  42   #define SMC_USE_16BIT         0
  43   #define SMC_USE_32BIT         1
  44   #define SMC_IRQ_SENSE         IRQF_TRIGGER_LOW
  45 #elif defined(CONFIG_ARCH_OMAP34XX)
  46   #define SMC_USE_16BIT         0
  47   #define SMC_USE_32BIT         1
  48   #define SMC_IRQ_SENSE         IRQF_TRIGGER_LOW
  49   #define SMC_MEM_RESERVED      1
  50 #endif
  51
  52
  53 /*
  54  * Define the bus width specific IO macros
  55  */
  56
  57 #if     SMC_USE_16BIT
  58 #define SMC_inb(a, r)                    readb((a) + (r))
  59 #define SMC_inw(a, r)                    readw((a) + (r))
  60 #define SMC_inl(a, r)                    ((SMC_inw(a, r) & 0xFFFF)+(SMC_inw(a+2, r)<<16))
  61 #define SMC_outb(v, a, r)                writeb(v, (a) + (r))
  62 #define SMC_outw(v, a, r)                writew(v, (a) + (r))
  63 #define SMC_outl(v, a, r)                        \
  64         do{                                      \
  65                  writel(v & 0xFFFF, (a) + (r));  \
  66                  writel(v >> 16, (a) + (r) + 2); \
  67          } while (0)
  68 #define SMC_insl(a, r, p, l)     readsw((short*)((a) + (r)), p, l*2)
  69 #define SMC_outsl(a, r, p, l)    writesw((short*)((a) + (r)), p, l*2)
  70
  71 #elif   SMC_USE_32BIT
  72 #define SMC_inb(a, r)            readb((a) + (r))
  73 #define SMC_inw(a, r)            readw((a) + (r))
  74 #define SMC_inl(a, r)            readl((a) + (r))
  75 #define SMC_outb(v, a, r)        writeb(v, (a) + (r))
  76 #define SMC_outl(v, a, r)        writel(v, (a) + (r))
  77 #define SMC_insl(a, r, p, l)     readsl((int*)((a) + (r)), p, l)
  78 #define SMC_outsl(a, r, p, l)    writesl((int*)((a) + (r)), p, l)
  79
  80 #endif /* SMC_USE_16BIT */
  81
  82
  83
  84 #ifdef SMC_USE_PXA_DMA
  85 #define SMC_USE_DMA
  86
  87 /*
  88  * Define the request and free functions
  89  * These are unfortunately architecture specific as no generic allocation
  90  * mechanism exits
  91  */
  92 #define SMC_DMA_REQUEST(dev, handler) \
  93          pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
  94
  95 #define SMC_DMA_FREE(dev, dma) \
  96          pxa_free_dma(dma)
  97
  98 #define SMC_DMA_ACK_IRQ(dev, dma)                                       \
  99 {                                                                       \
 100         if (DCSR(dma) & DCSR_BUSERR) {                                  \
 101                 printk("%s: DMA %d bus error!\n", dev->name, dma);      \
 102         }                                                               \
 103         DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;            \
 104 }
 105
 106 /*
 107  * Use a DMA for RX and TX packets.
 108  */
 109 #include <linux/dma-mapping.h>
 110 #include <asm/dma.h>
 111 #include <asm/arch/pxa-regs.h>
 112
 113 static dma_addr_t rx_dmabuf, tx_dmabuf;
 114 static int rx_dmalen, tx_dmalen;
 115
 116 #ifdef SMC_insl
 117 #undef SMC_insl
 118 #define SMC_insl(a, r, p, l) \
 119         smc_pxa_dma_insl(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
 120
 121 static inline void
 122 smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
 123                 int reg, int dma, u_char *buf, int len)
 124 {
 125         /* 64 bit alignment is required for memory to memory DMA */
 126         if ((long)buf & 4) {
 127                 *((u32 *)buf) = SMC_inl(ioaddr, reg);
 128                 buf += 4;
 129                 len--;
 130         }
 131
 132         len *= 4;
 133         rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
 134         rx_dmalen = len;
 135         DCSR(dma) = DCSR_NODESC;
 136         DTADR(dma) = rx_dmabuf;
 137         DSADR(dma) = physaddr + reg;
 138         DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
 139                 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
 140         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 141 }
 142 #endif
 143
 144 #ifdef SMC_insw
 145 #undef SMC_insw
 146 #define SMC_insw(a, r, p, l) \
 147         smc_pxa_dma_insw(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
 148
 149 static inline void
 150 smc_pxa_dma_insw(struct device *dev, u_long ioaddr, u_long physaddr,
 151                 int reg, int dma, u_char *buf, int len)
 152 {
 153         /* 64 bit alignment is required for memory to memory DMA */
 154         while ((long)buf & 6) {
 155                 *((u16 *)buf) = SMC_inw(ioaddr, reg);
 156                 buf += 2;
 157                 len--;
 158         }
 159
 160         len *= 2;
 161         rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
 162         rx_dmalen = len;
 163         DCSR(dma) = DCSR_NODESC;
 164         DTADR(dma) = rx_dmabuf;
 165         DSADR(dma) = physaddr + reg;
 166         DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
 167                 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
 168         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 169 }
 170 #endif
 171
 172 #ifdef SMC_outsl
 173 #undef SMC_outsl
 174 #define SMC_outsl(a, r, p, l) \
 175          smc_pxa_dma_outsl(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
 176
 177 static inline void
 178 smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr,
 179                 int reg, int dma, u_char *buf, int len)
 180 {
 181         /* 64 bit alignment is required for memory to memory DMA */
 182         if ((long)buf & 4) {
 183                 SMC_outl(*((u32 *)buf), ioaddr, reg);
 184                 buf += 4;
 185                 len--;
 186         }
 187
 188         len *= 4;
 189         tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
 190         tx_dmalen = len;
 191         DCSR(dma) = DCSR_NODESC;
 192         DSADR(dma) = tx_dmabuf;
 193         DTADR(dma) = physaddr + reg;
 194         DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
 195                 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
 196         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 197 }
 198 #endif
 199
 200 #ifdef SMC_outsw
 201 #undef SMC_outsw
 202 #define SMC_outsw(a, r, p, l) \
 203         smc_pxa_dma_outsw(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
 204
 205 static inline void
 206 smc_pxa_dma_outsw(struct device *dev, u_long ioaddr, u_long physaddr,
 207                   int reg, int dma, u_char *buf, int len)
 208 {
 209         /* 64 bit alignment is required for memory to memory DMA */
 210         while ((long)buf & 6) {
 211                 SMC_outw(*((u16 *)buf), ioaddr, reg);
 212                 buf += 2;
 213                 len--;
 214         }
 215
 216         len *= 2;
 217         tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
 218         tx_dmalen = len;
 219         DCSR(dma) = DCSR_NODESC;
 220         DSADR(dma) = tx_dmabuf;
 221         DTADR(dma) = physaddr + reg;
 222         DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
 223                 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
 224         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 225 }
 226 #endif
 227
 228 #endif   /* SMC_USE_PXA_DMA */
 229
 230
 231 /* Chip Parameters and Register Definitions */
 232
 233 #define SMC911X_TX_FIFO_LOW_THRESHOLD   (1536*2)
 234
 235 #define SMC911X_IO_EXTENT        0x100
 236
 237 #define SMC911X_EEPROM_LEN       7
 238
 239 /* Below are the register offsets and bit definitions
 240  * of the Lan911x memory space
 241  */
 242 #define RX_DATA_FIFO             (0x00)
 243
 244 #define TX_DATA_FIFO             (0x20)
 245 #define TX_CMD_A_INT_ON_COMP_           (0x80000000)
 246 #define TX_CMD_A_INT_BUF_END_ALGN_      (0x03000000)
 247 #define TX_CMD_A_INT_4_BYTE_ALGN_       (0x00000000)
 248 #define TX_CMD_A_INT_16_BYTE_ALGN_      (0x01000000)
 249 #define TX_CMD_A_INT_32_BYTE_ALGN_      (0x02000000)
 250 #define TX_CMD_A_INT_DATA_OFFSET_       (0x001F0000)
 251 #define TX_CMD_A_INT_FIRST_SEG_         (0x00002000)
 252 #define TX_CMD_A_INT_LAST_SEG_          (0x00001000)
 253 #define TX_CMD_A_BUF_SIZE_              (0x000007FF)
 254 #define TX_CMD_B_PKT_TAG_               (0xFFFF0000)
 255 #define TX_CMD_B_ADD_CRC_DISABLE_       (0x00002000)
 256 #define TX_CMD_B_DISABLE_PADDING_       (0x00001000)
 257 #define TX_CMD_B_PKT_BYTE_LENGTH_       (0x000007FF)
 258
 259 #define RX_STATUS_FIFO          (0x40)
 260 #define RX_STS_PKT_LEN_                 (0x3FFF0000)
 261 #define RX_STS_ES_                      (0x00008000)
 262 #define RX_STS_BCST_                    (0x00002000)
 263 #define RX_STS_LEN_ERR_                 (0x00001000)
 264 #define RX_STS_RUNT_ERR_                (0x00000800)
 265 #define RX_STS_MCAST_                   (0x00000400)
 266 #define RX_STS_TOO_LONG_                (0x00000080)
 267 #define RX_STS_COLL_                    (0x00000040)
 268 #define RX_STS_ETH_TYPE_                (0x00000020)
 269 #define RX_STS_WDOG_TMT_                (0x00000010)
 270 #define RX_STS_MII_ERR_                 (0x00000008)
 271 #define RX_STS_DRIBBLING_               (0x00000004)
 272 #define RX_STS_CRC_ERR_                 (0x00000002)
 273 #define RX_STATUS_FIFO_PEEK     (0x44)
 274 #define TX_STATUS_FIFO          (0x48)
 275 #define TX_STS_TAG_                     (0xFFFF0000)
 276 #define TX_STS_ES_                      (0x00008000)
 277 #define TX_STS_LOC_                     (0x00000800)
 278 #define TX_STS_NO_CARR_                 (0x00000400)
 279 #define TX_STS_LATE_COLL_               (0x00000200)
 280 #define TX_STS_MANY_COLL_               (0x00000100)
 281 #define TX_STS_COLL_CNT_                (0x00000078)
 282 #define TX_STS_MANY_DEFER_              (0x00000004)
 283 #define TX_STS_UNDERRUN_                (0x00000002)
 284 #define TX_STS_DEFERRED_                (0x00000001)
 285 #define TX_STATUS_FIFO_PEEK     (0x4C)
 286 #define ID_REV                  (0x50)
 287 #define ID_REV_CHIP_ID_                 (0xFFFF0000)  /* RO */
 288 #define ID_REV_REV_ID_                  (0x0000FFFF)  /* RO */
 289
 290 #define INT_CFG                 (0x54)
 291 #define INT_CFG_INT_DEAS_               (0xFF000000)  /* R/W */
 292 #define INT_CFG_INT_DEAS_CLR_           (0x00004000)
 293 #define INT_CFG_INT_DEAS_STS_           (0x00002000)
 294 #define INT_CFG_IRQ_INT_                (0x00001000)  /* RO */
 295 #define INT_CFG_IRQ_EN_                 (0x00000100)  /* R/W */
 296 #define INT_CFG_IRQ_POL_                (0x00000010)  /* R/W Not Affected by SW Reset */
 297 #define INT_CFG_IRQ_TYPE_               (0x00000001)  /* R/W Not Affected by SW Reset */
 298
 299 #define INT_STS                 (0x58)
 300 #define INT_STS_SW_INT_                 (0x80000000)  /* R/WC */
 301 #define INT_STS_TXSTOP_INT_             (0x02000000)  /* R/WC */
 302 #define INT_STS_RXSTOP_INT_             (0x01000000)  /* R/WC */
 303 #define INT_STS_RXDFH_INT_              (0x00800000)  /* R/WC */
 304 #define INT_STS_RXDF_INT_               (0x00400000)  /* R/WC */
 305 #define INT_STS_TX_IOC_                 (0x00200000)  /* R/WC */
 306 #define INT_STS_RXD_INT_                (0x00100000)  /* R/WC */
 307 #define INT_STS_GPT_INT_                (0x00080000)  /* R/WC */
 308 #define INT_STS_PHY_INT_                (0x00040000)  /* RO */
 309 #define INT_STS_PME_INT_                (0x00020000)  /* R/WC */
 310 #define INT_STS_TXSO_                   (0x00010000)  /* R/WC */
 311 #define INT_STS_RWT_                    (0x00008000)  /* R/WC */
 312 #define INT_STS_RXE_                    (0x00004000)  /* R/WC */
 313 #define INT_STS_TXE_                    (0x00002000)  /* R/WC */
 314 //#define       INT_STS_ERX_            (0x00001000)  /* R/WC */
 315 #define INT_STS_TDFU_                   (0x00000800)  /* R/WC */
 316 #define INT_STS_TDFO_                   (0x00000400)  /* R/WC */
 317 #define INT_STS_TDFA_                   (0x00000200)  /* R/WC */
 318 #define INT_STS_TSFF_                   (0x00000100)  /* R/WC */
 319 #define INT_STS_TSFL_                   (0x00000080)  /* R/WC */
 320 //#define       INT_STS_RXDF_           (0x00000040)  /* R/WC */
 321 #define INT_STS_RDFO_                   (0x00000040)  /* R/WC */
 322 #define INT_STS_RDFL_                   (0x00000020)  /* R/WC */
 323 #define INT_STS_RSFF_                   (0x00000010)  /* R/WC */
 324 #define INT_STS_RSFL_                   (0x00000008)  /* R/WC */
 325 #define INT_STS_GPIO2_INT_              (0x00000004)  /* R/WC */
 326 #define INT_STS_GPIO1_INT_              (0x00000002)  /* R/WC */
 327 #define INT_STS_GPIO0_INT_              (0x00000001)  /* R/WC */
 328
 329 #define INT_EN                  (0x5C)
 330 #define INT_EN_SW_INT_EN_               (0x80000000)  /* R/W */
 331 #define INT_EN_TXSTOP_INT_EN_           (0x02000000)  /* R/W */
 332 #define INT_EN_RXSTOP_INT_EN_           (0x01000000)  /* R/W */
 333 #define INT_EN_RXDFH_INT_EN_            (0x00800000)  /* R/W */
 334 //#define       INT_EN_RXDF_INT_EN_             (0x00400000)  /* R/W */
 335 #define INT_EN_TIOC_INT_EN_             (0x00200000)  /* R/W */
 336 #define INT_EN_RXD_INT_EN_              (0x00100000)  /* R/W */
 337 #define INT_EN_GPT_INT_EN_              (0x00080000)  /* R/W */
 338 #define INT_EN_PHY_INT_EN_              (0x00040000)  /* R/W */
 339 #define INT_EN_PME_INT_EN_              (0x00020000)  /* R/W */
 340 #define INT_EN_TXSO_EN_                 (0x00010000)  /* R/W */
 341 #define INT_EN_RWT_EN_                  (0x00008000)  /* R/W */
 342 #define INT_EN_RXE_EN_                  (0x00004000)  /* R/W */
 343 #define INT_EN_TXE_EN_                  (0x00002000)  /* R/W */
 344 //#define       INT_EN_ERX_EN_                  (0x00001000)  /* R/W */
 345 #define INT_EN_TDFU_EN_                 (0x00000800)  /* R/W */
 346 #define INT_EN_TDFO_EN_                 (0x00000400)  /* R/W */
 347 #define INT_EN_TDFA_EN_                 (0x00000200)  /* R/W */
 348 #define INT_EN_TSFF_EN_                 (0x00000100)  /* R/W */
 349 #define INT_EN_TSFL_EN_                 (0x00000080)  /* R/W */
 350 //#define       INT_EN_RXDF_EN_                 (0x00000040)  /* R/W */
 351 #define INT_EN_RDFO_EN_                 (0x00000040)  /* R/W */
 352 #define INT_EN_RDFL_EN_                 (0x00000020)  /* R/W */
 353 #define INT_EN_RSFF_EN_                 (0x00000010)  /* R/W */
 354 #define INT_EN_RSFL_EN_                 (0x00000008)  /* R/W */
 355 #define INT_EN_GPIO2_INT_               (0x00000004)  /* R/W */
 356 #define INT_EN_GPIO1_INT_               (0x00000002)  /* R/W */
 357 #define INT_EN_GPIO0_INT_               (0x00000001)  /* R/W */
 358
 359 #define BYTE_TEST               (0x64)
 360 #define FIFO_INT                (0x68)
 361 #define FIFO_INT_TX_AVAIL_LEVEL_        (0xFF000000)  /* R/W */
 362 #define FIFO_INT_TX_STS_LEVEL_          (0x00FF0000)  /* R/W */
 363 #define FIFO_INT_RX_AVAIL_LEVEL_        (0x0000FF00)  /* R/W */
 364 #define FIFO_INT_RX_STS_LEVEL_          (0x000000FF)  /* R/W */
 365
 366 #define RX_CFG                  (0x6C)
 367 #define RX_CFG_RX_END_ALGN_             (0xC0000000)  /* R/W */
 368 #define         RX_CFG_RX_END_ALGN4_            (0x00000000)  /* R/W */
 369 #define         RX_CFG_RX_END_ALGN16_           (0x40000000)  /* R/W */
 370 #define         RX_CFG_RX_END_ALGN32_           (0x80000000)  /* R/W */
 371 #define RX_CFG_RX_DMA_CNT_              (0x0FFF0000)  /* R/W */
 372 #define RX_CFG_RX_DUMP_                 (0x00008000)  /* R/W */
 373 #define RX_CFG_RXDOFF_                  (0x00001F00)  /* R/W */
 374 //#define       RX_CFG_RXBAD_                   (0x00000001)  /* R/W */
 375
 376 #define TX_CFG                  (0x70)
 377 //#define       TX_CFG_TX_DMA_LVL_              (0xE0000000)     /* R/W */
 378 //#define       TX_CFG_TX_DMA_CNT_              (0x0FFF0000)     /* R/W Self Clearing */
 379 #define TX_CFG_TXS_DUMP_                (0x00008000)  /* Self Clearing */
 380 #define TX_CFG_TXD_DUMP_                (0x00004000)  /* Self Clearing */
 381 #define TX_CFG_TXSAO_                   (0x00000004)  /* R/W */
 382 #define TX_CFG_TX_ON_                   (0x00000002)  /* R/W */
 383 #define TX_CFG_STOP_TX_                 (0x00000001)  /* Self Clearing */
 384
 385 #define HW_CFG                  (0x74)
 386 #define HW_CFG_TTM_                     (0x00200000)  /* R/W */
 387 #define HW_CFG_SF_                      (0x00100000)  /* R/W */
 388 #define HW_CFG_TX_FIF_SZ_               (0x000F0000)  /* R/W */
 389 #define HW_CFG_TR_                      (0x00003000)  /* R/W */
 390 #define HW_CFG_PHY_CLK_SEL_             (0x00000060)  /* R/W */
 391 #define          HW_CFG_PHY_CLK_SEL_INT_PHY_    (0x00000000) /* R/W */
 392 #define          HW_CFG_PHY_CLK_SEL_EXT_PHY_    (0x00000020) /* R/W */
 393 #define          HW_CFG_PHY_CLK_SEL_CLK_DIS_    (0x00000040) /* R/W */
 394 #define HW_CFG_SMI_SEL_                 (0x00000010)  /* R/W */
 395 #define HW_CFG_EXT_PHY_DET_             (0x00000008)  /* RO */
 396 #define HW_CFG_EXT_PHY_EN_              (0x00000004)  /* R/W */
 397 #define HW_CFG_32_16_BIT_MODE_          (0x00000004)  /* RO */
 398 #define HW_CFG_SRST_TO_                 (0x00000002)  /* RO */
 399 #define HW_CFG_SRST_                    (0x00000001)  /* Self Clearing */
 400
 401 #define RX_DP_CTRL              (0x78)
 402 #define RX_DP_CTRL_RX_FFWD_             (0x80000000)  /* R/W */
 403 #define RX_DP_CTRL_FFWD_BUSY_           (0x80000000)  /* RO */
 404
 405 #define RX_FIFO_INF             (0x7C)
 406 #define  RX_FIFO_INF_RXSUSED_           (0x00FF0000)  /* RO */
 407 #define  RX_FIFO_INF_RXDUSED_           (0x0000FFFF)  /* RO */
 408
 409 #define TX_FIFO_INF             (0x80)
 410 #define TX_FIFO_INF_TSUSED_             (0x00FF0000)  /* RO */
 411 #define TX_FIFO_INF_TDFREE_             (0x0000FFFF)  /* RO */
 412
 413 #define PMT_CTRL                (0x84)
 414 #define PMT_CTRL_PM_MODE_               (0x00003000)  /* Self Clearing */
 415 #define PMT_CTRL_PHY_RST_               (0x00000400)  /* Self Clearing */
 416 #define PMT_CTRL_WOL_EN_                (0x00000200)  /* R/W */
 417 #define PMT_CTRL_ED_EN_                 (0x00000100)  /* R/W */
 418 #define PMT_CTRL_PME_TYPE_              (0x00000040)  /* R/W Not Affected by SW Reset */
 419 #define PMT_CTRL_WUPS_                  (0x00000030)  /* R/WC */
 420 #define         PMT_CTRL_WUPS_NOWAKE_           (0x00000000)  /* R/WC */
 421 #define         PMT_CTRL_WUPS_ED_               (0x00000010)  /* R/WC */
 422 #define         PMT_CTRL_WUPS_WOL_              (0x00000020)  /* R/WC */
 423 #define         PMT_CTRL_WUPS_MULTI_            (0x00000030)  /* R/WC */
 424 #define PMT_CTRL_PME_IND_               (0x00000008)  /* R/W */
 425 #define PMT_CTRL_PME_POL_               (0x00000004)  /* R/W */
 426 #define PMT_CTRL_PME_EN_                (0x00000002)  /* R/W Not Affected by SW Reset */
 427 #define PMT_CTRL_READY_                 (0x00000001)  /* RO */
 428
 429 #define GPIO_CFG                (0x88)
 430 #define GPIO_CFG_LED3_EN_               (0x40000000)  /* R/W */
 431 #define GPIO_CFG_LED2_EN_               (0x20000000)  /* R/W */
 432 #define GPIO_CFG_LED1_EN_               (0x10000000)  /* R/W */
 433 #define GPIO_CFG_GPIO2_INT_POL_         (0x04000000)  /* R/W */
 434 #define GPIO_CFG_GPIO1_INT_POL_         (0x02000000)  /* R/W */
 435 #define GPIO_CFG_GPIO0_INT_POL_         (0x01000000)  /* R/W */
 436 #define GPIO_CFG_EEPR_EN_               (0x00700000)  /* R/W */
 437 #define GPIO_CFG_GPIOBUF2_              (0x00040000)  /* R/W */
 438 #define GPIO_CFG_GPIOBUF1_              (0x00020000)  /* R/W */
 439 #define GPIO_CFG_GPIOBUF0_              (0x00010000)  /* R/W */
 440 #define GPIO_CFG_GPIODIR2_              (0x00000400)  /* R/W */
 441 #define GPIO_CFG_GPIODIR1_              (0x00000200)  /* R/W */
 442 #define GPIO_CFG_GPIODIR0_              (0x00000100)  /* R/W */
 443 #define GPIO_CFG_GPIOD4_                (0x00000010)  /* R/W */
 444 #define GPIO_CFG_GPIOD3_                (0x00000008)  /* R/W */
 445 #define GPIO_CFG_GPIOD2_                (0x00000004)  /* R/W */
 446 #define GPIO_CFG_GPIOD1_                (0x00000002)  /* R/W */
 447 #define GPIO_CFG_GPIOD0_                (0x00000001)  /* R/W */
 448
 449 #define GPT_CFG                 (0x8C)
 450 #define GPT_CFG_TIMER_EN_               (0x20000000)  /* R/W */
 451 #define GPT_CFG_GPT_LOAD_               (0x0000FFFF)  /* R/W */
 452
 453 #define GPT_CNT                 (0x90)
 454 #define GPT_CNT_GPT_CNT_                (0x0000FFFF)  /* RO */
 455
 456 #define ENDIAN                  (0x98)
 457 #define FREE_RUN                (0x9C)
 458 #define RX_DROP                 (0xA0)
 459 #define MAC_CSR_CMD             (0xA4)
 460 #define  MAC_CSR_CMD_CSR_BUSY_          (0x80000000)  /* Self Clearing */
 461 #define  MAC_CSR_CMD_R_NOT_W_           (0x40000000)  /* R/W */
 462 #define  MAC_CSR_CMD_CSR_ADDR_          (0x000000FF)  /* R/W */
 463
 464 #define MAC_CSR_DATA            (0xA8)
 465 #define AFC_CFG                 (0xAC)
 466 #define         AFC_CFG_AFC_HI_                 (0x00FF0000)  /* R/W */
 467 #define         AFC_CFG_AFC_LO_                 (0x0000FF00)  /* R/W */
 468 #define         AFC_CFG_BACK_DUR_               (0x000000F0)  /* R/W */
 469 #define         AFC_CFG_FCMULT_                 (0x00000008)  /* R/W */
 470 #define         AFC_CFG_FCBRD_                  (0x00000004)  /* R/W */
 471 #define         AFC_CFG_FCADD_                  (0x00000002)  /* R/W */
 472 #define         AFC_CFG_FCANY_                  (0x00000001)  /* R/W */
 473
 474 #define E2P_CMD                 (0xB0)
 475 #define E2P_CMD_EPC_BUSY_               (0x80000000)  /* Self Clearing */
 476 #define E2P_CMD_EPC_CMD_                        (0x70000000)  /* R/W */
 477 #define         E2P_CMD_EPC_CMD_READ_           (0x00000000)  /* R/W */
 478 #define         E2P_CMD_EPC_CMD_EWDS_           (0x10000000)  /* R/W */
 479 #define         E2P_CMD_EPC_CMD_EWEN_           (0x20000000)  /* R/W */
 480 #define         E2P_CMD_EPC_CMD_WRITE_          (0x30000000)  /* R/W */
 481 #define         E2P_CMD_EPC_CMD_WRAL_           (0x40000000)  /* R/W */
 482 #define         E2P_CMD_EPC_CMD_ERASE_          (0x50000000)  /* R/W */
 483 #define         E2P_CMD_EPC_CMD_ERAL_           (0x60000000)  /* R/W */
 484 #define         E2P_CMD_EPC_CMD_RELOAD_         (0x70000000)  /* R/W */
 485 #define E2P_CMD_EPC_TIMEOUT_            (0x00000200)  /* RO */
 486 #define E2P_CMD_MAC_ADDR_LOADED_        (0x00000100)  /* RO */
 487 #define E2P_CMD_EPC_ADDR_               (0x000000FF)  /* R/W */
 488
 489 #define E2P_DATA                (0xB4)
 490 #define E2P_DATA_EEPROM_DATA_           (0x000000FF)  /* R/W */
 491 /* end of LAN register offsets and bit definitions */
 492
 493 /*
 494  ****************************************************************************
 495  ****************************************************************************
 496  * MAC Control and Status Register (Indirect Address)
 497  * Offset (through the MAC_CSR CMD and DATA port)
 498  ****************************************************************************
 499  ****************************************************************************
 500  *
 501  */
 502 #define MAC_CR                  (0x01)  /* R/W */
 503
 504 /* MAC_CR - MAC Control Register */
 505 #define MAC_CR_RXALL_                   (0x80000000)
 506 // TODO: delete this bit? It is not described in the data sheet.
 507 #define MAC_CR_HBDIS_                   (0x10000000)
 508 #define MAC_CR_RCVOWN_                  (0x00800000)
 509 #define MAC_CR_LOOPBK_                  (0x00200000)
 510 #define MAC_CR_FDPX_                    (0x00100000)
 511 #define MAC_CR_MCPAS_                   (0x00080000)
 512 #define MAC_CR_PRMS_                    (0x00040000)
 513 #define MAC_CR_INVFILT_                 (0x00020000)
 514 #define MAC_CR_PASSBAD_                 (0x00010000)
 515 #define MAC_CR_HFILT_                   (0x00008000)
 516 #define MAC_CR_HPFILT_                  (0x00002000)
 517 #define MAC_CR_LCOLL_                   (0x00001000)
 518 #define MAC_CR_BCAST_                   (0x00000800)
 519 #define MAC_CR_DISRTY_                  (0x00000400)
 520 #define MAC_CR_PADSTR_                  (0x00000100)
 521 #define MAC_CR_BOLMT_MASK_              (0x000000C0)
 522 #define MAC_CR_DFCHK_                   (0x00000020)
 523 #define MAC_CR_TXEN_                    (0x00000008)
 524 #define MAC_CR_RXEN_                    (0x00000004)
 525
 526 #define ADDRH                   (0x02)    /* R/W mask 0x0000FFFFUL */
 527 #define ADDRL                   (0x03)    /* R/W mask 0xFFFFFFFFUL */
 528 #define HASHH                   (0x04)    /* R/W */
 529 #define HASHL                   (0x05)    /* R/W */
 530
 531 #define MII_ACC                 (0x06)    /* R/W */
 532 #define MII_ACC_PHY_ADDR_               (0x0000F800)
 533 #define MII_ACC_MIIRINDA_               (0x000007C0)
 534 #define MII_ACC_MII_WRITE_              (0x00000002)
 535 #define MII_ACC_MII_BUSY_               (0x00000001)
 536
 537 #define MII_DATA                (0x07)    /* R/W mask 0x0000FFFFUL */
 538
 539 #define FLOW                    (0x08)    /* R/W */
 540 #define FLOW_FCPT_                      (0xFFFF0000)
 541 #define FLOW_FCPASS_                    (0x00000004)
 542 #define FLOW_FCEN_                      (0x00000002)
 543 #define FLOW_FCBSY_                     (0x00000001)
 544
 545 #define VLAN1                   (0x09)    /* R/W mask 0x0000FFFFUL */
 546 #define VLAN1_VTI1_                     (0x0000ffff)
 547
 548 #define VLAN2                   (0x0A)    /* R/W mask 0x0000FFFFUL */
 549 #define VLAN2_VTI2_                     (0x0000ffff)
 550
 551 #define WUFF                    (0x0B)    /* WO */
 552
 553 #define WUCSR                   (0x0C)    /* R/W */
 554 #define WUCSR_GUE_                      (0x00000200)
 555 #define WUCSR_WUFR_                     (0x00000040)
 556 #define WUCSR_MPR_                      (0x00000020)
 557 #define WUCSR_WAKE_EN_                  (0x00000004)
 558 #define WUCSR_MPEN_                     (0x00000002)
 559
 560 /*
 561  ****************************************************************************
 562  * Chip Specific MII Defines
 563  ****************************************************************************
 564  *
 565  * Phy register offsets and bit definitions
 566  *
 567  */
 568
 569 #define PHY_MODE_CTRL_STS       ((u32)17)       /* Mode Control/Status Register */
 570 //#define MODE_CTRL_STS_FASTRIP_          ((u16)0x4000)
 571 #define MODE_CTRL_STS_EDPWRDOWN_         ((u16)0x2000)
 572 //#define MODE_CTRL_STS_LOWSQEN_           ((u16)0x0800)
 573 //#define MODE_CTRL_STS_MDPREBP_           ((u16)0x0400)
 574 //#define MODE_CTRL_STS_FARLOOPBACK_  ((u16)0x0200)
 575 //#define MODE_CTRL_STS_FASTEST_           ((u16)0x0100)
 576 //#define MODE_CTRL_STS_REFCLKEN_          ((u16)0x0010)
 577 //#define MODE_CTRL_STS_PHYADBP_           ((u16)0x0008)
 578 //#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
 579 #define MODE_CTRL_STS_ENERGYON_         ((u16)0x0002)
 580
 581 #define PHY_INT_SRC                     ((u32)29)
 582 #define PHY_INT_SRC_ENERGY_ON_                  ((u16)0x0080)
 583 #define PHY_INT_SRC_ANEG_COMP_                  ((u16)0x0040)
 584 #define PHY_INT_SRC_REMOTE_FAULT_               ((u16)0x0020)
 585 #define PHY_INT_SRC_LINK_DOWN_                  ((u16)0x0010)
 586 #define PHY_INT_SRC_ANEG_LP_ACK_                ((u16)0x0008)
 587 #define PHY_INT_SRC_PAR_DET_FAULT_              ((u16)0x0004)
 588 #define PHY_INT_SRC_ANEG_PGRX_                  ((u16)0x0002)
 589
 590 #define PHY_INT_MASK                    ((u32)30)
 591 #define PHY_INT_MASK_ENERGY_ON_                 ((u16)0x0080)
 592 #define PHY_INT_MASK_ANEG_COMP_                 ((u16)0x0040)
 593 #define PHY_INT_MASK_REMOTE_FAULT_              ((u16)0x0020)
 594 #define PHY_INT_MASK_LINK_DOWN_                 ((u16)0x0010)
 595 #define PHY_INT_MASK_ANEG_LP_ACK_               ((u16)0x0008)
 596 #define PHY_INT_MASK_PAR_DET_FAULT_             ((u16)0x0004)
 597 #define PHY_INT_MASK_ANEG_PGRX_                 ((u16)0x0002)
 598
 599 #define PHY_SPECIAL                     ((u32)31)
 600 #define PHY_SPECIAL_ANEG_DONE_                  ((u16)0x1000)
 601 #define PHY_SPECIAL_RES_                        ((u16)0x0040)
 602 #define PHY_SPECIAL_RES_MASK_                   ((u16)0x0FE1)
 603 #define PHY_SPECIAL_SPD_                        ((u16)0x001C)
 604 #define PHY_SPECIAL_SPD_10HALF_                 ((u16)0x0004)
 605 #define PHY_SPECIAL_SPD_10FULL_                 ((u16)0x0014)
 606 #define PHY_SPECIAL_SPD_100HALF_                ((u16)0x0008)
 607 #define PHY_SPECIAL_SPD_100FULL_                ((u16)0x0018)
 608
 609 #define LAN911X_INTERNAL_PHY_ID         (0x0007C000)
 610
 611 /* Chip ID values */
 612 #define CHIP_9115       0x115
 613 #define CHIP_9116       0x116
 614 #define CHIP_9117       0x117
 615 #define CHIP_9118       0x118
 616
 617 struct chip_id {
 618         u16 id;
 619         char *name;
 620 };
 621
 622 static const struct chip_id chip_ids[] =  {
 623         { CHIP_9115, "LAN9115" },
 624         { CHIP_9116, "LAN9116" },
 625         { CHIP_9117, "LAN9117" },
 626         { CHIP_9118, "LAN9118" },
 627         { 0, NULL },
 628 };
 629
 630 #define IS_REV_A(x)     ((x & 0xFFFF)==0)
 631
 632 /*
 633  * Macros to abstract register access according to the data bus
 634  * capabilities.  Please use those and not the in/out primitives.
 635  */
 636 /* FIFO read/write macros */
 637 #define SMC_PUSH_DATA(p, l)     SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 )
 638 #define SMC_PULL_DATA(p, l)     SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 )
 639 #define SMC_SET_TX_FIFO(x)      SMC_outl( x, ioaddr, TX_DATA_FIFO )
 640 #define SMC_GET_RX_FIFO()       SMC_inl( ioaddr, RX_DATA_FIFO )
 641
 642
 643 /* I/O mapped register read/write macros */
 644 #define SMC_GET_TX_STS_FIFO()           SMC_inl( ioaddr, TX_STATUS_FIFO )
 645 #define SMC_GET_RX_STS_FIFO()           SMC_inl( ioaddr, RX_STATUS_FIFO )
 646 #define SMC_GET_RX_STS_FIFO_PEEK()      SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK )
 647 #define SMC_GET_PN()                    (SMC_inl( ioaddr, ID_REV ) >> 16)
 648 #define SMC_GET_REV()                   (SMC_inl( ioaddr, ID_REV ) & 0xFFFF)
 649 #define SMC_GET_IRQ_CFG()               SMC_inl( ioaddr, INT_CFG )
 650 #define SMC_SET_IRQ_CFG(x)              SMC_outl( x, ioaddr, INT_CFG )
 651 #define SMC_GET_INT()                   SMC_inl( ioaddr, INT_STS )
 652 #define SMC_ACK_INT(x)                  SMC_outl( x, ioaddr, INT_STS )
 653 #define SMC_GET_INT_EN()                SMC_inl( ioaddr, INT_EN )
 654 #define SMC_SET_INT_EN(x)               SMC_outl( x, ioaddr, INT_EN )
 655 #define SMC_GET_BYTE_TEST()             SMC_inl( ioaddr, BYTE_TEST )
 656 #define SMC_SET_BYTE_TEST(x)            SMC_outl( x, ioaddr, BYTE_TEST )
 657 #define SMC_GET_FIFO_INT()              SMC_inl( ioaddr, FIFO_INT )
 658 #define SMC_SET_FIFO_INT(x)             SMC_outl( x, ioaddr, FIFO_INT )
 659 #define SMC_SET_FIFO_TDA(x)                                     \
 660         do {                                                    \
 661                 unsigned long __flags;                          \
 662                 int __mask;                                     \
 663                 local_irq_save(__flags);                        \
 664                 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<24);      \
 665                 SMC_SET_FIFO_INT( __mask | (x)<<24 );           \
 666                 local_irq_restore(__flags);                     \
 667         } while (0)
 668 #define SMC_SET_FIFO_TSL(x)                                     \
 669         do {                                                    \
 670                 unsigned long __flags;                          \
 671                 int __mask;                                     \
 672                 local_irq_save(__flags);                        \
 673                 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<16);      \
 674                 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); \
 675                 local_irq_restore(__flags);                     \
 676         } while (0)
 677 #define SMC_SET_FIFO_RSA(x)                                     \
 678         do {                                                    \
 679                 unsigned long __flags;                          \
 680                 int __mask;                                     \
 681                 local_irq_save(__flags);                        \
 682                 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<8);       \
 683                 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8));  \
 684                 local_irq_restore(__flags);                     \
 685         } while (0)
 686 #define SMC_SET_FIFO_RSL(x)                                     \
 687         do {                                                    \
 688                 unsigned long __flags;                          \
 689                 int __mask;                                     \
 690                 local_irq_save(__flags);                        \
 691                 __mask = SMC_GET_FIFO_INT() & ~0xFF;            \
 692                 SMC_SET_FIFO_INT( __mask | ((x) & 0xFF));       \
 693                 local_irq_restore(__flags);                     \
 694         } while (0)
 695 #define SMC_GET_RX_CFG()                SMC_inl( ioaddr, RX_CFG )
 696 #define SMC_SET_RX_CFG(x)               SMC_outl( x, ioaddr, RX_CFG )
 697 #define SMC_GET_TX_CFG()                SMC_inl( ioaddr, TX_CFG )
 698 #define SMC_SET_TX_CFG(x)               SMC_outl( x, ioaddr, TX_CFG )
 699 #define SMC_GET_HW_CFG()                SMC_inl( ioaddr, HW_CFG )
 700 #define SMC_SET_HW_CFG(x)               SMC_outl( x, ioaddr, HW_CFG )
 701 #define SMC_GET_RX_DP_CTRL()            SMC_inl( ioaddr, RX_DP_CTRL )
 702 #define SMC_SET_RX_DP_CTRL(x)           SMC_outl( x, ioaddr, RX_DP_CTRL )
 703 #define SMC_GET_PMT_CTRL()              SMC_inl( ioaddr, PMT_CTRL )
 704 #define SMC_SET_PMT_CTRL(x)             SMC_outl( x, ioaddr, PMT_CTRL )
 705 #define SMC_GET_GPIO_CFG()              SMC_inl( ioaddr, GPIO_CFG )
 706 #define SMC_SET_GPIO_CFG(x)             SMC_outl( x, ioaddr, GPIO_CFG )
 707 #define SMC_GET_RX_FIFO_INF()           SMC_inl( ioaddr, RX_FIFO_INF )
 708 #define SMC_SET_RX_FIFO_INF(x)          SMC_outl( x, ioaddr, RX_FIFO_INF )
 709 #define SMC_GET_TX_FIFO_INF()           SMC_inl( ioaddr, TX_FIFO_INF )
 710 #define SMC_SET_TX_FIFO_INF(x)          SMC_outl( x, ioaddr, TX_FIFO_INF )
 711 #define SMC_GET_GPT_CFG()               SMC_inl( ioaddr, GPT_CFG )
 712 #define SMC_SET_GPT_CFG(x)              SMC_outl( x, ioaddr, GPT_CFG )
 713 #define SMC_GET_RX_DROP()               SMC_inl( ioaddr, RX_DROP )
 714 #define SMC_SET_RX_DROP(x)              SMC_outl( x, ioaddr, RX_DROP )
 715 #define SMC_GET_MAC_CMD()               SMC_inl( ioaddr, MAC_CSR_CMD )
 716 #define SMC_SET_MAC_CMD(x)              SMC_outl( x, ioaddr, MAC_CSR_CMD )
 717 #define SMC_GET_MAC_DATA()              SMC_inl( ioaddr, MAC_CSR_DATA )
 718 #define SMC_SET_MAC_DATA(x)             SMC_outl( x, ioaddr, MAC_CSR_DATA )
 719 #define SMC_GET_AFC_CFG()               SMC_inl( ioaddr, AFC_CFG )
 720 #define SMC_SET_AFC_CFG(x)              SMC_outl( x, ioaddr, AFC_CFG )
 721 #define SMC_GET_E2P_CMD()               SMC_inl( ioaddr, E2P_CMD )
 722 #define SMC_SET_E2P_CMD(x)              SMC_outl( x, ioaddr, E2P_CMD )
 723 #define SMC_GET_E2P_DATA()              SMC_inl( ioaddr, E2P_DATA )
 724 #define SMC_SET_E2P_DATA(x)             SMC_outl( x, ioaddr, E2P_DATA )
 725
 726 /* MAC register read/write macros */
 727 #define SMC_GET_MAC_CSR(a,v)                                            \
 728         do {                                                            \
 729                 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);      \
 730                 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ |                 \
 731                         MAC_CSR_CMD_R_NOT_W_ | (a) );                   \
 732                 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);      \
 733                 v = SMC_GET_MAC_DATA();                                 \
 734         } while (0)
 735 #define SMC_SET_MAC_CSR(a,v)                                            \
 736         do {                                                            \
 737                 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);      \
 738                 SMC_SET_MAC_DATA(v);                                    \
 739                 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) );          \
 740                 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);      \
 741         } while (0)
 742 #define SMC_GET_MAC_CR(x)       SMC_GET_MAC_CSR( MAC_CR, x )
 743 #define SMC_SET_MAC_CR(x)       SMC_SET_MAC_CSR( MAC_CR, x )
 744 #define SMC_GET_ADDRH(x)        SMC_GET_MAC_CSR( ADDRH, x )
 745 #define SMC_SET_ADDRH(x)        SMC_SET_MAC_CSR( ADDRH, x )
 746 #define SMC_GET_ADDRL(x)        SMC_GET_MAC_CSR( ADDRL, x )
 747 #define SMC_SET_ADDRL(x)        SMC_SET_MAC_CSR( ADDRL, x )
 748 #define SMC_GET_HASHH(x)        SMC_GET_MAC_CSR( HASHH, x )
 749 #define SMC_SET_HASHH(x)        SMC_SET_MAC_CSR( HASHH, x )
 750 #define SMC_GET_HASHL(x)        SMC_GET_MAC_CSR( HASHL, x )
 751 #define SMC_SET_HASHL(x)        SMC_SET_MAC_CSR( HASHL, x )
 752 #define SMC_GET_MII_ACC(x)      SMC_GET_MAC_CSR( MII_ACC, x )
 753 #define SMC_SET_MII_ACC(x)      SMC_SET_MAC_CSR( MII_ACC, x )
 754 #define SMC_GET_MII_DATA(x)     SMC_GET_MAC_CSR( MII_DATA, x )
 755 #define SMC_SET_MII_DATA(x)     SMC_SET_MAC_CSR( MII_DATA, x )
 756 #define SMC_GET_FLOW(x)         SMC_GET_MAC_CSR( FLOW, x )
 757 #define SMC_SET_FLOW(x)         SMC_SET_MAC_CSR( FLOW, x )
 758 #define SMC_GET_VLAN1(x)        SMC_GET_MAC_CSR( VLAN1, x )
 759 #define SMC_SET_VLAN1(x)        SMC_SET_MAC_CSR( VLAN1, x )
 760 #define SMC_GET_VLAN2(x)        SMC_GET_MAC_CSR( VLAN2, x )
 761 #define SMC_SET_VLAN2(x)        SMC_SET_MAC_CSR( VLAN2, x )
 762 #define SMC_SET_WUFF(x)         SMC_SET_MAC_CSR( WUFF, x )
 763 #define SMC_GET_WUCSR(x)        SMC_GET_MAC_CSR( WUCSR, x )
 764 #define SMC_SET_WUCSR(x)        SMC_SET_MAC_CSR( WUCSR, x )
 765
 766 /* PHY register read/write macros */
 767 #define SMC_GET_MII(a,phy,v)                                    \
 768         do {                                                    \
 769                 u32 __v;                                        \
 770                 do {                                            \
 771                         SMC_GET_MII_ACC(__v);                   \
 772                 } while ( __v & MII_ACC_MII_BUSY_ );            \
 773                 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) |       \
 774                         MII_ACC_MII_BUSY_);                     \
 775                 do {                                            \
 776                         SMC_GET_MII_ACC(__v);                   \
 777                 } while ( __v & MII_ACC_MII_BUSY_ );            \
 778                 SMC_GET_MII_DATA(v);                            \
 779         } while (0)
 780 #define SMC_SET_MII(a,phy,v)                                    \
 781         do {                                                    \
 782                 u32 __v;                                        \
 783                 do {                                            \
 784                         SMC_GET_MII_ACC(__v);                   \
 785                 } while ( __v & MII_ACC_MII_BUSY_ );            \
 786                 SMC_SET_MII_DATA(v);                            \
 787                 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) |       \
 788                         MII_ACC_MII_BUSY_        |              \
 789                         MII_ACC_MII_WRITE_  );                  \
 790                 do {                                            \
 791                         SMC_GET_MII_ACC(__v);                   \
 792                 } while ( __v & MII_ACC_MII_BUSY_ );            \
 793         } while (0)
 794 #define SMC_GET_PHY_BMCR(phy,x)         SMC_GET_MII( MII_BMCR, phy, x )
 795 #define SMC_SET_PHY_BMCR(phy,x)         SMC_SET_MII( MII_BMCR, phy, x )
 796 #define SMC_GET_PHY_BMSR(phy,x)         SMC_GET_MII( MII_BMSR, phy, x )
 797 #define SMC_GET_PHY_ID1(phy,x)          SMC_GET_MII( MII_PHYSID1, phy, x )
 798 #define SMC_GET_PHY_ID2(phy,x)          SMC_GET_MII( MII_PHYSID2, phy, x )
 799 #define SMC_GET_PHY_MII_ADV(phy,x)      SMC_GET_MII( MII_ADVERTISE, phy, x )
 800 #define SMC_SET_PHY_MII_ADV(phy,x)      SMC_SET_MII( MII_ADVERTISE, phy, x )
 801 #define SMC_GET_PHY_MII_LPA(phy,x)      SMC_GET_MII( MII_LPA, phy, x )
 802 #define SMC_SET_PHY_MII_LPA(phy,x)      SMC_SET_MII( MII_LPA, phy, x )
 803 #define SMC_GET_PHY_CTRL_STS(phy,x)     SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x )
 804 #define SMC_SET_PHY_CTRL_STS(phy,x)     SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x )
 805 #define SMC_GET_PHY_INT_SRC(phy,x)      SMC_GET_MII( PHY_INT_SRC, phy, x )
 806 #define SMC_SET_PHY_INT_SRC(phy,x)      SMC_SET_MII( PHY_INT_SRC, phy, x )
 807 #define SMC_GET_PHY_INT_MASK(phy,x)     SMC_GET_MII( PHY_INT_MASK, phy, x )
 808 #define SMC_SET_PHY_INT_MASK(phy,x)     SMC_SET_MII( PHY_INT_MASK, phy, x )
 809 #define SMC_GET_PHY_SPECIAL(phy,x)      SMC_GET_MII( PHY_SPECIAL, phy, x )
 810
 811
 812
 813 /* Misc read/write macros */
 814
 815 #ifndef SMC_GET_MAC_ADDR
 816 #define SMC_GET_MAC_ADDR(addr)                                  \
 817         do {                                                    \
 818                 unsigned int __v;                               \
 819                                                                 \
 820                 SMC_GET_MAC_CSR(ADDRL, __v);                    \
 821                 addr[0] = __v; addr[1] = __v >> 8;              \
 822                 addr[2] = __v >> 16; addr[3] = __v >> 24;       \
 823                 SMC_GET_MAC_CSR(ADDRH, __v);                    \
 824                 addr[4] = __v; addr[5] = __v >> 8;              \
 825         } while (0)
 826 #endif
 827
 828 #define SMC_SET_MAC_ADDR(addr)                                  \
 829         do {                                                    \
 830                  SMC_SET_MAC_CSR(ADDRL,                         \
 831                                  addr[0] |                      \
 832                                 (addr[1] << 8) |                \
 833                                 (addr[2] << 16) |               \
 834                                 (addr[3] << 24));               \
 835                  SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));\
 836         } while (0)
 837
 838
 839 #define SMC_WRITE_EEPROM_CMD(cmd, addr)                                 \
 840         do {                                                            \
 841                 while (SMC_GET_E2P_CMD() & MAC_CSR_CMD_CSR_BUSY_);      \
 842                 SMC_SET_MAC_CMD(MAC_CSR_CMD_R_NOT_W_ | a );             \
 843                 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);      \
 844         } while (0)
 845
 846 #endif   /* _SMC911X_H_ */