drivers/net/smc911x.h

   1 /*------------------------------------------------------------------------
   2  . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
   3  .
   4  . Copyright (C) 2005 Sensoria Corp.
   5  . Derived from the unified SMC91x driver by Nicolas Pitre
   6  .
   7  . This program is free software; you can redistribute it and/or modify
   8  . it under the terms of the GNU General Public License as published by
   9  . the Free Software Foundation; either version 2 of the License, or
  10  . (at your option) any later version.
  11  .
  12  . This program is distributed in the hope that it will be useful,
  13  . but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  . GNU General Public License for more details.
  16  .
  17  . You should have received a copy of the GNU General Public License
  18  . along with this program; if not, write to the Free Software
  19  . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  .
  21  . Information contained in this file was obtained from the LAN9118
  22  . manual from SMC.  To get a copy, if you really want one, you can find
  23  . information under www.smsc.com.
  24  .
  25  . Authors
  26  .       Dustin McIntire                 <dustin@sensoria.com>
  27  .
  28  ---------------------------------------------------------------------------*/
  29 #ifndef _SMC911X_H_
  30 #define _SMC911X_H_
  31
  32 /*
  33  * Use the DMA feature on PXA chips
  34  */
  35 #ifdef CONFIG_ARCH_PXA
  36   #define SMC_USE_PXA_DMA       1
  37   #define SMC_USE_16BIT         0
  38   #define SMC_USE_32BIT         1
  39   #define SMC_IRQ_SENSE         IRQF_TRIGGER_FALLING
  40 #elif defined(CONFIG_SH_MAGIC_PANEL_R2)
  41   #define SMC_USE_SH_DMA        0
  42   #define SMC_USE_16BIT         0
  43   #define SMC_USE_32BIT         1
  44   #define SMC_IRQ_SENSE         IRQF_TRIGGER_LOW
  45 #elif defined(CONFIG_ARCH_OMAP34XX)
  46   #define SMC_USE_16BIT         0
  47   #define SMC_USE_32BIT         1
  48   #define SMC_IRQ_SENSE         IRQF_TRIGGER_LOW
  49   #define SMC_MEM_RESERVED      1
  50 #elif defined(CONFIG_ARCH_OMAP24XX)
  51   #define SMC_USE_16BIT         0
  52   #define SMC_USE_32BIT         1
  53   #define SMC_IRQ_SENSE         IRQF_TRIGGER_LOW
  54   #define SMC_MEM_RESERVED      1
  55 #endif
  56
  57
  58 /*
  59  * Define the bus width specific IO macros
  60  */
  61
  62 #if     SMC_USE_16BIT
  63 #define SMC_inb(a, r)                    readb((a) + (r))
  64 #define SMC_inw(a, r)                    readw((a) + (r))
  65 #define SMC_inl(a, r)                    ((SMC_inw(a, r) & 0xFFFF)+(SMC_inw(a+2, r)<<16))
  66 #define SMC_outb(v, a, r)                writeb(v, (a) + (r))
  67 #define SMC_outw(v, a, r)                writew(v, (a) + (r))
  68 #define SMC_outl(v, a, r)                        \
  69         do{                                      \
  70                  writel(v & 0xFFFF, (a) + (r));  \
  71                  writel(v >> 16, (a) + (r) + 2); \
  72          } while (0)
  73 #define SMC_insl(a, r, p, l)     readsw((short*)((a) + (r)), p, l*2)
  74 #define SMC_outsl(a, r, p, l)    writesw((short*)((a) + (r)), p, l*2)
  75
  76 #elif   SMC_USE_32BIT
  77 #define SMC_inb(a, r)            readb((a) + (r))
  78 #define SMC_inw(a, r)            readw((a) + (r))
  79 #define SMC_inl(a, r)            readl((a) + (r))
  80 #define SMC_outb(v, a, r)        writeb(v, (a) + (r))
  81 #define SMC_outl(v, a, r)        writel(v, (a) + (r))
  82 #define SMC_insl(a, r, p, l)     readsl((int*)((a) + (r)), p, l)
  83 #define SMC_outsl(a, r, p, l)    writesl((int*)((a) + (r)), p, l)
  84
  85 #endif /* SMC_USE_16BIT */
  86
  87
  88
  89 #ifdef SMC_USE_PXA_DMA
  90 #define SMC_USE_DMA
  91
  92 /*
  93  * Define the request and free functions
  94  * These are unfortunately architecture specific as no generic allocation
  95  * mechanism exits
  96  */
  97 #define SMC_DMA_REQUEST(dev, handler) \
  98          pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
  99
 100 #define SMC_DMA_FREE(dev, dma) \
 101          pxa_free_dma(dma)
 102
 103 #define SMC_DMA_ACK_IRQ(dev, dma)                                       \
 104 {                                                                       \
 105         if (DCSR(dma) & DCSR_BUSERR) {                                  \
 106                 printk("%s: DMA %d bus error!\n", dev->name, dma);      \
 107         }                                                               \
 108         DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;            \
 109 }
 110
 111 /*
 112  * Use a DMA for RX and TX packets.
 113  */
 114 #include <linux/dma-mapping.h>
 115 #include <asm/dma.h>
 116 #include <asm/arch/pxa-regs.h>
 117
 118 static dma_addr_t rx_dmabuf, tx_dmabuf;
 119 static int rx_dmalen, tx_dmalen;
 120
 121 #ifdef SMC_insl
 122 #undef SMC_insl
 123 #define SMC_insl(a, r, p, l) \
 124         smc_pxa_dma_insl(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
 125
 126 static inline void
 127 smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
 128                 int reg, int dma, u_char *buf, int len)
 129 {
 130         /* 64 bit alignment is required for memory to memory DMA */
 131         if ((long)buf & 4) {
 132                 *((u32 *)buf) = SMC_inl(ioaddr, reg);
 133                 buf += 4;
 134                 len--;
 135         }
 136
 137         len *= 4;
 138         rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
 139         rx_dmalen = len;
 140         DCSR(dma) = DCSR_NODESC;
 141         DTADR(dma) = rx_dmabuf;
 142         DSADR(dma) = physaddr + reg;
 143         DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
 144                 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
 145         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 146 }
 147 #endif
 148
 149 #ifdef SMC_insw
 150 #undef SMC_insw
 151 #define SMC_insw(a, r, p, l) \
 152         smc_pxa_dma_insw(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
 153
 154 static inline void
 155 smc_pxa_dma_insw(struct device *dev, u_long ioaddr, u_long physaddr,
 156                 int reg, int dma, u_char *buf, int len)
 157 {
 158         /* 64 bit alignment is required for memory to memory DMA */
 159         while ((long)buf & 6) {
 160                 *((u16 *)buf) = SMC_inw(ioaddr, reg);
 161                 buf += 2;
 162                 len--;
 163         }
 164
 165         len *= 2;
 166         rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
 167         rx_dmalen = len;
 168         DCSR(dma) = DCSR_NODESC;
 169         DTADR(dma) = rx_dmabuf;
 170         DSADR(dma) = physaddr + reg;
 171         DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
 172                 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
 173         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 174 }
 175 #endif
 176
 177 #ifdef SMC_outsl
 178 #undef SMC_outsl
 179 #define SMC_outsl(a, r, p, l) \
 180          smc_pxa_dma_outsl(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
 181
 182 static inline void
 183 smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr,
 184                 int reg, int dma, u_char *buf, int len)
 185 {
 186         /* 64 bit alignment is required for memory to memory DMA */
 187         if ((long)buf & 4) {
 188                 SMC_outl(*((u32 *)buf), ioaddr, reg);
 189                 buf += 4;
 190                 len--;
 191         }
 192
 193         len *= 4;
 194         tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
 195         tx_dmalen = len;
 196         DCSR(dma) = DCSR_NODESC;
 197         DSADR(dma) = tx_dmabuf;
 198         DTADR(dma) = physaddr + reg;
 199         DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
 200                 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
 201         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 202 }
 203 #endif
 204
 205 #ifdef SMC_outsw
 206 #undef SMC_outsw
 207 #define SMC_outsw(a, r, p, l) \
 208         smc_pxa_dma_outsw(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
 209
 210 static inline void
 211 smc_pxa_dma_outsw(struct device *dev, u_long ioaddr, u_long physaddr,
 212                   int reg, int dma, u_char *buf, int len)
 213 {
 214         /* 64 bit alignment is required for memory to memory DMA */
 215         while ((long)buf & 6) {
 216                 SMC_outw(*((u16 *)buf), ioaddr, reg);
 217                 buf += 2;
 218                 len--;
 219         }
 220
 221         len *= 2;
 222         tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
 223         tx_dmalen = len;
 224         DCSR(dma) = DCSR_NODESC;
 225         DSADR(dma) = tx_dmabuf;
 226         DTADR(dma) = physaddr + reg;
 227         DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
 228                 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
 229         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 230 }
 231 #endif
 232
 233 #endif   /* SMC_USE_PXA_DMA */
 234
 235
 236 /* Chip Parameters and Register Definitions */
 237
 238 #define SMC911X_TX_FIFO_LOW_THRESHOLD   (1536*2)
 239
 240 #define SMC911X_IO_EXTENT        0x100
 241
 242 #define SMC911X_EEPROM_LEN       7
 243
 244 /* Below are the register offsets and bit definitions
 245  * of the Lan911x memory space
 246  */
 247 #define RX_DATA_FIFO             (0x00)
 248
 249 #define TX_DATA_FIFO             (0x20)
 250 #define TX_CMD_A_INT_ON_COMP_           (0x80000000)
 251 #define TX_CMD_A_INT_BUF_END_ALGN_      (0x03000000)
 252 #define TX_CMD_A_INT_4_BYTE_ALGN_       (0x00000000)
 253 #define TX_CMD_A_INT_16_BYTE_ALGN_      (0x01000000)
 254 #define TX_CMD_A_INT_32_BYTE_ALGN_      (0x02000000)
 255 #define TX_CMD_A_INT_DATA_OFFSET_       (0x001F0000)
 256 #define TX_CMD_A_INT_FIRST_SEG_         (0x00002000)
 257 #define TX_CMD_A_INT_LAST_SEG_          (0x00001000)
 258 #define TX_CMD_A_BUF_SIZE_              (0x000007FF)
 259 #define TX_CMD_B_PKT_TAG_               (0xFFFF0000)
 260 #define TX_CMD_B_ADD_CRC_DISABLE_       (0x00002000)
 261 #define TX_CMD_B_DISABLE_PADDING_       (0x00001000)
 262 #define TX_CMD_B_PKT_BYTE_LENGTH_       (0x000007FF)
 263
 264 #define RX_STATUS_FIFO          (0x40)
 265 #define RX_STS_PKT_LEN_                 (0x3FFF0000)
 266 #define RX_STS_ES_                      (0x00008000)
 267 #define RX_STS_BCST_                    (0x00002000)
 268 #define RX_STS_LEN_ERR_                 (0x00001000)
 269 #define RX_STS_RUNT_ERR_                (0x00000800)
 270 #define RX_STS_MCAST_                   (0x00000400)
 271 #define RX_STS_TOO_LONG_                (0x00000080)
 272 #define RX_STS_COLL_                    (0x00000040)
 273 #define RX_STS_ETH_TYPE_                (0x00000020)
 274 #define RX_STS_WDOG_TMT_                (0x00000010)
 275 #define RX_STS_MII_ERR_                 (0x00000008)
 276 #define RX_STS_DRIBBLING_               (0x00000004)
 277 #define RX_STS_CRC_ERR_                 (0x00000002)
 278 #define RX_STATUS_FIFO_PEEK     (0x44)
 279 #define TX_STATUS_FIFO          (0x48)
 280 #define TX_STS_TAG_                     (0xFFFF0000)
 281 #define TX_STS_ES_                      (0x00008000)
 282 #define TX_STS_LOC_                     (0x00000800)
 283 #define TX_STS_NO_CARR_                 (0x00000400)
 284 #define TX_STS_LATE_COLL_               (0x00000200)
 285 #define TX_STS_MANY_COLL_               (0x00000100)
 286 #define TX_STS_COLL_CNT_                (0x00000078)
 287 #define TX_STS_MANY_DEFER_              (0x00000004)
 288 #define TX_STS_UNDERRUN_                (0x00000002)
 289 #define TX_STS_DEFERRED_                (0x00000001)
 290 #define TX_STATUS_FIFO_PEEK     (0x4C)
 291 #define ID_REV                  (0x50)
 292 #define ID_REV_CHIP_ID_                 (0xFFFF0000)  /* RO */
 293 #define ID_REV_REV_ID_                  (0x0000FFFF)  /* RO */
 294
 295 #define INT_CFG                 (0x54)
 296 #define INT_CFG_INT_DEAS_               (0xFF000000)  /* R/W */
 297 #define INT_CFG_INT_DEAS_CLR_           (0x00004000)
 298 #define INT_CFG_INT_DEAS_STS_           (0x00002000)
 299 #define INT_CFG_IRQ_INT_                (0x00001000)  /* RO */
 300 #define INT_CFG_IRQ_EN_                 (0x00000100)  /* R/W */
 301 #define INT_CFG_IRQ_POL_                (0x00000010)  /* R/W Not Affected by SW Reset */
 302 #define INT_CFG_IRQ_TYPE_               (0x00000001)  /* R/W Not Affected by SW Reset */
 303
 304 #define INT_STS                 (0x58)
 305 #define INT_STS_SW_INT_                 (0x80000000)  /* R/WC */
 306 #define INT_STS_TXSTOP_INT_             (0x02000000)  /* R/WC */
 307 #define INT_STS_RXSTOP_INT_             (0x01000000)  /* R/WC */
 308 #define INT_STS_RXDFH_INT_              (0x00800000)  /* R/WC */
 309 #define INT_STS_RXDF_INT_               (0x00400000)  /* R/WC */
 310 #define INT_STS_TX_IOC_                 (0x00200000)  /* R/WC */
 311 #define INT_STS_RXD_INT_                (0x00100000)  /* R/WC */
 312 #define INT_STS_GPT_INT_                (0x00080000)  /* R/WC */
 313 #define INT_STS_PHY_INT_                (0x00040000)  /* RO */
 314 #define INT_STS_PME_INT_                (0x00020000)  /* R/WC */
 315 #define INT_STS_TXSO_                   (0x00010000)  /* R/WC */
 316 #define INT_STS_RWT_                    (0x00008000)  /* R/WC */
 317 #define INT_STS_RXE_                    (0x00004000)  /* R/WC */
 318 #define INT_STS_TXE_                    (0x00002000)  /* R/WC */
 319 //#define       INT_STS_ERX_            (0x00001000)  /* R/WC */
 320 #define INT_STS_TDFU_                   (0x00000800)  /* R/WC */
 321 #define INT_STS_TDFO_                   (0x00000400)  /* R/WC */
 322 #define INT_STS_TDFA_                   (0x00000200)  /* R/WC */
 323 #define INT_STS_TSFF_                   (0x00000100)  /* R/WC */
 324 #define INT_STS_TSFL_                   (0x00000080)  /* R/WC */
 325 //#define       INT_STS_RXDF_           (0x00000040)  /* R/WC */
 326 #define INT_STS_RDFO_                   (0x00000040)  /* R/WC */
 327 #define INT_STS_RDFL_                   (0x00000020)  /* R/WC */
 328 #define INT_STS_RSFF_                   (0x00000010)  /* R/WC */
 329 #define INT_STS_RSFL_                   (0x00000008)  /* R/WC */
 330 #define INT_STS_GPIO2_INT_              (0x00000004)  /* R/WC */
 331 #define INT_STS_GPIO1_INT_              (0x00000002)  /* R/WC */
 332 #define INT_STS_GPIO0_INT_              (0x00000001)  /* R/WC */
 333
 334 #define INT_EN                  (0x5C)
 335 #define INT_EN_SW_INT_EN_               (0x80000000)  /* R/W */
 336 #define INT_EN_TXSTOP_INT_EN_           (0x02000000)  /* R/W */
 337 #define INT_EN_RXSTOP_INT_EN_           (0x01000000)  /* R/W */
 338 #define INT_EN_RXDFH_INT_EN_            (0x00800000)  /* R/W */
 339 //#define       INT_EN_RXDF_INT_EN_             (0x00400000)  /* R/W */
 340 #define INT_EN_TIOC_INT_EN_             (0x00200000)  /* R/W */
 341 #define INT_EN_RXD_INT_EN_              (0x00100000)  /* R/W */
 342 #define INT_EN_GPT_INT_EN_              (0x00080000)  /* R/W */
 343 #define INT_EN_PHY_INT_EN_              (0x00040000)  /* R/W */
 344 #define INT_EN_PME_INT_EN_              (0x00020000)  /* R/W */
 345 #define INT_EN_TXSO_EN_                 (0x00010000)  /* R/W */
 346 #define INT_EN_RWT_EN_                  (0x00008000)  /* R/W */
 347 #define INT_EN_RXE_EN_                  (0x00004000)  /* R/W */
 348 #define INT_EN_TXE_EN_                  (0x00002000)  /* R/W */
 349 //#define       INT_EN_ERX_EN_                  (0x00001000)  /* R/W */
 350 #define INT_EN_TDFU_EN_                 (0x00000800)  /* R/W */
 351 #define INT_EN_TDFO_EN_                 (0x00000400)  /* R/W */
 352 #define INT_EN_TDFA_EN_                 (0x00000200)  /* R/W */
 353 #define INT_EN_TSFF_EN_                 (0x00000100)  /* R/W */
 354 #define INT_EN_TSFL_EN_                 (0x00000080)  /* R/W */
 355 //#define       INT_EN_RXDF_EN_                 (0x00000040)  /* R/W */
 356 #define INT_EN_RDFO_EN_                 (0x00000040)  /* R/W */
 357 #define INT_EN_RDFL_EN_                 (0x00000020)  /* R/W */
 358 #define INT_EN_RSFF_EN_                 (0x00000010)  /* R/W */
 359 #define INT_EN_RSFL_EN_                 (0x00000008)  /* R/W */
 360 #define INT_EN_GPIO2_INT_               (0x00000004)  /* R/W */
 361 #define INT_EN_GPIO1_INT_               (0x00000002)  /* R/W */
 362 #define INT_EN_GPIO0_INT_               (0x00000001)  /* R/W */
 363
 364 #define BYTE_TEST               (0x64)
 365 #define FIFO_INT                (0x68)
 366 #define FIFO_INT_TX_AVAIL_LEVEL_        (0xFF000000)  /* R/W */
 367 #define FIFO_INT_TX_STS_LEVEL_          (0x00FF0000)  /* R/W */
 368 #define FIFO_INT_RX_AVAIL_LEVEL_        (0x0000FF00)  /* R/W */
 369 #define FIFO_INT_RX_STS_LEVEL_          (0x000000FF)  /* R/W */
 370
 371 #define RX_CFG                  (0x6C)
 372 #define RX_CFG_RX_END_ALGN_             (0xC0000000)  /* R/W */
 373 #define         RX_CFG_RX_END_ALGN4_            (0x00000000)  /* R/W */
 374 #define         RX_CFG_RX_END_ALGN16_           (0x40000000)  /* R/W */
 375 #define         RX_CFG_RX_END_ALGN32_           (0x80000000)  /* R/W */
 376 #define RX_CFG_RX_DMA_CNT_              (0x0FFF0000)  /* R/W */
 377 #define RX_CFG_RX_DUMP_                 (0x00008000)  /* R/W */
 378 #define RX_CFG_RXDOFF_                  (0x00001F00)  /* R/W */
 379 //#define       RX_CFG_RXBAD_                   (0x00000001)  /* R/W */
 380
 381 #define TX_CFG                  (0x70)
 382 //#define       TX_CFG_TX_DMA_LVL_              (0xE0000000)     /* R/W */
 383 //#define       TX_CFG_TX_DMA_CNT_              (0x0FFF0000)     /* R/W Self Clearing */
 384 #define TX_CFG_TXS_DUMP_                (0x00008000)  /* Self Clearing */
 385 #define TX_CFG_TXD_DUMP_                (0x00004000)  /* Self Clearing */
 386 #define TX_CFG_TXSAO_                   (0x00000004)  /* R/W */
 387 #define TX_CFG_TX_ON_                   (0x00000002)  /* R/W */
 388 #define TX_CFG_STOP_TX_                 (0x00000001)  /* Self Clearing */
 389
 390 #define HW_CFG                  (0x74)
 391 #define HW_CFG_TTM_                     (0x00200000)  /* R/W */
 392 #define HW_CFG_SF_                      (0x00100000)  /* R/W */
 393 #define HW_CFG_TX_FIF_SZ_               (0x000F0000)  /* R/W */
 394 #define HW_CFG_TR_                      (0x00003000)  /* R/W */
 395 #define HW_CFG_PHY_CLK_SEL_             (0x00000060)  /* R/W */
 396 #define          HW_CFG_PHY_CLK_SEL_INT_PHY_    (0x00000000) /* R/W */
 397 #define          HW_CFG_PHY_CLK_SEL_EXT_PHY_    (0x00000020) /* R/W */
 398 #define          HW_CFG_PHY_CLK_SEL_CLK_DIS_    (0x00000040) /* R/W */
 399 #define HW_CFG_SMI_SEL_                 (0x00000010)  /* R/W */
 400 #define HW_CFG_EXT_PHY_DET_             (0x00000008)  /* RO */
 401 #define HW_CFG_EXT_PHY_EN_              (0x00000004)  /* R/W */
 402 #define HW_CFG_32_16_BIT_MODE_          (0x00000004)  /* RO */
 403 #define HW_CFG_SRST_TO_                 (0x00000002)  /* RO */
 404 #define HW_CFG_SRST_                    (0x00000001)  /* Self Clearing */
 405
 406 #define RX_DP_CTRL              (0x78)
 407 #define RX_DP_CTRL_RX_FFWD_             (0x80000000)  /* R/W */
 408 #define RX_DP_CTRL_FFWD_BUSY_           (0x80000000)  /* RO */
 409
 410 #define RX_FIFO_INF             (0x7C)
 411 #define  RX_FIFO_INF_RXSUSED_           (0x00FF0000)  /* RO */
 412 #define  RX_FIFO_INF_RXDUSED_           (0x0000FFFF)  /* RO */
 413
 414 #define TX_FIFO_INF             (0x80)
 415 #define TX_FIFO_INF_TSUSED_             (0x00FF0000)  /* RO */
 416 #define TX_FIFO_INF_TDFREE_             (0x0000FFFF)  /* RO */
 417
 418 #define PMT_CTRL                (0x84)
 419 #define PMT_CTRL_PM_MODE_               (0x00003000)  /* Self Clearing */
 420 #define PMT_CTRL_PHY_RST_               (0x00000400)  /* Self Clearing */
 421 #define PMT_CTRL_WOL_EN_                (0x00000200)  /* R/W */
 422 #define PMT_CTRL_ED_EN_                 (0x00000100)  /* R/W */
 423 #define PMT_CTRL_PME_TYPE_              (0x00000040)  /* R/W Not Affected by SW Reset */
 424 #define PMT_CTRL_WUPS_                  (0x00000030)  /* R/WC */
 425 #define         PMT_CTRL_WUPS_NOWAKE_           (0x00000000)  /* R/WC */
 426 #define         PMT_CTRL_WUPS_ED_               (0x00000010)  /* R/WC */
 427 #define         PMT_CTRL_WUPS_WOL_              (0x00000020)  /* R/WC */
 428 #define         PMT_CTRL_WUPS_MULTI_            (0x00000030)  /* R/WC */
 429 #define PMT_CTRL_PME_IND_               (0x00000008)  /* R/W */
 430 #define PMT_CTRL_PME_POL_               (0x00000004)  /* R/W */
 431 #define PMT_CTRL_PME_EN_                (0x00000002)  /* R/W Not Affected by SW Reset */
 432 #define PMT_CTRL_READY_                 (0x00000001)  /* RO */
 433
 434 #define GPIO_CFG                (0x88)
 435 #define GPIO_CFG_LED3_EN_               (0x40000000)  /* R/W */
 436 #define GPIO_CFG_LED2_EN_               (0x20000000)  /* R/W */
 437 #define GPIO_CFG_LED1_EN_               (0x10000000)  /* R/W */
 438 #define GPIO_CFG_GPIO2_INT_POL_         (0x04000000)  /* R/W */
 439 #define GPIO_CFG_GPIO1_INT_POL_         (0x02000000)  /* R/W */
 440 #define GPIO_CFG_GPIO0_INT_POL_         (0x01000000)  /* R/W */
 441 #define GPIO_CFG_EEPR_EN_               (0x00700000)  /* R/W */
 442 #define GPIO_CFG_GPIOBUF2_              (0x00040000)  /* R/W */
 443 #define GPIO_CFG_GPIOBUF1_              (0x00020000)  /* R/W */
 444 #define GPIO_CFG_GPIOBUF0_              (0x00010000)  /* R/W */
 445 #define GPIO_CFG_GPIODIR2_              (0x00000400)  /* R/W */
 446 #define GPIO_CFG_GPIODIR1_              (0x00000200)  /* R/W */
 447 #define GPIO_CFG_GPIODIR0_              (0x00000100)  /* R/W */
 448 #define GPIO_CFG_GPIOD4_                (0x00000010)  /* R/W */
 449 #define GPIO_CFG_GPIOD3_                (0x00000008)  /* R/W */
 450 #define GPIO_CFG_GPIOD2_                (0x00000004)  /* R/W */
 451 #define GPIO_CFG_GPIOD1_                (0x00000002)  /* R/W */
 452 #define GPIO_CFG_GPIOD0_                (0x00000001)  /* R/W */
 453
 454 #define GPT_CFG                 (0x8C)
 455 #define GPT_CFG_TIMER_EN_               (0x20000000)  /* R/W */
 456 #define GPT_CFG_GPT_LOAD_               (0x0000FFFF)  /* R/W */
 457
 458 #define GPT_CNT                 (0x90)
 459 #define GPT_CNT_GPT_CNT_                (0x0000FFFF)  /* RO */
 460
 461 #define ENDIAN                  (0x98)
 462 #define FREE_RUN                (0x9C)
 463 #define RX_DROP                 (0xA0)
 464 #define MAC_CSR_CMD             (0xA4)
 465 #define  MAC_CSR_CMD_CSR_BUSY_          (0x80000000)  /* Self Clearing */
 466 #define  MAC_CSR_CMD_R_NOT_W_           (0x40000000)  /* R/W */
 467 #define  MAC_CSR_CMD_CSR_ADDR_          (0x000000FF)  /* R/W */
 468
 469 #define MAC_CSR_DATA            (0xA8)
 470 #define AFC_CFG                 (0xAC)
 471 #define         AFC_CFG_AFC_HI_                 (0x00FF0000)  /* R/W */
 472 #define         AFC_CFG_AFC_LO_                 (0x0000FF00)  /* R/W */
 473 #define         AFC_CFG_BACK_DUR_               (0x000000F0)  /* R/W */
 474 #define         AFC_CFG_FCMULT_                 (0x00000008)  /* R/W */
 475 #define         AFC_CFG_FCBRD_                  (0x00000004)  /* R/W */
 476 #define         AFC_CFG_FCADD_                  (0x00000002)  /* R/W */
 477 #define         AFC_CFG_FCANY_                  (0x00000001)  /* R/W */
 478
 479 #define E2P_CMD                 (0xB0)
 480 #define E2P_CMD_EPC_BUSY_               (0x80000000)  /* Self Clearing */
 481 #define E2P_CMD_EPC_CMD_                        (0x70000000)  /* R/W */
 482 #define         E2P_CMD_EPC_CMD_READ_           (0x00000000)  /* R/W */
 483 #define         E2P_CMD_EPC_CMD_EWDS_           (0x10000000)  /* R/W */
 484 #define         E2P_CMD_EPC_CMD_EWEN_           (0x20000000)  /* R/W */
 485 #define         E2P_CMD_EPC_CMD_WRITE_          (0x30000000)  /* R/W */
 486 #define         E2P_CMD_EPC_CMD_WRAL_           (0x40000000)  /* R/W */
 487 #define         E2P_CMD_EPC_CMD_ERASE_          (0x50000000)  /* R/W */
 488 #define         E2P_CMD_EPC_CMD_ERAL_           (0x60000000)  /* R/W */
 489 #define         E2P_CMD_EPC_CMD_RELOAD_         (0x70000000)  /* R/W */
 490 #define E2P_CMD_EPC_TIMEOUT_            (0x00000200)  /* RO */
 491 #define E2P_CMD_MAC_ADDR_LOADED_        (0x00000100)  /* RO */
 492 #define E2P_CMD_EPC_ADDR_               (0x000000FF)  /* R/W */
 493
 494 #define E2P_DATA                (0xB4)
 495 #define E2P_DATA_EEPROM_DATA_           (0x000000FF)  /* R/W */
 496 /* end of LAN register offsets and bit definitions */
 497
 498 /*
 499  ****************************************************************************
 500  ****************************************************************************
 501  * MAC Control and Status Register (Indirect Address)
 502  * Offset (through the MAC_CSR CMD and DATA port)
 503  ****************************************************************************
 504  ****************************************************************************
 505  *
 506  */
 507 #define MAC_CR                  (0x01)  /* R/W */
 508
 509 /* MAC_CR - MAC Control Register */
 510 #define MAC_CR_RXALL_                   (0x80000000)
 511 // TODO: delete this bit? It is not described in the data sheet.
 512 #define MAC_CR_HBDIS_                   (0x10000000)
 513 #define MAC_CR_RCVOWN_                  (0x00800000)
 514 #define MAC_CR_LOOPBK_                  (0x00200000)
 515 #define MAC_CR_FDPX_                    (0x00100000)
 516 #define MAC_CR_MCPAS_                   (0x00080000)
 517 #define MAC_CR_PRMS_                    (0x00040000)
 518 #define MAC_CR_INVFILT_                 (0x00020000)
 519 #define MAC_CR_PASSBAD_                 (0x00010000)
 520 #define MAC_CR_HFILT_                   (0x00008000)
 521 #define MAC_CR_HPFILT_                  (0x00002000)
 522 #define MAC_CR_LCOLL_                   (0x00001000)
 523 #define MAC_CR_BCAST_                   (0x00000800)
 524 #define MAC_CR_DISRTY_                  (0x00000400)
 525 #define MAC_CR_PADSTR_                  (0x00000100)
 526 #define MAC_CR_BOLMT_MASK_              (0x000000C0)
 527 #define MAC_CR_DFCHK_                   (0x00000020)
 528 #define MAC_CR_TXEN_                    (0x00000008)
 529 #define MAC_CR_RXEN_                    (0x00000004)
 530
 531 #define ADDRH                   (0x02)    /* R/W mask 0x0000FFFFUL */
 532 #define ADDRL                   (0x03)    /* R/W mask 0xFFFFFFFFUL */
 533 #define HASHH                   (0x04)    /* R/W */
 534 #define HASHL                   (0x05)    /* R/W */
 535
 536 #define MII_ACC                 (0x06)    /* R/W */
 537 #define MII_ACC_PHY_ADDR_               (0x0000F800)
 538 #define MII_ACC_MIIRINDA_               (0x000007C0)
 539 #define MII_ACC_MII_WRITE_              (0x00000002)
 540 #define MII_ACC_MII_BUSY_               (0x00000001)
 541
 542 #define MII_DATA                (0x07)    /* R/W mask 0x0000FFFFUL */
 543
 544 #define FLOW                    (0x08)    /* R/W */
 545 #define FLOW_FCPT_                      (0xFFFF0000)
 546 #define FLOW_FCPASS_                    (0x00000004)
 547 #define FLOW_FCEN_                      (0x00000002)
 548 #define FLOW_FCBSY_                     (0x00000001)
 549
 550 #define VLAN1                   (0x09)    /* R/W mask 0x0000FFFFUL */
 551 #define VLAN1_VTI1_                     (0x0000ffff)
 552
 553 #define VLAN2                   (0x0A)    /* R/W mask 0x0000FFFFUL */
 554 #define VLAN2_VTI2_                     (0x0000ffff)
 555
 556 #define WUFF                    (0x0B)    /* WO */
 557
 558 #define WUCSR                   (0x0C)    /* R/W */
 559 #define WUCSR_GUE_                      (0x00000200)
 560 #define WUCSR_WUFR_                     (0x00000040)
 561 #define WUCSR_MPR_                      (0x00000020)
 562 #define WUCSR_WAKE_EN_                  (0x00000004)
 563 #define WUCSR_MPEN_                     (0x00000002)
 564
 565 /*
 566  ****************************************************************************
 567  * Chip Specific MII Defines
 568  ****************************************************************************
 569  *
 570  * Phy register offsets and bit definitions
 571  *
 572  */
 573
 574 #define PHY_MODE_CTRL_STS       ((u32)17)       /* Mode Control/Status Register */
 575 //#define MODE_CTRL_STS_FASTRIP_          ((u16)0x4000)
 576 #define MODE_CTRL_STS_EDPWRDOWN_         ((u16)0x2000)
 577 //#define MODE_CTRL_STS_LOWSQEN_           ((u16)0x0800)
 578 //#define MODE_CTRL_STS_MDPREBP_           ((u16)0x0400)
 579 //#define MODE_CTRL_STS_FARLOOPBACK_  ((u16)0x0200)
 580 //#define MODE_CTRL_STS_FASTEST_           ((u16)0x0100)
 581 //#define MODE_CTRL_STS_REFCLKEN_          ((u16)0x0010)
 582 //#define MODE_CTRL_STS_PHYADBP_           ((u16)0x0008)
 583 //#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
 584 #define MODE_CTRL_STS_ENERGYON_         ((u16)0x0002)
 585
 586 #define PHY_INT_SRC                     ((u32)29)
 587 #define PHY_INT_SRC_ENERGY_ON_                  ((u16)0x0080)
 588 #define PHY_INT_SRC_ANEG_COMP_                  ((u16)0x0040)
 589 #define PHY_INT_SRC_REMOTE_FAULT_               ((u16)0x0020)
 590 #define PHY_INT_SRC_LINK_DOWN_                  ((u16)0x0010)
 591 #define PHY_INT_SRC_ANEG_LP_ACK_                ((u16)0x0008)
 592 #define PHY_INT_SRC_PAR_DET_FAULT_              ((u16)0x0004)
 593 #define PHY_INT_SRC_ANEG_PGRX_                  ((u16)0x0002)
 594
 595 #define PHY_INT_MASK                    ((u32)30)
 596 #define PHY_INT_MASK_ENERGY_ON_                 ((u16)0x0080)
 597 #define PHY_INT_MASK_ANEG_COMP_                 ((u16)0x0040)
 598 #define PHY_INT_MASK_REMOTE_FAULT_              ((u16)0x0020)
 599 #define PHY_INT_MASK_LINK_DOWN_                 ((u16)0x0010)
 600 #define PHY_INT_MASK_ANEG_LP_ACK_               ((u16)0x0008)
 601 #define PHY_INT_MASK_PAR_DET_FAULT_             ((u16)0x0004)
 602 #define PHY_INT_MASK_ANEG_PGRX_                 ((u16)0x0002)
 603
 604 #define PHY_SPECIAL                     ((u32)31)
 605 #define PHY_SPECIAL_ANEG_DONE_                  ((u16)0x1000)
 606 #define PHY_SPECIAL_RES_                        ((u16)0x0040)
 607 #define PHY_SPECIAL_RES_MASK_                   ((u16)0x0FE1)
 608 #define PHY_SPECIAL_SPD_                        ((u16)0x001C)
 609 #define PHY_SPECIAL_SPD_10HALF_                 ((u16)0x0004)
 610 #define PHY_SPECIAL_SPD_10FULL_                 ((u16)0x0014)
 611 #define PHY_SPECIAL_SPD_100HALF_                ((u16)0x0008)
 612 #define PHY_SPECIAL_SPD_100FULL_                ((u16)0x0018)
 613
 614 #define LAN911X_INTERNAL_PHY_ID         (0x0007C000)
 615
 616 /* Chip ID values */
 617 #define CHIP_9115       0x115
 618 #define CHIP_9116       0x116
 619 #define CHIP_9117       0x117
 620 #define CHIP_9118       0x118
 621
 622 struct chip_id {
 623         u16 id;
 624         char *name;
 625 };
 626
 627 static const struct chip_id chip_ids[] =  {
 628         { CHIP_9115, "LAN9115" },
 629         { CHIP_9116, "LAN9116" },
 630         { CHIP_9117, "LAN9117" },
 631         { CHIP_9118, "LAN9118" },
 632         { 0, NULL },
 633 };
 634
 635 #define IS_REV_A(x)     ((x & 0xFFFF)==0)
 636
 637 /*
 638  * Macros to abstract register access according to the data bus
 639  * capabilities.  Please use those and not the in/out primitives.
 640  */
 641 /* FIFO read/write macros */
 642 #define SMC_PUSH_DATA(p, l)     SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 )
 643 #define SMC_PULL_DATA(p, l)     SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 )
 644 #define SMC_SET_TX_FIFO(x)      SMC_outl( x, ioaddr, TX_DATA_FIFO )
 645 #define SMC_GET_RX_FIFO()       SMC_inl( ioaddr, RX_DATA_FIFO )
 646
 647
 648 /* I/O mapped register read/write macros */
 649 #define SMC_GET_TX_STS_FIFO()           SMC_inl( ioaddr, TX_STATUS_FIFO )
 650 #define SMC_GET_RX_STS_FIFO()           SMC_inl( ioaddr, RX_STATUS_FIFO )
 651 #define SMC_GET_RX_STS_FIFO_PEEK()      SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK )
 652 #define SMC_GET_PN()                    (SMC_inl( ioaddr, ID_REV ) >> 16)
 653 #define SMC_GET_REV()                   (SMC_inl( ioaddr, ID_REV ) & 0xFFFF)
 654 #define SMC_GET_IRQ_CFG()               SMC_inl( ioaddr, INT_CFG )
 655 #define SMC_SET_IRQ_CFG(x)              SMC_outl( x, ioaddr, INT_CFG )
 656 #define SMC_GET_INT()                   SMC_inl( ioaddr, INT_STS )
 657 #define SMC_ACK_INT(x)                  SMC_outl( x, ioaddr, INT_STS )
 658 #define SMC_GET_INT_EN()                SMC_inl( ioaddr, INT_EN )
 659 #define SMC_SET_INT_EN(x)               SMC_outl( x, ioaddr, INT_EN )
 660 #define SMC_GET_BYTE_TEST()             SMC_inl( ioaddr, BYTE_TEST )
 661 #define SMC_SET_BYTE_TEST(x)            SMC_outl( x, ioaddr, BYTE_TEST )
 662 #define SMC_GET_FIFO_INT()              SMC_inl( ioaddr, FIFO_INT )
 663 #define SMC_SET_FIFO_INT(x)             SMC_outl( x, ioaddr, FIFO_INT )
 664 #define SMC_SET_FIFO_TDA(x)                                     \
 665         do {                                                    \
 666                 unsigned long __flags;                          \
 667                 int __mask;                                     \
 668                 local_irq_save(__flags);                        \
 669                 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<24);      \
 670                 SMC_SET_FIFO_INT( __mask | (x)<<24 );           \
 671                 local_irq_restore(__flags);                     \
 672         } while (0)
 673 #define SMC_SET_FIFO_TSL(x)                                     \
 674         do {                                                    \
 675                 unsigned long __flags;                          \
 676                 int __mask;                                     \
 677                 local_irq_save(__flags);                        \
 678                 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<16);      \
 679                 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); \
 680                 local_irq_restore(__flags);                     \
 681         } while (0)
 682 #define SMC_SET_FIFO_RSA(x)                                     \
 683         do {                                                    \
 684                 unsigned long __flags;                          \
 685                 int __mask;                                     \
 686                 local_irq_save(__flags);                        \
 687                 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<8);       \
 688                 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8));  \
 689                 local_irq_restore(__flags);                     \
 690         } while (0)
 691 #define SMC_SET_FIFO_RSL(x)                                     \
 692         do {                                                    \
 693                 unsigned long __flags;                          \
 694                 int __mask;                                     \
 695                 local_irq_save(__flags);                        \
 696                 __mask = SMC_GET_FIFO_INT() & ~0xFF;            \
 697                 SMC_SET_FIFO_INT( __mask | ((x) & 0xFF));       \
 698                 local_irq_restore(__flags);                     \
 699         } while (0)
 700 #define SMC_GET_RX_CFG()                SMC_inl( ioaddr, RX_CFG )
 701 #define SMC_SET_RX_CFG(x)               SMC_outl( x, ioaddr, RX_CFG )
 702 #define SMC_GET_TX_CFG()                SMC_inl( ioaddr, TX_CFG )
 703 #define SMC_SET_TX_CFG(x)               SMC_outl( x, ioaddr, TX_CFG )
 704 #define SMC_GET_HW_CFG()                SMC_inl( ioaddr, HW_CFG )
 705 #define SMC_SET_HW_CFG(x)               SMC_outl( x, ioaddr, HW_CFG )
 706 #define SMC_GET_RX_DP_CTRL()            SMC_inl( ioaddr, RX_DP_CTRL )
 707 #define SMC_SET_RX_DP_CTRL(x)           SMC_outl( x, ioaddr, RX_DP_CTRL )
 708 #define SMC_GET_PMT_CTRL()              SMC_inl( ioaddr, PMT_CTRL )
 709 #define SMC_SET_PMT_CTRL(x)             SMC_outl( x, ioaddr, PMT_CTRL )
 710 #define SMC_GET_GPIO_CFG()              SMC_inl( ioaddr, GPIO_CFG )
 711 #define SMC_SET_GPIO_CFG(x)             SMC_outl( x, ioaddr, GPIO_CFG )
 712 #define SMC_GET_RX_FIFO_INF()           SMC_inl( ioaddr, RX_FIFO_INF )
 713 #define SMC_SET_RX_FIFO_INF(x)          SMC_outl( x, ioaddr, RX_FIFO_INF )
 714 #define SMC_GET_TX_FIFO_INF()           SMC_inl( ioaddr, TX_FIFO_INF )
 715 #define SMC_SET_TX_FIFO_INF(x)          SMC_outl( x, ioaddr, TX_FIFO_INF )
 716 #define SMC_GET_GPT_CFG()               SMC_inl( ioaddr, GPT_CFG )
 717 #define SMC_SET_GPT_CFG(x)              SMC_outl( x, ioaddr, GPT_CFG )
 718 #define SMC_GET_RX_DROP()               SMC_inl( ioaddr, RX_DROP )
 719 #define SMC_SET_RX_DROP(x)              SMC_outl( x, ioaddr, RX_DROP )
 720 #define SMC_GET_MAC_CMD()               SMC_inl( ioaddr, MAC_CSR_CMD )
 721 #define SMC_SET_MAC_CMD(x)              SMC_outl( x, ioaddr, MAC_CSR_CMD )
 722 #define SMC_GET_MAC_DATA()              SMC_inl( ioaddr, MAC_CSR_DATA )
 723 #define SMC_SET_MAC_DATA(x)             SMC_outl( x, ioaddr, MAC_CSR_DATA )
 724 #define SMC_GET_AFC_CFG()               SMC_inl( ioaddr, AFC_CFG )
 725 #define SMC_SET_AFC_CFG(x)              SMC_outl( x, ioaddr, AFC_CFG )
 726 #define SMC_GET_E2P_CMD()               SMC_inl( ioaddr, E2P_CMD )
 727 #define SMC_SET_E2P_CMD(x)              SMC_outl( x, ioaddr, E2P_CMD )
 728 #define SMC_GET_E2P_DATA()              SMC_inl( ioaddr, E2P_DATA )
 729 #define SMC_SET_E2P_DATA(x)             SMC_outl( x, ioaddr, E2P_DATA )
 730
 731 /* MAC register read/write macros */
 732 #define SMC_GET_MAC_CSR(a,v)                                            \
 733         do {                                                            \
 734                 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);      \
 735                 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ |                 \
 736                         MAC_CSR_CMD_R_NOT_W_ | (a) );                   \
 737                 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);      \
 738                 v = SMC_GET_MAC_DATA();                                 \
 739         } while (0)
 740 #define SMC_SET_MAC_CSR(a,v)                                            \
 741         do {                                                            \
 742                 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);      \
 743                 SMC_SET_MAC_DATA(v);                                    \
 744                 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) );          \
 745                 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);      \
 746         } while (0)
 747 #define SMC_GET_MAC_CR(x)       SMC_GET_MAC_CSR( MAC_CR, x )
 748 #define SMC_SET_MAC_CR(x)       SMC_SET_MAC_CSR( MAC_CR, x )
 749 #define SMC_GET_ADDRH(x)        SMC_GET_MAC_CSR( ADDRH, x )
 750 #define SMC_SET_ADDRH(x)        SMC_SET_MAC_CSR( ADDRH, x )
 751 #define SMC_GET_ADDRL(x)        SMC_GET_MAC_CSR( ADDRL, x )
 752 #define SMC_SET_ADDRL(x)        SMC_SET_MAC_CSR( ADDRL, x )
 753 #define SMC_GET_HASHH(x)        SMC_GET_MAC_CSR( HASHH, x )
 754 #define SMC_SET_HASHH(x)        SMC_SET_MAC_CSR( HASHH, x )
 755 #define SMC_GET_HASHL(x)        SMC_GET_MAC_CSR( HASHL, x )
 756 #define SMC_SET_HASHL(x)        SMC_SET_MAC_CSR( HASHL, x )
 757 #define SMC_GET_MII_ACC(x)      SMC_GET_MAC_CSR( MII_ACC, x )
 758 #define SMC_SET_MII_ACC(x)      SMC_SET_MAC_CSR( MII_ACC, x )
 759 #define SMC_GET_MII_DATA(x)     SMC_GET_MAC_CSR( MII_DATA, x )
 760 #define SMC_SET_MII_DATA(x)     SMC_SET_MAC_CSR( MII_DATA, x )
 761 #define SMC_GET_FLOW(x)         SMC_GET_MAC_CSR( FLOW, x )
 762 #define SMC_SET_FLOW(x)         SMC_SET_MAC_CSR( FLOW, x )
 763 #define SMC_GET_VLAN1(x)        SMC_GET_MAC_CSR( VLAN1, x )
 764 #define SMC_SET_VLAN1(x)        SMC_SET_MAC_CSR( VLAN1, x )
 765 #define SMC_GET_VLAN2(x)        SMC_GET_MAC_CSR( VLAN2, x )
 766 #define SMC_SET_VLAN2(x)        SMC_SET_MAC_CSR( VLAN2, x )
 767 #define SMC_SET_WUFF(x)         SMC_SET_MAC_CSR( WUFF, x )
 768 #define SMC_GET_WUCSR(x)        SMC_GET_MAC_CSR( WUCSR, x )
 769 #define SMC_SET_WUCSR(x)        SMC_SET_MAC_CSR( WUCSR, x )
 770
 771 /* PHY register read/write macros */
 772 #define SMC_GET_MII(a,phy,v)                                    \
 773         do {                                                    \
 774                 u32 __v;                                        \
 775                 do {                                            \
 776                         SMC_GET_MII_ACC(__v);                   \
 777                 } while ( __v & MII_ACC_MII_BUSY_ );            \
 778                 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) |       \
 779                         MII_ACC_MII_BUSY_);                     \
 780                 do {                                            \
 781                         SMC_GET_MII_ACC(__v);                   \
 782                 } while ( __v & MII_ACC_MII_BUSY_ );            \
 783                 SMC_GET_MII_DATA(v);                            \
 784         } while (0)
 785 #define SMC_SET_MII(a,phy,v)                                    \
 786         do {                                                    \
 787                 u32 __v;                                        \
 788                 do {                                            \
 789                         SMC_GET_MII_ACC(__v);                   \
 790                 } while ( __v & MII_ACC_MII_BUSY_ );            \
 791                 SMC_SET_MII_DATA(v);                            \
 792                 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) |       \
 793                         MII_ACC_MII_BUSY_        |              \
 794                         MII_ACC_MII_WRITE_  );                  \
 795                 do {                                            \
 796                         SMC_GET_MII_ACC(__v);                   \
 797                 } while ( __v & MII_ACC_MII_BUSY_ );            \
 798         } while (0)
 799 #define SMC_GET_PHY_BMCR(phy,x)         SMC_GET_MII( MII_BMCR, phy, x )
 800 #define SMC_SET_PHY_BMCR(phy,x)         SMC_SET_MII( MII_BMCR, phy, x )
 801 #define SMC_GET_PHY_BMSR(phy,x)         SMC_GET_MII( MII_BMSR, phy, x )
 802 #define SMC_GET_PHY_ID1(phy,x)          SMC_GET_MII( MII_PHYSID1, phy, x )
 803 #define SMC_GET_PHY_ID2(phy,x)          SMC_GET_MII( MII_PHYSID2, phy, x )
 804 #define SMC_GET_PHY_MII_ADV(phy,x)      SMC_GET_MII( MII_ADVERTISE, phy, x )
 805 #define SMC_SET_PHY_MII_ADV(phy,x)      SMC_SET_MII( MII_ADVERTISE, phy, x )
 806 #define SMC_GET_PHY_MII_LPA(phy,x)      SMC_GET_MII( MII_LPA, phy, x )
 807 #define SMC_SET_PHY_MII_LPA(phy,x)      SMC_SET_MII( MII_LPA, phy, x )
 808 #define SMC_GET_PHY_CTRL_STS(phy,x)     SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x )
 809 #define SMC_SET_PHY_CTRL_STS(phy,x)     SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x )
 810 #define SMC_GET_PHY_INT_SRC(phy,x)      SMC_GET_MII( PHY_INT_SRC, phy, x )
 811 #define SMC_SET_PHY_INT_SRC(phy,x)      SMC_SET_MII( PHY_INT_SRC, phy, x )
 812 #define SMC_GET_PHY_INT_MASK(phy,x)     SMC_GET_MII( PHY_INT_MASK, phy, x )
 813 #define SMC_SET_PHY_INT_MASK(phy,x)     SMC_SET_MII( PHY_INT_MASK, phy, x )
 814 #define SMC_GET_PHY_SPECIAL(phy,x)      SMC_GET_MII( PHY_SPECIAL, phy, x )
 815
 816
 817
 818 /* Misc read/write macros */
 819
 820 #ifndef SMC_GET_MAC_ADDR
 821 #define SMC_GET_MAC_ADDR(addr)                                  \
 822         do {                                                    \
 823                 unsigned int __v;                               \
 824                                                                 \
 825                 SMC_GET_MAC_CSR(ADDRL, __v);                    \
 826                 addr[0] = __v; addr[1] = __v >> 8;              \
 827                 addr[2] = __v >> 16; addr[3] = __v >> 24;       \
 828                 SMC_GET_MAC_CSR(ADDRH, __v);                    \
 829                 addr[4] = __v; addr[5] = __v >> 8;              \
 830         } while (0)
 831 #endif
 832
 833 #define SMC_SET_MAC_ADDR(addr)                                  \
 834         do {                                                    \
 835                  SMC_SET_MAC_CSR(ADDRL,                         \
 836                                  addr[0] |                      \
 837                                 (addr[1] << 8) |                \
 838                                 (addr[2] << 16) |               \
 839                                 (addr[3] << 24));               \
 840                  SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));\
 841         } while (0)
 842
 843
 844 #define SMC_WRITE_EEPROM_CMD(cmd, addr)                                 \
 845         do {                                                            \
 846                 while (SMC_GET_E2P_CMD() & MAC_CSR_CMD_CSR_BUSY_);      \
 847                 SMC_SET_MAC_CMD(MAC_CSR_CMD_R_NOT_W_ | a );             \
 848                 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);      \
 849         } while (0)
 850
 851 #endif   /* _SMC911X_H_ */