drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  * Copyright (c) 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through platform_device.  Structures which
  29  *  define the configuration needed by the board are defined in a
  30  *  board structure in arch/ppc/platforms (though I do not
  31  *  discount the possibility that other architectures could one
  32  *  day be supported.
  33  *
  34  *  The Gianfar Ethernet Controller uses a ring of buffer
  35  *  descriptors.  The beginning is indicated by a register
  36  *  pointing to the physical address of the start of the ring.
  37  *  The end is determined by a "wrap" bit being set in the
  38  *  last descriptor of the ring.
  39  *
  40  *  When a packet is received, the RXF bit in the
  41  *  IEVENT register is set, triggering an interrupt when the
  42  *  corresponding bit in the IMASK register is also set (if
  43  *  interrupt coalescing is active, then the interrupt may not
  44  *  happen immediately, but will wait until either a set number
  45  *  of frames or amount of time have passed).  In NAPI, the
  46  *  interrupt handler will signal there is work to be done, and
  47  *  exit. This method will start at the last known empty
  48  *  descriptor, and process every subsequent descriptor until there
  49  *  are none left with data (NAPI will stop after a set number of
  50  *  packets to give time to other tasks, but will eventually
  51  *  process all the packets).  The data arrives inside a
  52  *  pre-allocated skb, and so after the skb is passed up to the
  53  *  stack, a new skb must be allocated, and the address field in
  54  *  the buffer descriptor must be updated to indicate this new
  55  *  skb.
  56  *
  57  *  When the kernel requests that a packet be transmitted, the
  58  *  driver starts where it left off last time, and points the
  59  *  descriptor at the buffer which was passed in.  The driver
  60  *  then informs the DMA engine that there are packets ready to
  61  *  be transmitted.  Once the controller is finished transmitting
  62  *  the packet, an interrupt may be triggered (under the same
  63  *  conditions as for reception, but depending on the TXF bit).
  64  *  The driver then cleans up the buffer.
  65  */
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/platform_device.h>
  82 #include <linux/ip.h>
  83 #include <linux/tcp.h>
  84 #include <linux/udp.h>
  85 #include <linux/in.h>
  86
  87 #include <asm/io.h>
  88 #include <asm/irq.h>
  89 #include <asm/uaccess.h>
  90 #include <linux/module.h>
  91 #include <linux/dma-mapping.h>
  92 #include <linux/crc32.h>
  93 #include <linux/mii.h>
  94 #include <linux/phy.h>
  95
  96 #include "gianfar.h"
  97 #include "gianfar_mii.h"
  98
  99 #define TX_TIMEOUT      (1*HZ)
 100 #undef BRIEF_GFAR_ERRORS
 101 #undef VERBOSE_GFAR_ERRORS
 102
 103 const char gfar_driver_name[] = "Gianfar Ethernet";
 104 const char gfar_driver_version[] = "1.3";
 105
 106 static int gfar_enet_open(struct net_device *dev);
 107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 108 static void gfar_reset_task(struct work_struct *work);
 109 static void gfar_timeout(struct net_device *dev);
 110 static int gfar_close(struct net_device *dev);
 111 struct sk_buff *gfar_new_skb(struct net_device *dev);
 112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
 113                 struct sk_buff *skb);
 114 static int gfar_set_mac_address(struct net_device *dev);
 115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 116 static irqreturn_t gfar_error(int irq, void *dev_id);
 117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 119 static void adjust_link(struct net_device *dev);
 120 static void init_registers(struct net_device *dev);
 121 static int init_phy(struct net_device *dev);
 122 static int gfar_probe(struct platform_device *pdev);
 123 static int gfar_remove(struct platform_device *pdev);
 124 static void free_skb_resources(struct gfar_private *priv);
 125 static void gfar_set_multi(struct net_device *dev);
 126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 127 static void gfar_configure_serdes(struct net_device *dev);
 128 static int gfar_poll(struct napi_struct *napi, int budget);
 129 #ifdef CONFIG_NET_POLL_CONTROLLER
 130 static void gfar_netpoll(struct net_device *dev);
 131 #endif
 132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 133 static int gfar_clean_tx_ring(struct net_device *dev);
 134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
 135 static void gfar_vlan_rx_register(struct net_device *netdev,
 136                                 struct vlan_group *grp);
 137 void gfar_halt(struct net_device *dev);
 138 static void gfar_halt_nodisable(struct net_device *dev);
 139 void gfar_start(struct net_device *dev);
 140 static void gfar_clear_exact_match(struct net_device *dev);
 141 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 142
 143 extern const struct ethtool_ops gfar_ethtool_ops;
 144
 145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 147 MODULE_LICENSE("GPL");
 148
 149 /* Returns 1 if incoming frames use an FCB */
 150 static inline int gfar_uses_fcb(struct gfar_private *priv)
 151 {
 152         return (priv->vlan_enable || priv->rx_csum_enable);
 153 }
 154
 155 /* Set up the ethernet device structure, private data,
 156  * and anything else we need before we start */
 157 static int gfar_probe(struct platform_device *pdev)
 158 {
 159         u32 tempval;
 160         struct net_device *dev = NULL;
 161         struct gfar_private *priv = NULL;
 162         struct gianfar_platform_data *einfo;
 163         struct resource *r;
 164         int err = 0, irq;
 165         DECLARE_MAC_BUF(mac);
 166
 167         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
 168
 169         if (NULL == einfo) {
 170                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
 171                        pdev->id);
 172
 173                 return -ENODEV;
 174         }
 175
 176         /* Create an ethernet device instance */
 177         dev = alloc_etherdev(sizeof (*priv));
 178
 179         if (NULL == dev)
 180                 return -ENOMEM;
 181
 182         priv = netdev_priv(dev);
 183         priv->dev = dev;
 184
 185         /* Set the info in the priv to the current info */
 186         priv->einfo = einfo;
 187
 188         /* fill out IRQ fields */
 189         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 190                 irq = platform_get_irq_byname(pdev, "tx");
 191                 if (irq < 0)
 192                         goto regs_fail;
 193                 priv->interruptTransmit = irq;
 194
 195                 irq = platform_get_irq_byname(pdev, "rx");
 196                 if (irq < 0)
 197                         goto regs_fail;
 198                 priv->interruptReceive = irq;
 199
 200                 irq = platform_get_irq_byname(pdev, "error");
 201                 if (irq < 0)
 202                         goto regs_fail;
 203                 priv->interruptError = irq;
 204         } else {
 205                 irq = platform_get_irq(pdev, 0);
 206                 if (irq < 0)
 207                         goto regs_fail;
 208                 priv->interruptTransmit = irq;
 209         }
 210
 211         /* get a pointer to the register memory */
 212         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 213         priv->regs = ioremap(r->start, sizeof (struct gfar));
 214
 215         if (NULL == priv->regs) {
 216                 err = -ENOMEM;
 217                 goto regs_fail;
 218         }
 219
 220         spin_lock_init(&priv->txlock);
 221         spin_lock_init(&priv->rxlock);
 222         spin_lock_init(&priv->bflock);
 223         INIT_WORK(&priv->reset_task, gfar_reset_task);
 224
 225         platform_set_drvdata(pdev, dev);
 226
 227         /* Stop the DMA engine now, in case it was running before */
 228         /* (The firmware could have used it, and left it running). */
 229         /* To do this, we write Graceful Receive Stop and Graceful */
 230         /* Transmit Stop, and then wait until the corresponding bits */
 231         /* in IEVENT indicate the stops have completed. */
 232         tempval = gfar_read(&priv->regs->dmactrl);
 233         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 234         gfar_write(&priv->regs->dmactrl, tempval);
 235
 236         tempval = gfar_read(&priv->regs->dmactrl);
 237         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 238         gfar_write(&priv->regs->dmactrl, tempval);
 239
 240         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
 241                 cpu_relax();
 242
 243         /* Reset MAC layer */
 244         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 245
 246         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 247         gfar_write(&priv->regs->maccfg1, tempval);
 248
 249         /* Initialize MACCFG2. */
 250         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 251
 252         /* Initialize ECNTRL */
 253         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 254
 255         /* Copy the station address into the dev structure, */
 256         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
 257
 258         /* Set the dev->base_addr to the gfar reg region */
 259         dev->base_addr = (unsigned long) (priv->regs);
 260
 261         SET_NETDEV_DEV(dev, &pdev->dev);
 262
 263         /* Fill in the dev structure */
 264         dev->open = gfar_enet_open;
 265         dev->hard_start_xmit = gfar_start_xmit;
 266         dev->tx_timeout = gfar_timeout;
 267         dev->watchdog_timeo = TX_TIMEOUT;
 268         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
 269 #ifdef CONFIG_NET_POLL_CONTROLLER
 270         dev->poll_controller = gfar_netpoll;
 271 #endif
 272         dev->stop = gfar_close;
 273         dev->change_mtu = gfar_change_mtu;
 274         dev->mtu = 1500;
 275         dev->set_multicast_list = gfar_set_multi;
 276
 277         dev->ethtool_ops = &gfar_ethtool_ops;
 278
 279         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 280                 priv->rx_csum_enable = 1;
 281                 dev->features |= NETIF_F_IP_CSUM;
 282         } else
 283                 priv->rx_csum_enable = 0;
 284
 285         priv->vlgrp = NULL;
 286
 287         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
 288                 dev->vlan_rx_register = gfar_vlan_rx_register;
 289
 290                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 291
 292                 priv->vlan_enable = 1;
 293         }
 294
 295         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 296                 priv->extended_hash = 1;
 297                 priv->hash_width = 9;
 298
 299                 priv->hash_regs[0] = &priv->regs->igaddr0;
 300                 priv->hash_regs[1] = &priv->regs->igaddr1;
 301                 priv->hash_regs[2] = &priv->regs->igaddr2;
 302                 priv->hash_regs[3] = &priv->regs->igaddr3;
 303                 priv->hash_regs[4] = &priv->regs->igaddr4;
 304                 priv->hash_regs[5] = &priv->regs->igaddr5;
 305                 priv->hash_regs[6] = &priv->regs->igaddr6;
 306                 priv->hash_regs[7] = &priv->regs->igaddr7;
 307                 priv->hash_regs[8] = &priv->regs->gaddr0;
 308                 priv->hash_regs[9] = &priv->regs->gaddr1;
 309                 priv->hash_regs[10] = &priv->regs->gaddr2;
 310                 priv->hash_regs[11] = &priv->regs->gaddr3;
 311                 priv->hash_regs[12] = &priv->regs->gaddr4;
 312                 priv->hash_regs[13] = &priv->regs->gaddr5;
 313                 priv->hash_regs[14] = &priv->regs->gaddr6;
 314                 priv->hash_regs[15] = &priv->regs->gaddr7;
 315
 316         } else {
 317                 priv->extended_hash = 0;
 318                 priv->hash_width = 8;
 319
 320                 priv->hash_regs[0] = &priv->regs->gaddr0;
 321                 priv->hash_regs[1] = &priv->regs->gaddr1;
 322                 priv->hash_regs[2] = &priv->regs->gaddr2;
 323                 priv->hash_regs[3] = &priv->regs->gaddr3;
 324                 priv->hash_regs[4] = &priv->regs->gaddr4;
 325                 priv->hash_regs[5] = &priv->regs->gaddr5;
 326                 priv->hash_regs[6] = &priv->regs->gaddr6;
 327                 priv->hash_regs[7] = &priv->regs->gaddr7;
 328         }
 329
 330         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 331                 priv->padding = DEFAULT_PADDING;
 332         else
 333                 priv->padding = 0;
 334
 335         if (dev->features & NETIF_F_IP_CSUM)
 336                 dev->hard_header_len += GMAC_FCB_LEN;
 337
 338         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 339         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 340         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 341
 342         priv->txcoalescing = DEFAULT_TX_COALESCE;
 343         priv->txcount = DEFAULT_TXCOUNT;
 344         priv->txtime = DEFAULT_TXTIME;
 345         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 346         priv->rxcount = DEFAULT_RXCOUNT;
 347         priv->rxtime = DEFAULT_RXTIME;
 348
 349         /* Enable most messages by default */
 350         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 351
 352         /* Carrier starts down, phylib will bring it up */
 353         netif_carrier_off(dev);
 354
 355         err = register_netdev(dev);
 356
 357         if (err) {
 358                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 359                                 dev->name);
 360                 goto register_fail;
 361         }
 362
 363         /* Create all the sysfs files */
 364         gfar_init_sysfs(dev);
 365
 366         /* Print out the device info */
 367         printk(KERN_INFO DEVICE_NAME "%s\n",
 368                dev->name, print_mac(mac, dev->dev_addr));
 369
 370         /* Even more device info helps when determining which kernel */
 371         /* provided which set of benchmarks. */
 372         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 373         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 374                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 375
 376         return 0;
 377
 378 register_fail:
 379         iounmap(priv->regs);
 380 regs_fail:
 381         free_netdev(dev);
 382         return err;
 383 }
 384
 385 static int gfar_remove(struct platform_device *pdev)
 386 {
 387         struct net_device *dev = platform_get_drvdata(pdev);
 388         struct gfar_private *priv = netdev_priv(dev);
 389
 390         platform_set_drvdata(pdev, NULL);
 391
 392         iounmap(priv->regs);
 393         free_netdev(dev);
 394
 395         return 0;
 396 }
 397
 398 #ifdef CONFIG_PM
 399 static int gfar_suspend(struct platform_device *pdev, pm_message_t state)
 400 {
 401         struct net_device *dev = platform_get_drvdata(pdev);
 402         struct gfar_private *priv = netdev_priv(dev);
 403         unsigned long flags;
 404         u32 tempval;
 405
 406         int magic_packet = priv->wol_en &&
 407                 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 408
 409         netif_device_detach(dev);
 410
 411         if (netif_running(dev)) {
 412                 spin_lock_irqsave(&priv->txlock, flags);
 413                 spin_lock(&priv->rxlock);
 414
 415                 gfar_halt_nodisable(dev);
 416
 417                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
 418                 tempval = gfar_read(&priv->regs->maccfg1);
 419
 420                 tempval &= ~MACCFG1_TX_EN;
 421
 422                 if (!magic_packet)
 423                         tempval &= ~MACCFG1_RX_EN;
 424
 425                 gfar_write(&priv->regs->maccfg1, tempval);
 426
 427                 spin_unlock(&priv->rxlock);
 428                 spin_unlock_irqrestore(&priv->txlock, flags);
 429
 430                 napi_disable(&priv->napi);
 431
 432                 if (magic_packet) {
 433                         /* Enable interrupt on Magic Packet */
 434                         gfar_write(&priv->regs->imask, IMASK_MAG);
 435
 436                         /* Enable Magic Packet mode */
 437                         tempval = gfar_read(&priv->regs->maccfg2);
 438                         tempval |= MACCFG2_MPEN;
 439                         gfar_write(&priv->regs->maccfg2, tempval);
 440                 } else {
 441                         phy_stop(priv->phydev);
 442                 }
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int gfar_resume(struct platform_device *pdev)
 449 {
 450         struct net_device *dev = platform_get_drvdata(pdev);
 451         struct gfar_private *priv = netdev_priv(dev);
 452         unsigned long flags;
 453         u32 tempval;
 454         int magic_packet = priv->wol_en &&
 455                 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 456
 457         if (!netif_running(dev)) {
 458                 netif_device_attach(dev);
 459                 return 0;
 460         }
 461
 462         if (!magic_packet && priv->phydev)
 463                 phy_start(priv->phydev);
 464
 465         /* Disable Magic Packet mode, in case something
 466          * else woke us up.
 467          */
 468
 469         spin_lock_irqsave(&priv->txlock, flags);
 470         spin_lock(&priv->rxlock);
 471
 472         tempval = gfar_read(&priv->regs->maccfg2);
 473         tempval &= ~MACCFG2_MPEN;
 474         gfar_write(&priv->regs->maccfg2, tempval);
 475
 476         gfar_start(dev);
 477
 478         spin_unlock(&priv->rxlock);
 479         spin_unlock_irqrestore(&priv->txlock, flags);
 480
 481         netif_device_attach(dev);
 482
 483         napi_enable(&priv->napi);
 484
 485         return 0;
 486 }
 487 #else
 488 #define gfar_suspend NULL
 489 #define gfar_resume NULL
 490 #endif
 491
 492 /* Reads the controller's registers to determine what interface
 493  * connects it to the PHY.
 494  */
 495 static phy_interface_t gfar_get_interface(struct net_device *dev)
 496 {
 497         struct gfar_private *priv = netdev_priv(dev);
 498         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 499
 500         if (ecntrl & ECNTRL_SGMII_MODE)
 501                 return PHY_INTERFACE_MODE_SGMII;
 502
 503         if (ecntrl & ECNTRL_TBI_MODE) {
 504                 if (ecntrl & ECNTRL_REDUCED_MODE)
 505                         return PHY_INTERFACE_MODE_RTBI;
 506                 else
 507                         return PHY_INTERFACE_MODE_TBI;
 508         }
 509
 510         if (ecntrl & ECNTRL_REDUCED_MODE) {
 511                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 512                         return PHY_INTERFACE_MODE_RMII;
 513                 else {
 514                         phy_interface_t interface = priv->einfo->interface;
 515
 516                         /*
 517                          * This isn't autodetected right now, so it must
 518                          * be set by the device tree or platform code.
 519                          */
 520                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 521                                 return PHY_INTERFACE_MODE_RGMII_ID;
 522
 523                         return PHY_INTERFACE_MODE_RGMII;
 524                 }
 525         }
 526
 527         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 528                 return PHY_INTERFACE_MODE_GMII;
 529
 530         return PHY_INTERFACE_MODE_MII;
 531 }
 532
 533
 534 /* Initializes driver's PHY state, and attaches to the PHY.
 535  * Returns 0 on success.
 536  */
 537 static int init_phy(struct net_device *dev)
 538 {
 539         struct gfar_private *priv = netdev_priv(dev);
 540         uint gigabit_support =
 541                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 542                 SUPPORTED_1000baseT_Full : 0;
 543         struct phy_device *phydev;
 544         char phy_id[BUS_ID_SIZE];
 545         phy_interface_t interface;
 546
 547         priv->oldlink = 0;
 548         priv->oldspeed = 0;
 549         priv->oldduplex = -1;
 550
 551         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
 552
 553         interface = gfar_get_interface(dev);
 554
 555         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
 556
 557         if (interface == PHY_INTERFACE_MODE_SGMII)
 558                 gfar_configure_serdes(dev);
 559
 560         if (IS_ERR(phydev)) {
 561                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 562                 return PTR_ERR(phydev);
 563         }
 564
 565         /* Remove any features not supported by the controller */
 566         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 567         phydev->advertising = phydev->supported;
 568
 569         priv->phydev = phydev;
 570
 571         return 0;
 572 }
 573
 574 /*
 575  * Initialize TBI PHY interface for communicating with the
 576  * SERDES lynx PHY on the chip.  We communicate with this PHY
 577  * through the MDIO bus on each controller, treating it as a
 578  * "normal" PHY at the address found in the TBIPA register.  We assume
 579  * that the TBIPA register is valid.  Either the MDIO bus code will set
 580  * it to a value that doesn't conflict with other PHYs on the bus, or the
 581  * value doesn't matter, as there are no other PHYs on the bus.
 582  */
 583 static void gfar_configure_serdes(struct net_device *dev)
 584 {
 585         struct gfar_private *priv = netdev_priv(dev);
 586         struct gfar_mii __iomem *regs =
 587                         (void __iomem *)&priv->regs->gfar_mii_regs;
 588         int tbipa = gfar_read(&priv->regs->tbipa);
 589         struct mii_bus *bus = gfar_get_miibus(priv);
 590
 591         if (bus)
 592                 mutex_lock(&bus->mdio_lock);
 593
 594         /* Single clk mode, mii mode off(for serdes communication) */
 595         gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT);
 596
 597         gfar_local_mdio_write(regs, tbipa, MII_ADVERTISE,
 598                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 599                         ADVERTISE_1000XPSE_ASYM);
 600
 601         gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE |
 602                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 603
 604         if (bus)
 605                 mutex_unlock(&bus->mdio_lock);
 606 }
 607
 608 static void init_registers(struct net_device *dev)
 609 {
 610         struct gfar_private *priv = netdev_priv(dev);
 611
 612         /* Clear IEVENT */
 613         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 614
 615         /* Initialize IMASK */
 616         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 617
 618         /* Init hash registers to zero */
 619         gfar_write(&priv->regs->igaddr0, 0);
 620         gfar_write(&priv->regs->igaddr1, 0);
 621         gfar_write(&priv->regs->igaddr2, 0);
 622         gfar_write(&priv->regs->igaddr3, 0);
 623         gfar_write(&priv->regs->igaddr4, 0);
 624         gfar_write(&priv->regs->igaddr5, 0);
 625         gfar_write(&priv->regs->igaddr6, 0);
 626         gfar_write(&priv->regs->igaddr7, 0);
 627
 628         gfar_write(&priv->regs->gaddr0, 0);
 629         gfar_write(&priv->regs->gaddr1, 0);
 630         gfar_write(&priv->regs->gaddr2, 0);
 631         gfar_write(&priv->regs->gaddr3, 0);
 632         gfar_write(&priv->regs->gaddr4, 0);
 633         gfar_write(&priv->regs->gaddr5, 0);
 634         gfar_write(&priv->regs->gaddr6, 0);
 635         gfar_write(&priv->regs->gaddr7, 0);
 636
 637         /* Zero out the rmon mib registers if it has them */
 638         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 639                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 640
 641                 /* Mask off the CAM interrupts */
 642                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 643                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 644         }
 645
 646         /* Initialize the max receive buffer length */
 647         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 648
 649         /* Initialize the Minimum Frame Length Register */
 650         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 651 }
 652
 653
 654 /* Halt the receive and transmit queues */
 655 static void gfar_halt_nodisable(struct net_device *dev)
 656 {
 657         struct gfar_private *priv = netdev_priv(dev);
 658         struct gfar __iomem *regs = priv->regs;
 659         u32 tempval;
 660
 661         /* Mask all interrupts */
 662         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 663
 664         /* Clear all interrupts */
 665         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 666
 667         /* Stop the DMA, and wait for it to stop */
 668         tempval = gfar_read(&priv->regs->dmactrl);
 669         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 670             != (DMACTRL_GRS | DMACTRL_GTS)) {
 671                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 672                 gfar_write(&priv->regs->dmactrl, tempval);
 673
 674                 while (!(gfar_read(&priv->regs->ievent) &
 675                          (IEVENT_GRSC | IEVENT_GTSC)))
 676                         cpu_relax();
 677         }
 678 }
 679
 680 /* Halt the receive and transmit queues */
 681 void gfar_halt(struct net_device *dev)
 682 {
 683         struct gfar_private *priv = netdev_priv(dev);
 684         struct gfar __iomem *regs = priv->regs;
 685         u32 tempval;
 686
 687         gfar_halt_nodisable(dev);
 688
 689         /* Disable Rx and Tx */
 690         tempval = gfar_read(&regs->maccfg1);
 691         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 692         gfar_write(&regs->maccfg1, tempval);
 693 }
 694
 695 void stop_gfar(struct net_device *dev)
 696 {
 697         struct gfar_private *priv = netdev_priv(dev);
 698         struct gfar __iomem *regs = priv->regs;
 699         unsigned long flags;
 700
 701         phy_stop(priv->phydev);
 702
 703         /* Lock it down */
 704         spin_lock_irqsave(&priv->txlock, flags);
 705         spin_lock(&priv->rxlock);
 706
 707         gfar_halt(dev);
 708
 709         spin_unlock(&priv->rxlock);
 710         spin_unlock_irqrestore(&priv->txlock, flags);
 711
 712         /* Free the IRQs */
 713         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 714                 free_irq(priv->interruptError, dev);
 715                 free_irq(priv->interruptTransmit, dev);
 716                 free_irq(priv->interruptReceive, dev);
 717         } else {
 718                 free_irq(priv->interruptTransmit, dev);
 719         }
 720
 721         free_skb_resources(priv);
 722
 723         dma_free_coherent(&dev->dev,
 724                         sizeof(struct txbd8)*priv->tx_ring_size
 725                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 726                         priv->tx_bd_base,
 727                         gfar_read(&regs->tbase0));
 728 }
 729
 730 /* If there are any tx skbs or rx skbs still around, free them.
 731  * Then free tx_skbuff and rx_skbuff */
 732 static void free_skb_resources(struct gfar_private *priv)
 733 {
 734         struct rxbd8 *rxbdp;
 735         struct txbd8 *txbdp;
 736         int i;
 737
 738         /* Go through all the buffer descriptors and free their data buffers */
 739         txbdp = priv->tx_bd_base;
 740
 741         for (i = 0; i < priv->tx_ring_size; i++) {
 742
 743                 if (priv->tx_skbuff[i]) {
 744                         dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
 745                                         txbdp->length,
 746                                         DMA_TO_DEVICE);
 747                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 748                         priv->tx_skbuff[i] = NULL;
 749                 }
 750
 751                 txbdp++;
 752         }
 753
 754         kfree(priv->tx_skbuff);
 755
 756         rxbdp = priv->rx_bd_base;
 757
 758         /* rx_skbuff is not guaranteed to be allocated, so only
 759          * free it and its contents if it is allocated */
 760         if(priv->rx_skbuff != NULL) {
 761                 for (i = 0; i < priv->rx_ring_size; i++) {
 762                         if (priv->rx_skbuff[i]) {
 763                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
 764                                                 priv->rx_buffer_size,
 765                                                 DMA_FROM_DEVICE);
 766
 767                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 768                                 priv->rx_skbuff[i] = NULL;
 769                         }
 770
 771                         rxbdp->status = 0;
 772                         rxbdp->length = 0;
 773                         rxbdp->bufPtr = 0;
 774
 775                         rxbdp++;
 776                 }
 777
 778                 kfree(priv->rx_skbuff);
 779         }
 780 }
 781
 782 void gfar_start(struct net_device *dev)
 783 {
 784         struct gfar_private *priv = netdev_priv(dev);
 785         struct gfar __iomem *regs = priv->regs;
 786         u32 tempval;
 787
 788         /* Enable Rx and Tx in MACCFG1 */
 789         tempval = gfar_read(&regs->maccfg1);
 790         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 791         gfar_write(&regs->maccfg1, tempval);
 792
 793         /* Initialize DMACTRL to have WWR and WOP */
 794         tempval = gfar_read(&priv->regs->dmactrl);
 795         tempval |= DMACTRL_INIT_SETTINGS;
 796         gfar_write(&priv->regs->dmactrl, tempval);
 797
 798         /* Make sure we aren't stopped */
 799         tempval = gfar_read(&priv->regs->dmactrl);
 800         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 801         gfar_write(&priv->regs->dmactrl, tempval);
 802
 803         /* Clear THLT/RHLT, so that the DMA starts polling now */
 804         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 805         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 806
 807         /* Unmask the interrupts we look for */
 808         gfar_write(&regs->imask, IMASK_DEFAULT);
 809 }
 810
 811 /* Bring the controller up and running */
 812 int startup_gfar(struct net_device *dev)
 813 {
 814         struct txbd8 *txbdp;
 815         struct rxbd8 *rxbdp;
 816         dma_addr_t addr = 0;
 817         unsigned long vaddr;
 818         int i;
 819         struct gfar_private *priv = netdev_priv(dev);
 820         struct gfar __iomem *regs = priv->regs;
 821         int err = 0;
 822         u32 rctrl = 0;
 823         u32 attrs = 0;
 824
 825         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 826
 827         /* Allocate memory for the buffer descriptors */
 828         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
 829                         sizeof (struct txbd8) * priv->tx_ring_size +
 830                         sizeof (struct rxbd8) * priv->rx_ring_size,
 831                         &addr, GFP_KERNEL);
 832
 833         if (vaddr == 0) {
 834                 if (netif_msg_ifup(priv))
 835                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
 836                                         dev->name);
 837                 return -ENOMEM;
 838         }
 839
 840         priv->tx_bd_base = (struct txbd8 *) vaddr;
 841
 842         /* enet DMA only understands physical addresses */
 843         gfar_write(&regs->tbase0, addr);
 844
 845         /* Start the rx descriptor ring where the tx ring leaves off */
 846         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
 847         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
 848         priv->rx_bd_base = (struct rxbd8 *) vaddr;
 849         gfar_write(&regs->rbase0, addr);
 850
 851         /* Setup the skbuff rings */
 852         priv->tx_skbuff =
 853             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 854                                         priv->tx_ring_size, GFP_KERNEL);
 855
 856         if (NULL == priv->tx_skbuff) {
 857                 if (netif_msg_ifup(priv))
 858                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
 859                                         dev->name);
 860                 err = -ENOMEM;
 861                 goto tx_skb_fail;
 862         }
 863
 864         for (i = 0; i < priv->tx_ring_size; i++)
 865                 priv->tx_skbuff[i] = NULL;
 866
 867         priv->rx_skbuff =
 868             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 869                                         priv->rx_ring_size, GFP_KERNEL);
 870
 871         if (NULL == priv->rx_skbuff) {
 872                 if (netif_msg_ifup(priv))
 873                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
 874                                         dev->name);
 875                 err = -ENOMEM;
 876                 goto rx_skb_fail;
 877         }
 878
 879         for (i = 0; i < priv->rx_ring_size; i++)
 880                 priv->rx_skbuff[i] = NULL;
 881
 882         /* Initialize some variables in our dev structure */
 883         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
 884         priv->cur_rx = priv->rx_bd_base;
 885         priv->skb_curtx = priv->skb_dirtytx = 0;
 886         priv->skb_currx = 0;
 887
 888         /* Initialize Transmit Descriptor Ring */
 889         txbdp = priv->tx_bd_base;
 890         for (i = 0; i < priv->tx_ring_size; i++) {
 891                 txbdp->status = 0;
 892                 txbdp->length = 0;
 893                 txbdp->bufPtr = 0;
 894                 txbdp++;
 895         }
 896
 897         /* Set the last descriptor in the ring to indicate wrap */
 898         txbdp--;
 899         txbdp->status |= TXBD_WRAP;
 900
 901         rxbdp = priv->rx_bd_base;
 902         for (i = 0; i < priv->rx_ring_size; i++) {
 903                 struct sk_buff *skb;
 904
 905                 skb = gfar_new_skb(dev);
 906
 907                 if (!skb) {
 908                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
 909                                         dev->name);
 910
 911                         goto err_rxalloc_fail;
 912                 }
 913
 914                 priv->rx_skbuff[i] = skb;
 915
 916                 gfar_new_rxbdp(dev, rxbdp, skb);
 917
 918                 rxbdp++;
 919         }
 920
 921         /* Set the last descriptor in the ring to wrap */
 922         rxbdp--;
 923         rxbdp->status |= RXBD_WRAP;
 924
 925         /* If the device has multiple interrupts, register for
 926          * them.  Otherwise, only register for the one */
 927         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 928                 /* Install our interrupt handlers for Error,
 929                  * Transmit, and Receive */
 930                 if (request_irq(priv->interruptError, gfar_error,
 931                                 0, "enet_error", dev) < 0) {
 932                         if (netif_msg_intr(priv))
 933                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 934                                         dev->name, priv->interruptError);
 935
 936                         err = -1;
 937                         goto err_irq_fail;
 938                 }
 939
 940                 if (request_irq(priv->interruptTransmit, gfar_transmit,
 941                                 0, "enet_tx", dev) < 0) {
 942                         if (netif_msg_intr(priv))
 943                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 944                                         dev->name, priv->interruptTransmit);
 945
 946                         err = -1;
 947
 948                         goto tx_irq_fail;
 949                 }
 950
 951                 if (request_irq(priv->interruptReceive, gfar_receive,
 952                                 0, "enet_rx", dev) < 0) {
 953                         if (netif_msg_intr(priv))
 954                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
 955                                                 dev->name, priv->interruptReceive);
 956
 957                         err = -1;
 958                         goto rx_irq_fail;
 959                 }
 960         } else {
 961                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
 962                                 0, "gfar_interrupt", dev) < 0) {
 963                         if (netif_msg_intr(priv))
 964                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 965                                         dev->name, priv->interruptError);
 966
 967                         err = -1;
 968                         goto err_irq_fail;
 969                 }
 970         }
 971
 972         phy_start(priv->phydev);
 973
 974         /* Configure the coalescing support */
 975         if (priv->txcoalescing)
 976                 gfar_write(&regs->txic,
 977                            mk_ic_value(priv->txcount, priv->txtime));
 978         else
 979                 gfar_write(&regs->txic, 0);
 980
 981         if (priv->rxcoalescing)
 982                 gfar_write(&regs->rxic,
 983                            mk_ic_value(priv->rxcount, priv->rxtime));
 984         else
 985                 gfar_write(&regs->rxic, 0);
 986
 987         if (priv->rx_csum_enable)
 988                 rctrl |= RCTRL_CHECKSUMMING;
 989
 990         if (priv->extended_hash) {
 991                 rctrl |= RCTRL_EXTHASH;
 992
 993                 gfar_clear_exact_match(dev);
 994                 rctrl |= RCTRL_EMEN;
 995         }
 996
 997         if (priv->vlan_enable)
 998                 rctrl |= RCTRL_VLAN;
 999
1000         if (priv->padding) {
1001                 rctrl &= ~RCTRL_PAL_MASK;
1002                 rctrl |= RCTRL_PADDING(priv->padding);
1003         }
1004
1005         /* Init rctrl based on our settings */
1006         gfar_write(&priv->regs->rctrl, rctrl);
1007
1008         if (dev->features & NETIF_F_IP_CSUM)
1009                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1010
1011         /* Set the extraction length and index */
1012         attrs = ATTRELI_EL(priv->rx_stash_size) |
1013                 ATTRELI_EI(priv->rx_stash_index);
1014
1015         gfar_write(&priv->regs->attreli, attrs);
1016
1017         /* Start with defaults, and add stashing or locking
1018          * depending on the approprate variables */
1019         attrs = ATTR_INIT_SETTINGS;
1020
1021         if (priv->bd_stash_en)
1022                 attrs |= ATTR_BDSTASH;
1023
1024         if (priv->rx_stash_size != 0)
1025                 attrs |= ATTR_BUFSTASH;
1026
1027         gfar_write(&priv->regs->attr, attrs);
1028
1029         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1030         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1031         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1032
1033         /* Start the controller */
1034         gfar_start(dev);
1035
1036         return 0;
1037
1038 rx_irq_fail:
1039         free_irq(priv->interruptTransmit, dev);
1040 tx_irq_fail:
1041         free_irq(priv->interruptError, dev);
1042 err_irq_fail:
1043 err_rxalloc_fail:
1044 rx_skb_fail:
1045         free_skb_resources(priv);
1046 tx_skb_fail:
1047         dma_free_coherent(&dev->dev,
1048                         sizeof(struct txbd8)*priv->tx_ring_size
1049                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1050                         priv->tx_bd_base,
1051                         gfar_read(&regs->tbase0));
1052
1053         return err;
1054 }
1055
1056 /* Called when something needs to use the ethernet device */
1057 /* Returns 0 for success. */
1058 static int gfar_enet_open(struct net_device *dev)
1059 {
1060         struct gfar_private *priv = netdev_priv(dev);
1061         int err;
1062
1063         napi_enable(&priv->napi);
1064
1065         /* Initialize a bunch of registers */
1066         init_registers(dev);
1067
1068         gfar_set_mac_address(dev);
1069
1070         err = init_phy(dev);
1071
1072         if(err) {
1073                 napi_disable(&priv->napi);
1074                 return err;
1075         }
1076
1077         err = startup_gfar(dev);
1078         if (err) {
1079                 napi_disable(&priv->napi);
1080                 return err;
1081         }
1082
1083         netif_start_queue(dev);
1084
1085         return err;
1086 }
1087
1088 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
1089 {
1090         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1091
1092         memset(fcb, 0, GMAC_FCB_LEN);
1093
1094         return fcb;
1095 }
1096
1097 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1098 {
1099         u8 flags = 0;
1100
1101         /* If we're here, it's a IP packet with a TCP or UDP
1102          * payload.  We set it to checksum, using a pseudo-header
1103          * we provide
1104          */
1105         flags = TXFCB_DEFAULT;
1106
1107         /* Tell the controller what the protocol is */
1108         /* And provide the already calculated phcs */
1109         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1110                 flags |= TXFCB_UDP;
1111                 fcb->phcs = udp_hdr(skb)->check;
1112         } else
1113                 fcb->phcs = tcp_hdr(skb)->check;
1114
1115         /* l3os is the distance between the start of the
1116          * frame (skb->data) and the start of the IP hdr.
1117          * l4os is the distance between the start of the
1118          * l3 hdr and the l4 hdr */
1119         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1120         fcb->l4os = skb_network_header_len(skb);
1121
1122         fcb->flags = flags;
1123 }
1124
1125 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1126 {
1127         fcb->flags |= TXFCB_VLN;
1128         fcb->vlctl = vlan_tx_tag_get(skb);
1129 }
1130
1131 /* This is called by the kernel when a frame is ready for transmission. */
1132 /* It is pointed to by the dev->hard_start_xmit function pointer */
1133 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1134 {
1135         struct gfar_private *priv = netdev_priv(dev);
1136         struct txfcb *fcb = NULL;
1137         struct txbd8 *txbdp;
1138         u16 status;
1139         unsigned long flags;
1140
1141         /* Update transmit stats */
1142         dev->stats.tx_bytes += skb->len;
1143
1144         /* Lock priv now */
1145         spin_lock_irqsave(&priv->txlock, flags);
1146
1147         /* Point at the first free tx descriptor */
1148         txbdp = priv->cur_tx;
1149
1150         /* Clear all but the WRAP status flags */
1151         status = txbdp->status & TXBD_WRAP;
1152
1153         /* Set up checksumming */
1154         if (likely((dev->features & NETIF_F_IP_CSUM)
1155                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1156                 fcb = gfar_add_fcb(skb, txbdp);
1157                 status |= TXBD_TOE;
1158                 gfar_tx_checksum(skb, fcb);
1159         }
1160
1161         if (priv->vlan_enable &&
1162                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1163                 if (unlikely(NULL == fcb)) {
1164                         fcb = gfar_add_fcb(skb, txbdp);
1165                         status |= TXBD_TOE;
1166                 }
1167
1168                 gfar_tx_vlan(skb, fcb);
1169         }
1170
1171         /* Set buffer length and pointer */
1172         txbdp->length = skb->len;
1173         txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1174                         skb->len, DMA_TO_DEVICE);
1175
1176         /* Save the skb pointer so we can free it later */
1177         priv->tx_skbuff[priv->skb_curtx] = skb;
1178
1179         /* Update the current skb pointer (wrapping if this was the last) */
1180         priv->skb_curtx =
1181             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1182
1183         /* Flag the BD as interrupt-causing */
1184         status |= TXBD_INTERRUPT;
1185
1186         /* Flag the BD as ready to go, last in frame, and  */
1187         /* in need of CRC */
1188         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1189
1190         dev->trans_start = jiffies;
1191
1192         /* The powerpc-specific eieio() is used, as wmb() has too strong
1193          * semantics (it requires synchronization between cacheable and
1194          * uncacheable mappings, which eieio doesn't provide and which we
1195          * don't need), thus requiring a more expensive sync instruction.  At
1196          * some point, the set of architecture-independent barrier functions
1197          * should be expanded to include weaker barriers.
1198          */
1199
1200         eieio();
1201         txbdp->status = status;
1202
1203         /* If this was the last BD in the ring, the next one */
1204         /* is at the beginning of the ring */
1205         if (txbdp->status & TXBD_WRAP)
1206                 txbdp = priv->tx_bd_base;
1207         else
1208                 txbdp++;
1209
1210         /* If the next BD still needs to be cleaned up, then the bds
1211            are full.  We need to tell the kernel to stop sending us stuff. */
1212         if (txbdp == priv->dirty_tx) {
1213                 netif_stop_queue(dev);
1214
1215                 dev->stats.tx_fifo_errors++;
1216         }
1217
1218         /* Update the current txbd to the next one */
1219         priv->cur_tx = txbdp;
1220
1221         /* Tell the DMA to go go go */
1222         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1223
1224         /* Unlock priv */
1225         spin_unlock_irqrestore(&priv->txlock, flags);
1226
1227         return 0;
1228 }
1229
1230 /* Stops the kernel queue, and halts the controller */
1231 static int gfar_close(struct net_device *dev)
1232 {
1233         struct gfar_private *priv = netdev_priv(dev);
1234
1235         napi_disable(&priv->napi);
1236
1237         cancel_work_sync(&priv->reset_task);
1238         stop_gfar(dev);
1239
1240         /* Disconnect from the PHY */
1241         phy_disconnect(priv->phydev);
1242         priv->phydev = NULL;
1243
1244         netif_stop_queue(dev);
1245
1246         return 0;
1247 }
1248
1249 /* Changes the mac address if the controller is not running. */
1250 static int gfar_set_mac_address(struct net_device *dev)
1251 {
1252         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1253
1254         return 0;
1255 }
1256
1257
1258 /* Enables and disables VLAN insertion/extraction */
1259 static void gfar_vlan_rx_register(struct net_device *dev,
1260                 struct vlan_group *grp)
1261 {
1262         struct gfar_private *priv = netdev_priv(dev);
1263         unsigned long flags;
1264         u32 tempval;
1265
1266         spin_lock_irqsave(&priv->rxlock, flags);
1267
1268         priv->vlgrp = grp;
1269
1270         if (grp) {
1271                 /* Enable VLAN tag insertion */
1272                 tempval = gfar_read(&priv->regs->tctrl);
1273                 tempval |= TCTRL_VLINS;
1274
1275                 gfar_write(&priv->regs->tctrl, tempval);
1276
1277                 /* Enable VLAN tag extraction */
1278                 tempval = gfar_read(&priv->regs->rctrl);
1279                 tempval |= RCTRL_VLEX;
1280                 gfar_write(&priv->regs->rctrl, tempval);
1281         } else {
1282                 /* Disable VLAN tag insertion */
1283                 tempval = gfar_read(&priv->regs->tctrl);
1284                 tempval &= ~TCTRL_VLINS;
1285                 gfar_write(&priv->regs->tctrl, tempval);
1286
1287                 /* Disable VLAN tag extraction */
1288                 tempval = gfar_read(&priv->regs->rctrl);
1289                 tempval &= ~RCTRL_VLEX;
1290                 gfar_write(&priv->regs->rctrl, tempval);
1291         }
1292
1293         spin_unlock_irqrestore(&priv->rxlock, flags);
1294 }
1295
1296 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1297 {
1298         int tempsize, tempval;
1299         struct gfar_private *priv = netdev_priv(dev);
1300         int oldsize = priv->rx_buffer_size;
1301         int frame_size = new_mtu + ETH_HLEN;
1302
1303         if (priv->vlan_enable)
1304                 frame_size += VLAN_HLEN;
1305
1306         if (gfar_uses_fcb(priv))
1307                 frame_size += GMAC_FCB_LEN;
1308
1309         frame_size += priv->padding;
1310
1311         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1312                 if (netif_msg_drv(priv))
1313                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1314                                         dev->name);
1315                 return -EINVAL;
1316         }
1317
1318         tempsize =
1319             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1320             INCREMENTAL_BUFFER_SIZE;
1321
1322         /* Only stop and start the controller if it isn't already
1323          * stopped, and we changed something */
1324         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1325                 stop_gfar(dev);
1326
1327         priv->rx_buffer_size = tempsize;
1328
1329         dev->mtu = new_mtu;
1330
1331         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1332         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1333
1334         /* If the mtu is larger than the max size for standard
1335          * ethernet frames (ie, a jumbo frame), then set maccfg2
1336          * to allow huge frames, and to check the length */
1337         tempval = gfar_read(&priv->regs->maccfg2);
1338
1339         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1340                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1341         else
1342                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1343
1344         gfar_write(&priv->regs->maccfg2, tempval);
1345
1346         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1347                 startup_gfar(dev);
1348
1349         return 0;
1350 }
1351
1352 /* gfar_reset_task gets scheduled when a packet has not been
1353  * transmitted after a set amount of time.
1354  * For now, assume that clearing out all the structures, and
1355  * starting over will fix the problem.
1356  */
1357 static void gfar_reset_task(struct work_struct *work)
1358 {
1359         struct gfar_private *priv = container_of(work, struct gfar_private,
1360                         reset_task);
1361         struct net_device *dev = priv->dev;
1362
1363         if (dev->flags & IFF_UP) {
1364                 stop_gfar(dev);
1365                 startup_gfar(dev);
1366         }
1367
1368         netif_tx_schedule_all(dev);
1369 }
1370
1371 static void gfar_timeout(struct net_device *dev)
1372 {
1373         struct gfar_private *priv = netdev_priv(dev);
1374
1375         dev->stats.tx_errors++;
1376         schedule_work(&priv->reset_task);
1377 }
1378
1379 /* Interrupt Handler for Transmit complete */
1380 static int gfar_clean_tx_ring(struct net_device *dev)
1381 {
1382         struct txbd8 *bdp;
1383         struct gfar_private *priv = netdev_priv(dev);
1384         int howmany = 0;
1385
1386         bdp = priv->dirty_tx;
1387         while ((bdp->status & TXBD_READY) == 0) {
1388                 /* If dirty_tx and cur_tx are the same, then either the */
1389                 /* ring is empty or full now (it could only be full in the beginning, */
1390                 /* obviously).  If it is empty, we are done. */
1391                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1392                         break;
1393
1394                 howmany++;
1395
1396                 /* Deferred means some collisions occurred during transmit, */
1397                 /* but we eventually sent the packet. */
1398                 if (bdp->status & TXBD_DEF)
1399                         dev->stats.collisions++;
1400
1401                 /* Free the sk buffer associated with this TxBD */
1402                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1403
1404                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1405                 priv->skb_dirtytx =
1406                     (priv->skb_dirtytx +
1407                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1408
1409                 /* Clean BD length for empty detection */
1410                 bdp->length = 0;
1411
1412                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1413                 if (bdp->status & TXBD_WRAP)
1414                         bdp = priv->tx_bd_base;
1415                 else
1416                         bdp++;
1417
1418                 /* Move dirty_tx to be the next bd */
1419                 priv->dirty_tx = bdp;
1420
1421                 /* We freed a buffer, so now we can restart transmission */
1422                 if (netif_queue_stopped(dev))
1423                         netif_wake_queue(dev);
1424         } /* while ((bdp->status & TXBD_READY) == 0) */
1425
1426         dev->stats.tx_packets += howmany;
1427
1428         return howmany;
1429 }
1430
1431 /* Interrupt Handler for Transmit complete */
1432 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1433 {
1434         struct net_device *dev = (struct net_device *) dev_id;
1435         struct gfar_private *priv = netdev_priv(dev);
1436
1437         /* Clear IEVENT */
1438         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1439
1440         /* Lock priv */
1441         spin_lock(&priv->txlock);
1442
1443         gfar_clean_tx_ring(dev);
1444
1445         /* If we are coalescing the interrupts, reset the timer */
1446         /* Otherwise, clear it */
1447         if (likely(priv->txcoalescing)) {
1448                 gfar_write(&priv->regs->txic, 0);
1449                 gfar_write(&priv->regs->txic,
1450                            mk_ic_value(priv->txcount, priv->txtime));
1451         }
1452
1453         spin_unlock(&priv->txlock);
1454
1455         return IRQ_HANDLED;
1456 }
1457
1458 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1459                 struct sk_buff *skb)
1460 {
1461         struct gfar_private *priv = netdev_priv(dev);
1462         u32 * status_len = (u32 *)bdp;
1463         u16 flags;
1464
1465         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1466                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1467
1468         flags = RXBD_EMPTY | RXBD_INTERRUPT;
1469
1470         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1471                 flags |= RXBD_WRAP;
1472
1473         eieio();
1474
1475         *status_len = (u32)flags << 16;
1476 }
1477
1478
1479 struct sk_buff * gfar_new_skb(struct net_device *dev)
1480 {
1481         unsigned int alignamount;
1482         struct gfar_private *priv = netdev_priv(dev);
1483         struct sk_buff *skb = NULL;
1484
1485         /* We have to allocate the skb, so keep trying till we succeed */
1486         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1487
1488         if (!skb)
1489                 return NULL;
1490
1491         alignamount = RXBUF_ALIGNMENT -
1492                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1493
1494         /* We need the data buffer to be aligned properly.  We will reserve
1495          * as many bytes as needed to align the data properly
1496          */
1497         skb_reserve(skb, alignamount);
1498
1499         return skb;
1500 }
1501
1502 static inline void count_errors(unsigned short status, struct net_device *dev)
1503 {
1504         struct gfar_private *priv = netdev_priv(dev);
1505         struct net_device_stats *stats = &dev->stats;
1506         struct gfar_extra_stats *estats = &priv->extra_stats;
1507
1508         /* If the packet was truncated, none of the other errors
1509          * matter */
1510         if (status & RXBD_TRUNCATED) {
1511                 stats->rx_length_errors++;
1512
1513                 estats->rx_trunc++;
1514
1515                 return;
1516         }
1517         /* Count the errors, if there were any */
1518         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1519                 stats->rx_length_errors++;
1520
1521                 if (status & RXBD_LARGE)
1522                         estats->rx_large++;
1523                 else
1524                         estats->rx_short++;
1525         }
1526         if (status & RXBD_NONOCTET) {
1527                 stats->rx_frame_errors++;
1528                 estats->rx_nonoctet++;
1529         }
1530         if (status & RXBD_CRCERR) {
1531                 estats->rx_crcerr++;
1532                 stats->rx_crc_errors++;
1533         }
1534         if (status & RXBD_OVERRUN) {
1535                 estats->rx_overrun++;
1536                 stats->rx_crc_errors++;
1537         }
1538 }
1539
1540 irqreturn_t gfar_receive(int irq, void *dev_id)
1541 {
1542         struct net_device *dev = (struct net_device *) dev_id;
1543         struct gfar_private *priv = netdev_priv(dev);
1544         u32 tempval;
1545
1546         /* support NAPI */
1547         /* Clear IEVENT, so interrupts aren't called again
1548          * because of the packets that have already arrived */
1549         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1550
1551         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1552                 tempval = gfar_read(&priv->regs->imask);
1553                 tempval &= IMASK_RTX_DISABLED;
1554                 gfar_write(&priv->regs->imask, tempval);
1555
1556                 __netif_rx_schedule(dev, &priv->napi);
1557         } else {
1558                 if (netif_msg_rx_err(priv))
1559                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1560                                 dev->name, gfar_read(&priv->regs->ievent),
1561                                 gfar_read(&priv->regs->imask));
1562         }
1563
1564         return IRQ_HANDLED;
1565 }
1566
1567 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1568 {
1569         /* If valid headers were found, and valid sums
1570          * were verified, then we tell the kernel that no
1571          * checksumming is necessary.  Otherwise, it is */
1572         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1573                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1574         else
1575                 skb->ip_summed = CHECKSUM_NONE;
1576 }
1577
1578
1579 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1580 {
1581         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1582
1583         /* Remove the FCB from the skb */
1584         skb_pull(skb, GMAC_FCB_LEN);
1585
1586         return fcb;
1587 }
1588
1589 /* gfar_process_frame() -- handle one incoming packet if skb
1590  * isn't NULL.  */
1591 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1592                 int length)
1593 {
1594         struct gfar_private *priv = netdev_priv(dev);
1595         struct rxfcb *fcb = NULL;
1596
1597         if (NULL == skb) {
1598                 if (netif_msg_rx_err(priv))
1599                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1600                 dev->stats.rx_dropped++;
1601                 priv->extra_stats.rx_skbmissing++;
1602         } else {
1603                 int ret;
1604
1605                 /* Prep the skb for the packet */
1606                 skb_put(skb, length);
1607
1608                 /* Grab the FCB if there is one */
1609                 if (gfar_uses_fcb(priv))
1610                         fcb = gfar_get_fcb(skb);
1611
1612                 /* Remove the padded bytes, if there are any */
1613                 if (priv->padding)
1614                         skb_pull(skb, priv->padding);
1615
1616                 if (priv->rx_csum_enable)
1617                         gfar_rx_checksum(skb, fcb);
1618
1619                 /* Tell the skb what kind of packet this is */
1620                 skb->protocol = eth_type_trans(skb, dev);
1621
1622                 /* Send the packet up the stack */
1623                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) {
1624                         ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1625                                                        fcb->vlctl);
1626                 } else
1627                         ret = netif_receive_skb(skb);
1628
1629                 if (NET_RX_DROP == ret)
1630                         priv->extra_stats.kernel_dropped++;
1631         }
1632
1633         return 0;
1634 }
1635
1636 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1637  *   until the budget/quota has been reached. Returns the number
1638  *   of frames handled
1639  */
1640 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1641 {
1642         struct rxbd8 *bdp;
1643         struct sk_buff *skb;
1644         u16 pkt_len;
1645         int howmany = 0;
1646         struct gfar_private *priv = netdev_priv(dev);
1647
1648         /* Get the first full descriptor */
1649         bdp = priv->cur_rx;
1650
1651         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1652                 struct sk_buff *newskb;
1653                 rmb();
1654
1655                 /* Add another skb for the future */
1656                 newskb = gfar_new_skb(dev);
1657
1658                 skb = priv->rx_skbuff[priv->skb_currx];
1659
1660                 /* We drop the frame if we failed to allocate a new buffer */
1661                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1662                                  bdp->status & RXBD_ERR)) {
1663                         count_errors(bdp->status, dev);
1664
1665                         if (unlikely(!newskb))
1666                                 newskb = skb;
1667
1668                         if (skb) {
1669                                 dma_unmap_single(&priv->dev->dev,
1670                                                 bdp->bufPtr,
1671                                                 priv->rx_buffer_size,
1672                                                 DMA_FROM_DEVICE);
1673
1674                                 dev_kfree_skb_any(skb);
1675                         }
1676                 } else {
1677                         /* Increment the number of packets */
1678                         dev->stats.rx_packets++;
1679                         howmany++;
1680
1681                         /* Remove the FCS from the packet length */
1682                         pkt_len = bdp->length - 4;
1683
1684                         gfar_process_frame(dev, skb, pkt_len);
1685
1686                         dev->stats.rx_bytes += pkt_len;
1687                 }
1688
1689                 dev->last_rx = jiffies;
1690
1691                 priv->rx_skbuff[priv->skb_currx] = newskb;
1692
1693                 /* Setup the new bdp */
1694                 gfar_new_rxbdp(dev, bdp, newskb);
1695
1696                 /* Update to the next pointer */
1697                 if (bdp->status & RXBD_WRAP)
1698                         bdp = priv->rx_bd_base;
1699                 else
1700                         bdp++;
1701
1702                 /* update to point at the next skb */
1703                 priv->skb_currx =
1704                     (priv->skb_currx + 1) &
1705                     RX_RING_MOD_MASK(priv->rx_ring_size);
1706         }
1707
1708         /* Update the current rxbd pointer to be the next one */
1709         priv->cur_rx = bdp;
1710
1711         return howmany;
1712 }
1713
1714 static int gfar_poll(struct napi_struct *napi, int budget)
1715 {
1716         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1717         struct net_device *dev = priv->dev;
1718         int howmany;
1719         unsigned long flags;
1720
1721         /* If we fail to get the lock, don't bother with the TX BDs */
1722         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1723                 gfar_clean_tx_ring(dev);
1724                 spin_unlock_irqrestore(&priv->txlock, flags);
1725         }
1726
1727         howmany = gfar_clean_rx_ring(dev, budget);
1728
1729         if (howmany < budget) {
1730                 netif_rx_complete(dev, napi);
1731
1732                 /* Clear the halt bit in RSTAT */
1733                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1734
1735                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1736
1737                 /* If we are coalescing interrupts, update the timer */
1738                 /* Otherwise, clear it */
1739                 if (likely(priv->rxcoalescing)) {
1740                         gfar_write(&priv->regs->rxic, 0);
1741                         gfar_write(&priv->regs->rxic,
1742                                    mk_ic_value(priv->rxcount, priv->rxtime));
1743                 }
1744         }
1745
1746         return howmany;
1747 }
1748
1749 #ifdef CONFIG_NET_POLL_CONTROLLER
1750 /*
1751  * Polling 'interrupt' - used by things like netconsole to send skbs
1752  * without having to re-enable interrupts. It's not called while
1753  * the interrupt routine is executing.
1754  */
1755 static void gfar_netpoll(struct net_device *dev)
1756 {
1757         struct gfar_private *priv = netdev_priv(dev);
1758
1759         /* If the device has multiple interrupts, run tx/rx */
1760         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1761                 disable_irq(priv->interruptTransmit);
1762                 disable_irq(priv->interruptReceive);
1763                 disable_irq(priv->interruptError);
1764                 gfar_interrupt(priv->interruptTransmit, dev);
1765                 enable_irq(priv->interruptError);
1766                 enable_irq(priv->interruptReceive);
1767                 enable_irq(priv->interruptTransmit);
1768         } else {
1769                 disable_irq(priv->interruptTransmit);
1770                 gfar_interrupt(priv->interruptTransmit, dev);
1771                 enable_irq(priv->interruptTransmit);
1772         }
1773 }
1774 #endif
1775
1776 /* The interrupt handler for devices with one interrupt */
1777 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1778 {
1779         struct net_device *dev = dev_id;
1780         struct gfar_private *priv = netdev_priv(dev);
1781
1782         /* Save ievent for future reference */
1783         u32 events = gfar_read(&priv->regs->ievent);
1784
1785         /* Check for reception */
1786         if (events & IEVENT_RX_MASK)
1787                 gfar_receive(irq, dev_id);
1788
1789         /* Check for transmit completion */
1790         if (events & IEVENT_TX_MASK)
1791                 gfar_transmit(irq, dev_id);
1792
1793         /* Check for errors */
1794         if (events & IEVENT_ERR_MASK)
1795                 gfar_error(irq, dev_id);
1796
1797         return IRQ_HANDLED;
1798 }
1799
1800 /* Called every time the controller might need to be made
1801  * aware of new link state.  The PHY code conveys this
1802  * information through variables in the phydev structure, and this
1803  * function converts those variables into the appropriate
1804  * register values, and can bring down the device if needed.
1805  */
1806 static void adjust_link(struct net_device *dev)
1807 {
1808         struct gfar_private *priv = netdev_priv(dev);
1809         struct gfar __iomem *regs = priv->regs;
1810         unsigned long flags;
1811         struct phy_device *phydev = priv->phydev;
1812         int new_state = 0;
1813
1814         spin_lock_irqsave(&priv->txlock, flags);
1815         if (phydev->link) {
1816                 u32 tempval = gfar_read(&regs->maccfg2);
1817                 u32 ecntrl = gfar_read(&regs->ecntrl);
1818
1819                 /* Now we make sure that we can be in full duplex mode.
1820                  * If not, we operate in half-duplex mode. */
1821                 if (phydev->duplex != priv->oldduplex) {
1822                         new_state = 1;
1823                         if (!(phydev->duplex))
1824                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1825                         else
1826                                 tempval |= MACCFG2_FULL_DUPLEX;
1827
1828                         priv->oldduplex = phydev->duplex;
1829                 }
1830
1831                 if (phydev->speed != priv->oldspeed) {
1832                         new_state = 1;
1833                         switch (phydev->speed) {
1834                         case 1000:
1835                                 tempval =
1836                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1837                                 break;
1838                         case 100:
1839                         case 10:
1840                                 tempval =
1841                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1842
1843                                 /* Reduced mode distinguishes
1844                                  * between 10 and 100 */
1845                                 if (phydev->speed == SPEED_100)
1846                                         ecntrl |= ECNTRL_R100;
1847                                 else
1848                                         ecntrl &= ~(ECNTRL_R100);
1849                                 break;
1850                         default:
1851                                 if (netif_msg_link(priv))
1852                                         printk(KERN_WARNING
1853                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1854                                                 dev->name, phydev->speed);
1855                                 break;
1856                         }
1857
1858                         priv->oldspeed = phydev->speed;
1859                 }
1860
1861                 gfar_write(&regs->maccfg2, tempval);
1862                 gfar_write(&regs->ecntrl, ecntrl);
1863
1864                 if (!priv->oldlink) {
1865                         new_state = 1;
1866                         priv->oldlink = 1;
1867                 }
1868         } else if (priv->oldlink) {
1869                 new_state = 1;
1870                 priv->oldlink = 0;
1871                 priv->oldspeed = 0;
1872                 priv->oldduplex = -1;
1873         }
1874
1875         if (new_state && netif_msg_link(priv))
1876                 phy_print_status(phydev);
1877
1878         spin_unlock_irqrestore(&priv->txlock, flags);
1879 }
1880
1881 /* Update the hash table based on the current list of multicast
1882  * addresses we subscribe to.  Also, change the promiscuity of
1883  * the device based on the flags (this function is called
1884  * whenever dev->flags is changed */
1885 static void gfar_set_multi(struct net_device *dev)
1886 {
1887         struct dev_mc_list *mc_ptr;
1888         struct gfar_private *priv = netdev_priv(dev);
1889         struct gfar __iomem *regs = priv->regs;
1890         u32 tempval;
1891
1892         if(dev->flags & IFF_PROMISC) {
1893                 /* Set RCTRL to PROM */
1894                 tempval = gfar_read(&regs->rctrl);
1895                 tempval |= RCTRL_PROM;
1896                 gfar_write(&regs->rctrl, tempval);
1897         } else {
1898                 /* Set RCTRL to not PROM */
1899                 tempval = gfar_read(&regs->rctrl);
1900                 tempval &= ~(RCTRL_PROM);
1901                 gfar_write(&regs->rctrl, tempval);
1902         }
1903
1904         if(dev->flags & IFF_ALLMULTI) {
1905                 /* Set the hash to rx all multicast frames */
1906                 gfar_write(&regs->igaddr0, 0xffffffff);
1907                 gfar_write(&regs->igaddr1, 0xffffffff);
1908                 gfar_write(&regs->igaddr2, 0xffffffff);
1909                 gfar_write(&regs->igaddr3, 0xffffffff);
1910                 gfar_write(&regs->igaddr4, 0xffffffff);
1911                 gfar_write(&regs->igaddr5, 0xffffffff);
1912                 gfar_write(&regs->igaddr6, 0xffffffff);
1913                 gfar_write(&regs->igaddr7, 0xffffffff);
1914                 gfar_write(&regs->gaddr0, 0xffffffff);
1915                 gfar_write(&regs->gaddr1, 0xffffffff);
1916                 gfar_write(&regs->gaddr2, 0xffffffff);
1917                 gfar_write(&regs->gaddr3, 0xffffffff);
1918                 gfar_write(&regs->gaddr4, 0xffffffff);
1919                 gfar_write(&regs->gaddr5, 0xffffffff);
1920                 gfar_write(&regs->gaddr6, 0xffffffff);
1921                 gfar_write(&regs->gaddr7, 0xffffffff);
1922         } else {
1923                 int em_num;
1924                 int idx;
1925
1926                 /* zero out the hash */
1927                 gfar_write(&regs->igaddr0, 0x0);
1928                 gfar_write(&regs->igaddr1, 0x0);
1929                 gfar_write(&regs->igaddr2, 0x0);
1930                 gfar_write(&regs->igaddr3, 0x0);
1931                 gfar_write(&regs->igaddr4, 0x0);
1932                 gfar_write(&regs->igaddr5, 0x0);
1933                 gfar_write(&regs->igaddr6, 0x0);
1934                 gfar_write(&regs->igaddr7, 0x0);
1935                 gfar_write(&regs->gaddr0, 0x0);
1936                 gfar_write(&regs->gaddr1, 0x0);
1937                 gfar_write(&regs->gaddr2, 0x0);
1938                 gfar_write(&regs->gaddr3, 0x0);
1939                 gfar_write(&regs->gaddr4, 0x0);
1940                 gfar_write(&regs->gaddr5, 0x0);
1941                 gfar_write(&regs->gaddr6, 0x0);
1942                 gfar_write(&regs->gaddr7, 0x0);
1943
1944                 /* If we have extended hash tables, we need to
1945                  * clear the exact match registers to prepare for
1946                  * setting them */
1947                 if (priv->extended_hash) {
1948                         em_num = GFAR_EM_NUM + 1;
1949                         gfar_clear_exact_match(dev);
1950                         idx = 1;
1951                 } else {
1952                         idx = 0;
1953                         em_num = 0;
1954                 }
1955
1956                 if(dev->mc_count == 0)
1957                         return;
1958
1959                 /* Parse the list, and set the appropriate bits */
1960                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1961                         if (idx < em_num) {
1962                                 gfar_set_mac_for_addr(dev, idx,
1963                                                 mc_ptr->dmi_addr);
1964                                 idx++;
1965                         } else
1966                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1967                 }
1968         }
1969
1970         return;
1971 }
1972
1973
1974 /* Clears each of the exact match registers to zero, so they
1975  * don't interfere with normal reception */
1976 static void gfar_clear_exact_match(struct net_device *dev)
1977 {
1978         int idx;
1979         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1980
1981         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1982                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1983 }
1984
1985 /* Set the appropriate hash bit for the given addr */
1986 /* The algorithm works like so:
1987  * 1) Take the Destination Address (ie the multicast address), and
1988  * do a CRC on it (little endian), and reverse the bits of the
1989  * result.
1990  * 2) Use the 8 most significant bits as a hash into a 256-entry
1991  * table.  The table is controlled through 8 32-bit registers:
1992  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1993  * gaddr7.  This means that the 3 most significant bits in the
1994  * hash index which gaddr register to use, and the 5 other bits
1995  * indicate which bit (assuming an IBM numbering scheme, which
1996  * for PowerPC (tm) is usually the case) in the register holds
1997  * the entry. */
1998 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1999 {
2000         u32 tempval;
2001         struct gfar_private *priv = netdev_priv(dev);
2002         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2003         int width = priv->hash_width;
2004         u8 whichbit = (result >> (32 - width)) & 0x1f;
2005         u8 whichreg = result >> (32 - width + 5);
2006         u32 value = (1 << (31-whichbit));
2007
2008         tempval = gfar_read(priv->hash_regs[whichreg]);
2009         tempval |= value;
2010         gfar_write(priv->hash_regs[whichreg], tempval);
2011
2012         return;
2013 }
2014
2015
2016 /* There are multiple MAC Address register pairs on some controllers
2017  * This function sets the numth pair to a given address
2018  */
2019 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2020 {
2021         struct gfar_private *priv = netdev_priv(dev);
2022         int idx;
2023         char tmpbuf[MAC_ADDR_LEN];
2024         u32 tempval;
2025         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2026
2027         macptr += num*2;
2028
2029         /* Now copy it into the mac registers backwards, cuz */
2030         /* little endian is silly */
2031         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2032                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2033
2034         gfar_write(macptr, *((u32 *) (tmpbuf)));
2035
2036         tempval = *((u32 *) (tmpbuf + 4));
2037
2038         gfar_write(macptr+1, tempval);
2039 }
2040
2041 /* GFAR error interrupt handler */
2042 static irqreturn_t gfar_error(int irq, void *dev_id)
2043 {
2044         struct net_device *dev = dev_id;
2045         struct gfar_private *priv = netdev_priv(dev);
2046
2047         /* Save ievent for future reference */
2048         u32 events = gfar_read(&priv->regs->ievent);
2049
2050         /* Clear IEVENT */
2051         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2052
2053         /* Magic Packet is not an error. */
2054         if ((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2055             (events & IEVENT_MAG))
2056                 events &= ~IEVENT_MAG;
2057
2058         /* Hmm... */
2059         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2060                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2061                        dev->name, events, gfar_read(&priv->regs->imask));
2062
2063         /* Update the error counters */
2064         if (events & IEVENT_TXE) {
2065                 dev->stats.tx_errors++;
2066
2067                 if (events & IEVENT_LC)
2068                         dev->stats.tx_window_errors++;
2069                 if (events & IEVENT_CRL)
2070                         dev->stats.tx_aborted_errors++;
2071                 if (events & IEVENT_XFUN) {
2072                         if (netif_msg_tx_err(priv))
2073                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2074                                        "packet dropped.\n", dev->name);
2075                         dev->stats.tx_dropped++;
2076                         priv->extra_stats.tx_underrun++;
2077
2078                         /* Reactivate the Tx Queues */
2079                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2080                 }
2081                 if (netif_msg_tx_err(priv))
2082                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2083         }
2084         if (events & IEVENT_BSY) {
2085                 dev->stats.rx_errors++;
2086                 priv->extra_stats.rx_bsy++;
2087
2088                 gfar_receive(irq, dev_id);
2089
2090                 if (netif_msg_rx_err(priv))
2091                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2092                                dev->name, gfar_read(&priv->regs->rstat));
2093         }
2094         if (events & IEVENT_BABR) {
2095                 dev->stats.rx_errors++;
2096                 priv->extra_stats.rx_babr++;
2097
2098                 if (netif_msg_rx_err(priv))
2099                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2100         }
2101         if (events & IEVENT_EBERR) {
2102                 priv->extra_stats.eberr++;
2103                 if (netif_msg_rx_err(priv))
2104                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2105         }
2106         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2107                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2108
2109         if (events & IEVENT_BABT) {
2110                 priv->extra_stats.tx_babt++;
2111                 if (netif_msg_tx_err(priv))
2112                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2113         }
2114         return IRQ_HANDLED;
2115 }
2116
2117 /* work with hotplug and coldplug */
2118 MODULE_ALIAS("platform:fsl-gianfar");
2119
2120 /* Structure for a device driver */
2121 static struct platform_driver gfar_driver = {
2122         .probe = gfar_probe,
2123         .remove = gfar_remove,
2124         .suspend = gfar_suspend,
2125         .resume = gfar_resume,
2126         .driver = {
2127                 .name = "fsl-gianfar",
2128                 .owner = THIS_MODULE,
2129         },
2130 };
2131
2132 static int __init gfar_init(void)
2133 {
2134         int err = gfar_mdio_init();
2135
2136         if (err)
2137                 return err;
2138
2139         err = platform_driver_register(&gfar_driver);
2140
2141         if (err)
2142                 gfar_mdio_exit();
2143
2144         return err;
2145 }
2146
2147 static void __exit gfar_exit(void)
2148 {
2149         platform_driver_unregister(&gfar_driver);
2150         gfar_mdio_exit();
2151 }
2152
2153 module_init(gfar_init);
2154 module_exit(gfar_exit);
2155