drivers/net/amd8111e.c

   1
   2 /* Advanced  Micro Devices Inc. AMD8111E Linux Network Driver
   3  * Copyright (C) 2004 Advanced Micro Devices
   4  *
   5  *
   6  * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
   7  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
   8  * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
   9  * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
  10  * Copyright 1993 United States Government as represented by the
  11  *      Director, National Security Agency.[ pcnet32.c ]
  12  * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
  13  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  14  *
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307
  29  * USA
  30
  31 Module Name:
  32
  33         amd8111e.c
  34
  35 Abstract:
  36
  37          AMD8111 based 10/100 Ethernet Controller Driver.
  38
  39 Environment:
  40
  41         Kernel Mode
  42
  43 Revision History:
  44         3.0.0
  45            Initial Revision.
  46         3.0.1
  47          1. Dynamic interrupt coalescing.
  48          2. Removed prev_stats.
  49          3. MII support.
  50          4. Dynamic IPG support
  51         3.0.2  05/29/2003
  52          1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
  53          2. Bug fix: Fixed VLAN support failure.
  54          3. Bug fix: Fixed receive interrupt coalescing bug.
  55          4. Dynamic IPG support is disabled by default.
  56         3.0.3 06/05/2003
  57          1. Bug fix: Fixed failure to close the interface if SMP is enabled.
  58         3.0.4 12/09/2003
  59          1. Added set_mac_address routine for bonding driver support.
  60          2. Tested the driver for bonding support
  61          3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
  62             indicated to the h/w.
  63          4. Modified amd8111e_rx() routine to receive all the received packets
  64             in the first interrupt.
  65          5. Bug fix: Corrected  rx_errors  reported in get_stats() function.
  66         3.0.5 03/22/2004
  67          1. Added NAPI support
  68
  69 */
  70
  71
  72 #include <linux/module.h>
  73 #include <linux/kernel.h>
  74 #include <linux/types.h>
  75 #include <linux/compiler.h>
  76 #include <linux/slab.h>
  77 #include <linux/delay.h>
  78 #include <linux/init.h>
  79 #include <linux/ioport.h>
  80 #include <linux/pci.h>
  81 #include <linux/netdevice.h>
  82 #include <linux/etherdevice.h>
  83 #include <linux/skbuff.h>
  84 #include <linux/ethtool.h>
  85 #include <linux/mii.h>
  86 #include <linux/if_vlan.h>
  87 #include <linux/ctype.h>
  88 #include <linux/crc32.h>
  89 #include <linux/dma-mapping.h>
  90
  91 #include <asm/system.h>
  92 #include <asm/io.h>
  93 #include <asm/byteorder.h>
  94 #include <asm/uaccess.h>
  95
  96 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  97 #define AMD8111E_VLAN_TAG_USED 1
  98 #else
  99 #define AMD8111E_VLAN_TAG_USED 0
 100 #endif
 101
 102 #include "amd8111e.h"
 103 #define MODULE_NAME     "amd8111e"
 104 #define MODULE_VERS     "3.0.7"
 105 MODULE_AUTHOR("Advanced Micro Devices, Inc.");
 106 MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version "MODULE_VERS);
 107 MODULE_LICENSE("GPL");
 108 MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
 109 module_param_array(speed_duplex, int, NULL, 0);
 110 MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
 111 module_param_array(coalesce, bool, NULL, 0);
 112 MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
 113 module_param_array(dynamic_ipg, bool, NULL, 0);
 114 MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
 115
 116 static struct pci_device_id amd8111e_pci_tbl[] = {
 117
 118         { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
 119          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 120         { 0, }
 121
 122 };
 123 /*
 124 This function will read the PHY registers.
 125 */
 126 static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
 127 {
 128         void __iomem *mmio = lp->mmio;
 129         unsigned int reg_val;
 130         unsigned int repeat= REPEAT_CNT;
 131
 132         reg_val = readl(mmio + PHY_ACCESS);
 133         while (reg_val & PHY_CMD_ACTIVE)
 134                 reg_val = readl( mmio + PHY_ACCESS );
 135
 136         writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
 137                            ((reg & 0x1f) << 16),  mmio +PHY_ACCESS);
 138         do{
 139                 reg_val = readl(mmio + PHY_ACCESS);
 140                 udelay(30);  /* It takes 30 us to read/write data */
 141         } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
 142         if(reg_val & PHY_RD_ERR)
 143                 goto err_phy_read;
 144
 145         *val = reg_val & 0xffff;
 146         return 0;
 147 err_phy_read:
 148         *val = 0;
 149         return -EINVAL;
 150
 151 }
 152
 153 /*
 154 This function will write into PHY registers.
 155 */
 156 static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
 157 {
 158         unsigned int repeat = REPEAT_CNT;
 159         void __iomem *mmio = lp->mmio;
 160         unsigned int reg_val;
 161
 162         reg_val = readl(mmio + PHY_ACCESS);
 163         while (reg_val & PHY_CMD_ACTIVE)
 164                 reg_val = readl( mmio + PHY_ACCESS );
 165
 166         writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
 167                            ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
 168
 169         do{
 170                 reg_val = readl(mmio + PHY_ACCESS);
 171                 udelay(30);  /* It takes 30 us to read/write the data */
 172         } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
 173
 174         if(reg_val & PHY_RD_ERR)
 175                 goto err_phy_write;
 176
 177         return 0;
 178
 179 err_phy_write:
 180         return -EINVAL;
 181
 182 }
 183 /*
 184 This is the mii register read function provided to the mii interface.
 185 */
 186 static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
 187 {
 188         struct amd8111e_priv* lp = netdev_priv(dev);
 189         unsigned int reg_val;
 190
 191         amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
 192         return reg_val;
 193
 194 }
 195
 196 /*
 197 This is the mii register write function provided to the mii interface.
 198 */
 199 static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
 200 {
 201         struct amd8111e_priv* lp = netdev_priv(dev);
 202
 203         amd8111e_write_phy(lp, phy_id, reg_num, val);
 204 }
 205
 206 /*
 207 This function will set PHY speed. During initialization sets the original speed to 100 full.
 208 */
 209 static void amd8111e_set_ext_phy(struct net_device *dev)
 210 {
 211         struct amd8111e_priv *lp = netdev_priv(dev);
 212         u32 bmcr,advert,tmp;
 213
 214         /* Determine mii register values to set the speed */
 215         advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
 216         tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
 217         switch (lp->ext_phy_option){
 218
 219                 default:
 220                 case SPEED_AUTONEG: /* advertise all values */
 221                         tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
 222                                 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
 223                         break;
 224                 case SPEED10_HALF:
 225                         tmp |= ADVERTISE_10HALF;
 226                         break;
 227                 case SPEED10_FULL:
 228                         tmp |= ADVERTISE_10FULL;
 229                         break;
 230                 case SPEED100_HALF:
 231                         tmp |= ADVERTISE_100HALF;
 232                         break;
 233                 case SPEED100_FULL:
 234                         tmp |= ADVERTISE_100FULL;
 235                         break;
 236         }
 237
 238         if(advert != tmp)
 239                 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
 240         /* Restart auto negotiation */
 241         bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
 242         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
 243         amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
 244
 245 }
 246
 247 /*
 248 This function will unmap skb->data space and will free
 249 all transmit and receive skbuffs.
 250 */
 251 static int amd8111e_free_skbs(struct net_device *dev)
 252 {
 253         struct amd8111e_priv *lp = netdev_priv(dev);
 254         struct sk_buff* rx_skbuff;
 255         int i;
 256
 257         /* Freeing transmit skbs */
 258         for(i = 0; i < NUM_TX_BUFFERS; i++){
 259                 if(lp->tx_skbuff[i]){
 260                         pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i],                                        lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
 261                         dev_kfree_skb (lp->tx_skbuff[i]);
 262                         lp->tx_skbuff[i] = NULL;
 263                         lp->tx_dma_addr[i] = 0;
 264                 }
 265         }
 266         /* Freeing previously allocated receive buffers */
 267         for (i = 0; i < NUM_RX_BUFFERS; i++){
 268                 rx_skbuff = lp->rx_skbuff[i];
 269                 if(rx_skbuff != NULL){
 270                         pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
 271                                   lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
 272                         dev_kfree_skb(lp->rx_skbuff[i]);
 273                         lp->rx_skbuff[i] = NULL;
 274                         lp->rx_dma_addr[i] = 0;
 275                 }
 276         }
 277
 278         return 0;
 279 }
 280
 281 /*
 282 This will set the receive buffer length corresponding to the mtu size of networkinterface.
 283 */
 284 static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
 285 {
 286         struct amd8111e_priv* lp = netdev_priv(dev);
 287         unsigned int mtu = dev->mtu;
 288
 289         if (mtu > ETH_DATA_LEN){
 290                 /* MTU + ethernet header + FCS
 291                 + optional VLAN tag + skb reserve space 2 */
 292
 293                 lp->rx_buff_len = mtu + ETH_HLEN + 10;
 294                 lp->options |= OPTION_JUMBO_ENABLE;
 295         } else{
 296                 lp->rx_buff_len = PKT_BUFF_SZ;
 297                 lp->options &= ~OPTION_JUMBO_ENABLE;
 298         }
 299 }
 300
 301 /*
 302 This function will free all the previously allocated buffers, determine new receive buffer length  and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
 303  */
 304 static int amd8111e_init_ring(struct net_device *dev)
 305 {
 306         struct amd8111e_priv *lp = netdev_priv(dev);
 307         int i;
 308
 309         lp->rx_idx = lp->tx_idx = 0;
 310         lp->tx_complete_idx = 0;
 311         lp->tx_ring_idx = 0;
 312
 313
 314         if(lp->opened)
 315                 /* Free previously allocated transmit and receive skbs */
 316                 amd8111e_free_skbs(dev);
 317
 318         else{
 319                  /* allocate the tx and rx descriptors */
 320                 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
 321                         sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
 322                         &lp->tx_ring_dma_addr)) == NULL)
 323
 324                         goto err_no_mem;
 325
 326                 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
 327                         sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
 328                         &lp->rx_ring_dma_addr)) == NULL)
 329
 330                         goto err_free_tx_ring;
 331
 332         }
 333         /* Set new receive buff size */
 334         amd8111e_set_rx_buff_len(dev);
 335
 336         /* Allocating receive  skbs */
 337         for (i = 0; i < NUM_RX_BUFFERS; i++) {
 338
 339                 if (!(lp->rx_skbuff[i] = dev_alloc_skb(lp->rx_buff_len))) {
 340                                 /* Release previos allocated skbs */
 341                                 for(--i; i >= 0 ;i--)
 342                                         dev_kfree_skb(lp->rx_skbuff[i]);
 343                                 goto err_free_rx_ring;
 344                 }
 345                 skb_reserve(lp->rx_skbuff[i],2);
 346         }
 347         /* Initilaizing receive descriptors */
 348         for (i = 0; i < NUM_RX_BUFFERS; i++) {
 349                 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
 350                         lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
 351
 352                 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
 353                 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
 354                 wmb();
 355                 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
 356         }
 357
 358         /* Initializing transmit descriptors */
 359         for (i = 0; i < NUM_TX_RING_DR; i++) {
 360                 lp->tx_ring[i].buff_phy_addr = 0;
 361                 lp->tx_ring[i].tx_flags = 0;
 362                 lp->tx_ring[i].buff_count = 0;
 363         }
 364
 365         return 0;
 366
 367 err_free_rx_ring:
 368
 369         pci_free_consistent(lp->pci_dev,
 370                 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
 371                 lp->rx_ring_dma_addr);
 372
 373 err_free_tx_ring:
 374
 375         pci_free_consistent(lp->pci_dev,
 376                  sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
 377                  lp->tx_ring_dma_addr);
 378
 379 err_no_mem:
 380         return -ENOMEM;
 381 }
 382 /* This function will set the interrupt coalescing according to the input arguments */
 383 static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
 384 {
 385         unsigned int timeout;
 386         unsigned int event_count;
 387
 388         struct amd8111e_priv *lp = netdev_priv(dev);
 389         void __iomem *mmio = lp->mmio;
 390         struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
 391
 392
 393         switch(cmod)
 394         {
 395                 case RX_INTR_COAL :
 396                         timeout = coal_conf->rx_timeout;
 397                         event_count = coal_conf->rx_event_count;
 398                         if( timeout > MAX_TIMEOUT ||
 399                                         event_count > MAX_EVENT_COUNT )
 400                         return -EINVAL;
 401
 402                         timeout = timeout * DELAY_TIMER_CONV;
 403                         writel(VAL0|STINTEN, mmio+INTEN0);
 404                         writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
 405                                                         mmio+DLY_INT_A);
 406                         break;
 407
 408                 case TX_INTR_COAL :
 409                         timeout = coal_conf->tx_timeout;
 410                         event_count = coal_conf->tx_event_count;
 411                         if( timeout > MAX_TIMEOUT ||
 412                                         event_count > MAX_EVENT_COUNT )
 413                         return -EINVAL;
 414
 415
 416                         timeout = timeout * DELAY_TIMER_CONV;
 417                         writel(VAL0|STINTEN,mmio+INTEN0);
 418                         writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
 419                                                          mmio+DLY_INT_B);
 420                         break;
 421
 422                 case DISABLE_COAL:
 423                         writel(0,mmio+STVAL);
 424                         writel(STINTEN, mmio+INTEN0);
 425                         writel(0, mmio +DLY_INT_B);
 426                         writel(0, mmio+DLY_INT_A);
 427                         break;
 428                  case ENABLE_COAL:
 429                        /* Start the timer */
 430                         writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /*  0.5 sec */
 431                         writel(VAL0|STINTEN, mmio+INTEN0);
 432                         break;
 433                 default:
 434                         break;
 435
 436    }
 437         return 0;
 438
 439 }
 440
 441 /*
 442 This function initializes the device registers  and starts the device.
 443 */
 444 static int amd8111e_restart(struct net_device *dev)
 445 {
 446         struct amd8111e_priv *lp = netdev_priv(dev);
 447         void __iomem *mmio = lp->mmio;
 448         int i,reg_val;
 449
 450         /* stop the chip */
 451          writel(RUN, mmio + CMD0);
 452
 453         if(amd8111e_init_ring(dev))
 454                 return -ENOMEM;
 455
 456         /* enable the port manager and set auto negotiation always */
 457         writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
 458         writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
 459
 460         amd8111e_set_ext_phy(dev);
 461
 462         /* set control registers */
 463         reg_val = readl(mmio + CTRL1);
 464         reg_val &= ~XMTSP_MASK;
 465         writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
 466
 467         /* enable interrupt */
 468         writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
 469                 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
 470                 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
 471
 472         writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
 473
 474         /* initialize tx and rx ring base addresses */
 475         writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
 476         writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
 477
 478         writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
 479         writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
 480
 481         /* set default IPG to 96 */
 482         writew((u32)DEFAULT_IPG,mmio+IPG);
 483         writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
 484
 485         if(lp->options & OPTION_JUMBO_ENABLE){
 486                 writel((u32)VAL2|JUMBO, mmio + CMD3);
 487                 /* Reset REX_UFLO */
 488                 writel( REX_UFLO, mmio + CMD2);
 489                 /* Should not set REX_UFLO for jumbo frames */
 490                 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
 491         }else{
 492                 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
 493                 writel((u32)JUMBO, mmio + CMD3);
 494         }
 495
 496 #if AMD8111E_VLAN_TAG_USED
 497         writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
 498 #endif
 499         writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
 500
 501         /* Setting the MAC address to the device */
 502         for(i = 0; i < ETH_ADDR_LEN; i++)
 503                 writeb( dev->dev_addr[i], mmio + PADR + i );
 504
 505         /* Enable interrupt coalesce */
 506         if(lp->options & OPTION_INTR_COAL_ENABLE){
 507                 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
 508                                                                 dev->name);
 509                 amd8111e_set_coalesce(dev,ENABLE_COAL);
 510         }
 511
 512         /* set RUN bit to start the chip */
 513         writel(VAL2 | RDMD0, mmio + CMD0);
 514         writel(VAL0 | INTREN | RUN, mmio + CMD0);
 515
 516         /* To avoid PCI posting bug */
 517         readl(mmio+CMD0);
 518         return 0;
 519 }
 520 /*
 521 This function clears necessary the device registers.
 522 */
 523 static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
 524 {
 525         unsigned int reg_val;
 526         unsigned int logic_filter[2] ={0,};
 527         void __iomem *mmio = lp->mmio;
 528
 529
 530         /* stop the chip */
 531         writel(RUN, mmio + CMD0);
 532
 533         /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
 534         writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
 535
 536         /* Clear RCV_RING_BASE_ADDR */
 537         writel(0, mmio + RCV_RING_BASE_ADDR0);
 538
 539         /* Clear XMT_RING_BASE_ADDR */
 540         writel(0, mmio + XMT_RING_BASE_ADDR0);
 541         writel(0, mmio + XMT_RING_BASE_ADDR1);
 542         writel(0, mmio + XMT_RING_BASE_ADDR2);
 543         writel(0, mmio + XMT_RING_BASE_ADDR3);
 544
 545         /* Clear CMD0  */
 546         writel(CMD0_CLEAR,mmio + CMD0);
 547
 548         /* Clear CMD2 */
 549         writel(CMD2_CLEAR, mmio +CMD2);
 550
 551         /* Clear CMD7 */
 552         writel(CMD7_CLEAR , mmio + CMD7);
 553
 554         /* Clear DLY_INT_A and DLY_INT_B */
 555         writel(0x0, mmio + DLY_INT_A);
 556         writel(0x0, mmio + DLY_INT_B);
 557
 558         /* Clear FLOW_CONTROL */
 559         writel(0x0, mmio + FLOW_CONTROL);
 560
 561         /* Clear INT0  write 1 to clear register */
 562         reg_val = readl(mmio + INT0);
 563         writel(reg_val, mmio + INT0);
 564
 565         /* Clear STVAL */
 566         writel(0x0, mmio + STVAL);
 567
 568         /* Clear INTEN0 */
 569         writel( INTEN0_CLEAR, mmio + INTEN0);
 570
 571         /* Clear LADRF */
 572         writel(0x0 , mmio + LADRF);
 573
 574         /* Set SRAM_SIZE & SRAM_BOUNDARY registers  */
 575         writel( 0x80010,mmio + SRAM_SIZE);
 576
 577         /* Clear RCV_RING0_LEN */
 578         writel(0x0, mmio +  RCV_RING_LEN0);
 579
 580         /* Clear XMT_RING0/1/2/3_LEN */
 581         writel(0x0, mmio +  XMT_RING_LEN0);
 582         writel(0x0, mmio +  XMT_RING_LEN1);
 583         writel(0x0, mmio +  XMT_RING_LEN2);
 584         writel(0x0, mmio +  XMT_RING_LEN3);
 585
 586         /* Clear XMT_RING_LIMIT */
 587         writel(0x0, mmio + XMT_RING_LIMIT);
 588
 589         /* Clear MIB */
 590         writew(MIB_CLEAR, mmio + MIB_ADDR);
 591
 592         /* Clear LARF */
 593         amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
 594
 595         /* SRAM_SIZE register */
 596         reg_val = readl(mmio + SRAM_SIZE);
 597
 598         if(lp->options & OPTION_JUMBO_ENABLE)
 599                 writel( VAL2|JUMBO, mmio + CMD3);
 600 #if AMD8111E_VLAN_TAG_USED
 601         writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
 602 #endif
 603         /* Set default value to CTRL1 Register */
 604         writel(CTRL1_DEFAULT, mmio + CTRL1);
 605
 606         /* To avoid PCI posting bug */
 607         readl(mmio + CMD2);
 608
 609 }
 610
 611 /*
 612 This function disables the interrupt and clears all the pending
 613 interrupts in INT0
 614  */
 615 static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
 616 {
 617         u32 intr0;
 618
 619         /* Disable interrupt */
 620         writel(INTREN, lp->mmio + CMD0);
 621
 622         /* Clear INT0 */
 623         intr0 = readl(lp->mmio + INT0);
 624         writel(intr0, lp->mmio + INT0);
 625
 626         /* To avoid PCI posting bug */
 627         readl(lp->mmio + INT0);
 628
 629 }
 630
 631 /*
 632 This function stops the chip.
 633 */
 634 static void amd8111e_stop_chip(struct amd8111e_priv* lp)
 635 {
 636         writel(RUN, lp->mmio + CMD0);
 637
 638         /* To avoid PCI posting bug */
 639         readl(lp->mmio + CMD0);
 640 }
 641
 642 /*
 643 This function frees the  transmiter and receiver descriptor rings.
 644 */
 645 static void amd8111e_free_ring(struct amd8111e_priv* lp)
 646 {
 647         /* Free transmit and receive descriptor rings */
 648         if(lp->rx_ring){
 649                 pci_free_consistent(lp->pci_dev,
 650                         sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
 651                         lp->rx_ring, lp->rx_ring_dma_addr);
 652                 lp->rx_ring = NULL;
 653         }
 654
 655         if(lp->tx_ring){
 656                 pci_free_consistent(lp->pci_dev,
 657                         sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
 658                         lp->tx_ring, lp->tx_ring_dma_addr);
 659
 660                 lp->tx_ring = NULL;
 661         }
 662
 663 }
 664 #if AMD8111E_VLAN_TAG_USED
 665 /*
 666 This is the receive indication function for packets with vlan tag.
 667 */
 668 static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag)
 669 {
 670         return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag);
 671 }
 672 #endif
 673
 674 /*
 675 This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb.
 676 */
 677 static int amd8111e_tx(struct net_device *dev)
 678 {
 679         struct amd8111e_priv* lp = netdev_priv(dev);
 680         int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
 681         int status;
 682         /* Complete all the transmit packet */
 683         while (lp->tx_complete_idx != lp->tx_idx){
 684                 tx_index =  lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
 685                 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
 686
 687                 if(status & OWN_BIT)
 688                         break;  /* It still hasn't been Txed */
 689
 690                 lp->tx_ring[tx_index].buff_phy_addr = 0;
 691
 692                 /* We must free the original skb */
 693                 if (lp->tx_skbuff[tx_index]) {
 694                         pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
 695                                         lp->tx_skbuff[tx_index]->len,
 696                                         PCI_DMA_TODEVICE);
 697                         dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
 698                         lp->tx_skbuff[tx_index] = NULL;
 699                         lp->tx_dma_addr[tx_index] = 0;
 700                 }
 701                 lp->tx_complete_idx++;
 702                 /*COAL update tx coalescing parameters */
 703                 lp->coal_conf.tx_packets++;
 704                 lp->coal_conf.tx_bytes +=
 705                         le16_to_cpu(lp->tx_ring[tx_index].buff_count);
 706
 707                 if (netif_queue_stopped(dev) &&
 708                         lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
 709                         /* The ring is no longer full, clear tbusy. */
 710                         /* lp->tx_full = 0; */
 711                         netif_wake_queue (dev);
 712                 }
 713         }
 714         return 0;
 715 }
 716
 717 /* This function handles the driver receive operation in polling mode */
 718 static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
 719 {
 720         struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi);
 721         struct net_device *dev = lp->amd8111e_net_dev;
 722         int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
 723         void __iomem *mmio = lp->mmio;
 724         struct sk_buff *skb,*new_skb;
 725         int min_pkt_len, status;
 726         unsigned int intr0;
 727         int num_rx_pkt = 0;
 728         short pkt_len;
 729 #if AMD8111E_VLAN_TAG_USED
 730         short vtag;
 731 #endif
 732         int rx_pkt_limit = budget;
 733         unsigned long flags;
 734
 735         do{
 736                 /* process receive packets until we use the quota*/
 737                 /* If we own the next entry, it's a new packet. Send it up. */
 738                 while(1) {
 739                         status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
 740                         if (status & OWN_BIT)
 741                                 break;
 742
 743                         /*
 744                          * There is a tricky error noted by John Murphy,
 745                          * <murf@perftech.com> to Russ Nelson: Even with
 746                          * full-sized * buffers it's possible for a
 747                          * jabber packet to use two buffers, with only
 748                          * the last correctly noting the error.
 749                          */
 750
 751                         if(status & ERR_BIT) {
 752                                 /* reseting flags */
 753                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 754                                 goto err_next_pkt;
 755                         }
 756                         /* check for STP and ENP */
 757                         if(!((status & STP_BIT) && (status & ENP_BIT))){
 758                                 /* reseting flags */
 759                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 760                                 goto err_next_pkt;
 761                         }
 762                         pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
 763
 764 #if AMD8111E_VLAN_TAG_USED
 765                         vtag = status & TT_MASK;
 766                         /*MAC will strip vlan tag*/
 767                         if(lp->vlgrp != NULL && vtag !=0)
 768                                 min_pkt_len =MIN_PKT_LEN - 4;
 769                         else
 770 #endif
 771                                 min_pkt_len =MIN_PKT_LEN;
 772
 773                         if (pkt_len < min_pkt_len) {
 774                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 775                                 lp->drv_rx_errors++;
 776                                 goto err_next_pkt;
 777                         }
 778                         if(--rx_pkt_limit < 0)
 779                                 goto rx_not_empty;
 780                         if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
 781                                 /* if allocation fail,
 782                                    ignore that pkt and go to next one */
 783                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 784                                 lp->drv_rx_errors++;
 785                                 goto err_next_pkt;
 786                         }
 787
 788                         skb_reserve(new_skb, 2);
 789                         skb = lp->rx_skbuff[rx_index];
 790                         pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
 791                                          lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
 792                         skb_put(skb, pkt_len);
 793                         lp->rx_skbuff[rx_index] = new_skb;
 794                         lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
 795                                                                    new_skb->data,
 796                                                                    lp->rx_buff_len-2,
 797                                                                    PCI_DMA_FROMDEVICE);
 798
 799                         skb->protocol = eth_type_trans(skb, dev);
 800
 801 #if AMD8111E_VLAN_TAG_USED
 802                         if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
 803                                 amd8111e_vlan_rx(lp, skb,
 804                                          le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
 805                         } else
 806 #endif
 807                                 netif_receive_skb(skb);
 808                         /*COAL update rx coalescing parameters*/
 809                         lp->coal_conf.rx_packets++;
 810                         lp->coal_conf.rx_bytes += pkt_len;
 811                         num_rx_pkt++;
 812                         dev->last_rx = jiffies;
 813
 814                 err_next_pkt:
 815                         lp->rx_ring[rx_index].buff_phy_addr
 816                                 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
 817                         lp->rx_ring[rx_index].buff_count =
 818                                 cpu_to_le16(lp->rx_buff_len-2);
 819                         wmb();
 820                         lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
 821                         rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
 822                 }
 823                 /* Check the interrupt status register for more packets in the
 824                    mean time. Process them since we have not used up our quota.*/
 825
 826                 intr0 = readl(mmio + INT0);
 827                 /*Ack receive packets */
 828                 writel(intr0 & RINT0,mmio + INT0);
 829
 830         } while(intr0 & RINT0);
 831
 832         if (rx_pkt_limit > 0) {
 833                 /* Receive descriptor is empty now */
 834                 spin_lock_irqsave(&lp->lock, flags);
 835                 __netif_rx_complete(dev, napi);
 836                 writel(VAL0|RINTEN0, mmio + INTEN0);
 837                 writel(VAL2 | RDMD0, mmio + CMD0);
 838                 spin_unlock_irqrestore(&lp->lock, flags);
 839         }
 840
 841 rx_not_empty:
 842         return num_rx_pkt;
 843 }
 844
 845 /*
 846 This function will indicate the link status to the kernel.
 847 */
 848 static int amd8111e_link_change(struct net_device* dev)
 849 {
 850         struct amd8111e_priv *lp = netdev_priv(dev);
 851         int status0,speed;
 852
 853         /* read the link change */
 854         status0 = readl(lp->mmio + STAT0);
 855
 856         if(status0 & LINK_STATS){
 857                 if(status0 & AUTONEG_COMPLETE)
 858                         lp->link_config.autoneg = AUTONEG_ENABLE;
 859                 else
 860                         lp->link_config.autoneg = AUTONEG_DISABLE;
 861
 862                 if(status0 & FULL_DPLX)
 863                         lp->link_config.duplex = DUPLEX_FULL;
 864                 else
 865                         lp->link_config.duplex = DUPLEX_HALF;
 866                 speed = (status0 & SPEED_MASK) >> 7;
 867                 if(speed == PHY_SPEED_10)
 868                         lp->link_config.speed = SPEED_10;
 869                 else if(speed == PHY_SPEED_100)
 870                         lp->link_config.speed = SPEED_100;
 871
 872                 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n",                        dev->name,
 873                        (lp->link_config.speed == SPEED_100) ? "100": "10",
 874                        (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half");
 875                 netif_carrier_on(dev);
 876         }
 877         else{
 878                 lp->link_config.speed = SPEED_INVALID;
 879                 lp->link_config.duplex = DUPLEX_INVALID;
 880                 lp->link_config.autoneg = AUTONEG_INVALID;
 881                 printk(KERN_INFO "%s: Link is Down.\n",dev->name);
 882                 netif_carrier_off(dev);
 883         }
 884
 885         return 0;
 886 }
 887 /*
 888 This function reads the mib counters.
 889 */
 890 static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
 891 {
 892         unsigned int  status;
 893         unsigned  int data;
 894         unsigned int repeat = REPEAT_CNT;
 895
 896         writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
 897         do {
 898                 status = readw(mmio + MIB_ADDR);
 899                 udelay(2);      /* controller takes MAX 2 us to get mib data */
 900         }
 901         while (--repeat && (status & MIB_CMD_ACTIVE));
 902
 903         data = readl(mmio + MIB_DATA);
 904         return data;
 905 }
 906
 907 /*
 908 This function reads the mib registers and returns the hardware statistics. It  updates previous internal driver statistics with new values.
 909 */
 910 static struct net_device_stats *amd8111e_get_stats(struct net_device * dev)
 911 {
 912         struct amd8111e_priv *lp = netdev_priv(dev);
 913         void __iomem *mmio = lp->mmio;
 914         unsigned long flags;
 915         /* struct net_device_stats *prev_stats = &lp->prev_stats; */
 916         struct net_device_stats* new_stats = &lp->stats;
 917
 918         if(!lp->opened)
 919                 return &lp->stats;
 920         spin_lock_irqsave (&lp->lock, flags);
 921
 922         /* stats.rx_packets */
 923         new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
 924                                 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
 925                                 amd8111e_read_mib(mmio, rcv_unicast_pkts);
 926
 927         /* stats.tx_packets */
 928         new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
 929
 930         /*stats.rx_bytes */
 931         new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
 932
 933         /* stats.tx_bytes */
 934         new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
 935
 936         /* stats.rx_errors */
 937         /* hw errors + errors driver reported */
 938         new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
 939                                 amd8111e_read_mib(mmio, rcv_fragments)+
 940                                 amd8111e_read_mib(mmio, rcv_jabbers)+
 941                                 amd8111e_read_mib(mmio, rcv_alignment_errors)+
 942                                 amd8111e_read_mib(mmio, rcv_fcs_errors)+
 943                                 amd8111e_read_mib(mmio, rcv_miss_pkts)+
 944                                 lp->drv_rx_errors;
 945
 946         /* stats.tx_errors */
 947         new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
 948
 949         /* stats.rx_dropped*/
 950         new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
 951
 952         /* stats.tx_dropped*/
 953         new_stats->tx_dropped = amd8111e_read_mib(mmio,  xmt_underrun_pkts);
 954
 955         /* stats.multicast*/
 956         new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
 957
 958         /* stats.collisions*/
 959         new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
 960
 961         /* stats.rx_length_errors*/
 962         new_stats->rx_length_errors =
 963                 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
 964                 amd8111e_read_mib(mmio, rcv_oversize_pkts);
 965
 966         /* stats.rx_over_errors*/
 967         new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
 968
 969         /* stats.rx_crc_errors*/
 970         new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
 971
 972         /* stats.rx_frame_errors*/
 973         new_stats->rx_frame_errors =
 974                 amd8111e_read_mib(mmio, rcv_alignment_errors);
 975
 976         /* stats.rx_fifo_errors */
 977         new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
 978
 979         /* stats.rx_missed_errors */
 980         new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
 981
 982         /* stats.tx_aborted_errors*/
 983         new_stats->tx_aborted_errors =
 984                 amd8111e_read_mib(mmio, xmt_excessive_collision);
 985
 986         /* stats.tx_carrier_errors*/
 987         new_stats->tx_carrier_errors =
 988                 amd8111e_read_mib(mmio, xmt_loss_carrier);
 989
 990         /* stats.tx_fifo_errors*/
 991         new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
 992
 993         /* stats.tx_window_errors*/
 994         new_stats->tx_window_errors =
 995                 amd8111e_read_mib(mmio, xmt_late_collision);
 996
 997         /* Reset the mibs for collecting new statistics */
 998         /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
 999
1000         spin_unlock_irqrestore (&lp->lock, flags);
1001
1002         return new_stats;
1003 }
1004 /* This function recalculate the interrupt coalescing  mode on every interrupt
1005 according to the datarate and the packet rate.
1006 */
1007 static int amd8111e_calc_coalesce(struct net_device *dev)
1008 {
1009         struct amd8111e_priv *lp = netdev_priv(dev);
1010         struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
1011         int tx_pkt_rate;
1012         int rx_pkt_rate;
1013         int tx_data_rate;
1014         int rx_data_rate;
1015         int rx_pkt_size;
1016         int tx_pkt_size;
1017
1018         tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
1019         coal_conf->tx_prev_packets =  coal_conf->tx_packets;
1020
1021         tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
1022         coal_conf->tx_prev_bytes =  coal_conf->tx_bytes;
1023
1024         rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
1025         coal_conf->rx_prev_packets =  coal_conf->rx_packets;
1026
1027         rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
1028         coal_conf->rx_prev_bytes =  coal_conf->rx_bytes;
1029
1030         if(rx_pkt_rate < 800){
1031                 if(coal_conf->rx_coal_type != NO_COALESCE){
1032
1033                         coal_conf->rx_timeout = 0x0;
1034                         coal_conf->rx_event_count = 0;
1035                         amd8111e_set_coalesce(dev,RX_INTR_COAL);
1036                         coal_conf->rx_coal_type = NO_COALESCE;
1037                 }
1038         }
1039         else{
1040
1041                 rx_pkt_size = rx_data_rate/rx_pkt_rate;
1042                 if (rx_pkt_size < 128){
1043                         if(coal_conf->rx_coal_type != NO_COALESCE){
1044
1045                                 coal_conf->rx_timeout = 0;
1046                                 coal_conf->rx_event_count = 0;
1047                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1048                                 coal_conf->rx_coal_type = NO_COALESCE;
1049                         }
1050
1051                 }
1052                 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
1053
1054                         if(coal_conf->rx_coal_type !=  LOW_COALESCE){
1055                                 coal_conf->rx_timeout = 1;
1056                                 coal_conf->rx_event_count = 4;
1057                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1058                                 coal_conf->rx_coal_type = LOW_COALESCE;
1059                         }
1060                 }
1061                 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
1062
1063                         if(coal_conf->rx_coal_type !=  MEDIUM_COALESCE){
1064                                 coal_conf->rx_timeout = 1;
1065                                 coal_conf->rx_event_count = 4;
1066                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1067                                 coal_conf->rx_coal_type = MEDIUM_COALESCE;
1068                         }
1069
1070                 }
1071                 else if(rx_pkt_size >= 1024){
1072                         if(coal_conf->rx_coal_type !=  HIGH_COALESCE){
1073                                 coal_conf->rx_timeout = 2;
1074                                 coal_conf->rx_event_count = 3;
1075                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1076                                 coal_conf->rx_coal_type = HIGH_COALESCE;
1077                         }
1078                 }
1079         }
1080         /* NOW FOR TX INTR COALESC */
1081         if(tx_pkt_rate < 800){
1082                 if(coal_conf->tx_coal_type != NO_COALESCE){
1083
1084                         coal_conf->tx_timeout = 0x0;
1085                         coal_conf->tx_event_count = 0;
1086                         amd8111e_set_coalesce(dev,TX_INTR_COAL);
1087                         coal_conf->tx_coal_type = NO_COALESCE;
1088                 }
1089         }
1090         else{
1091
1092                 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1093                 if (tx_pkt_size < 128){
1094
1095                         if(coal_conf->tx_coal_type != NO_COALESCE){
1096
1097                                 coal_conf->tx_timeout = 0;
1098                                 coal_conf->tx_event_count = 0;
1099                                 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1100                                 coal_conf->tx_coal_type = NO_COALESCE;
1101                         }
1102
1103                 }
1104                 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
1105
1106                         if(coal_conf->tx_coal_type !=  LOW_COALESCE){
1107                                 coal_conf->tx_timeout = 1;
1108                                 coal_conf->tx_event_count = 2;
1109                                 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1110                                 coal_conf->tx_coal_type = LOW_COALESCE;
1111
1112                         }
1113                 }
1114                 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
1115
1116                         if(coal_conf->tx_coal_type !=  MEDIUM_COALESCE){
1117                                 coal_conf->tx_timeout = 2;
1118                                 coal_conf->tx_event_count = 5;
1119                                 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1120                                 coal_conf->tx_coal_type = MEDIUM_COALESCE;
1121                         }
1122
1123                 }
1124                 else if(tx_pkt_size >= 1024){
1125                         if (tx_pkt_size >= 1024){
1126                                 if(coal_conf->tx_coal_type !=  HIGH_COALESCE){
1127                                         coal_conf->tx_timeout = 4;
1128                                         coal_conf->tx_event_count = 8;
1129                                         amd8111e_set_coalesce(dev,TX_INTR_COAL);
1130                                         coal_conf->tx_coal_type = HIGH_COALESCE;
1131                                 }
1132                         }
1133                 }
1134         }
1135         return 0;
1136
1137 }
1138 /*
1139 This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
1140 */
1141 static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1142 {
1143
1144         struct net_device * dev = (struct net_device *) dev_id;
1145         struct amd8111e_priv *lp = netdev_priv(dev);
1146         void __iomem *mmio = lp->mmio;
1147         unsigned int intr0, intren0;
1148         unsigned int handled = 1;
1149
1150         if(unlikely(dev == NULL))
1151                 return IRQ_NONE;
1152
1153         spin_lock(&lp->lock);
1154
1155         /* disabling interrupt */
1156         writel(INTREN, mmio + CMD0);
1157
1158         /* Read interrupt status */
1159         intr0 = readl(mmio + INT0);
1160         intren0 = readl(mmio + INTEN0);
1161
1162         /* Process all the INT event until INTR bit is clear. */
1163
1164         if (!(intr0 & INTR)){
1165                 handled = 0;
1166                 goto err_no_interrupt;
1167         }
1168
1169         /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1170         writel(intr0, mmio + INT0);
1171
1172         /* Check if Receive Interrupt has occurred. */
1173         if (intr0 & RINT0) {
1174                 if (netif_rx_schedule_prep(dev, &lp->napi)) {
1175                         /* Disable receive interupts */
1176                         writel(RINTEN0, mmio + INTEN0);
1177                         /* Schedule a polling routine */
1178                         __netif_rx_schedule(dev, &lp->napi);
1179                 } else if (intren0 & RINTEN0) {
1180                         printk("************Driver bug! \
1181                                 interrupt while in poll\n");
1182                         /* Fix by disable receive interrupts */
1183                         writel(RINTEN0, mmio + INTEN0);
1184                 }
1185         }
1186
1187         /* Check if  Transmit Interrupt has occurred. */
1188         if (intr0 & TINT0)
1189                 amd8111e_tx(dev);
1190
1191         /* Check if  Link Change Interrupt has occurred. */
1192         if (intr0 & LCINT)
1193                 amd8111e_link_change(dev);
1194
1195         /* Check if Hardware Timer Interrupt has occurred. */
1196         if (intr0 & STINT)
1197                 amd8111e_calc_coalesce(dev);
1198
1199 err_no_interrupt:
1200         writel( VAL0 | INTREN,mmio + CMD0);
1201
1202         spin_unlock(&lp->lock);
1203
1204         return IRQ_RETVAL(handled);
1205 }
1206
1207 #ifdef CONFIG_NET_POLL_CONTROLLER
1208 static void amd8111e_poll(struct net_device *dev)
1209 {
1210         unsigned long flags;
1211         local_irq_save(flags);
1212         amd8111e_interrupt(0, dev);
1213         local_irq_restore(flags);
1214 }
1215 #endif
1216
1217
1218 /*
1219 This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
1220 */
1221 static int amd8111e_close(struct net_device * dev)
1222 {
1223         struct amd8111e_priv *lp = netdev_priv(dev);
1224         netif_stop_queue(dev);
1225
1226         napi_disable(&lp->napi);
1227
1228         spin_lock_irq(&lp->lock);
1229
1230         amd8111e_disable_interrupt(lp);
1231         amd8111e_stop_chip(lp);
1232
1233         /* Free transmit and receive skbs */
1234         amd8111e_free_skbs(lp->amd8111e_net_dev);
1235
1236         netif_carrier_off(lp->amd8111e_net_dev);
1237
1238         /* Delete ipg timer */
1239         if(lp->options & OPTION_DYN_IPG_ENABLE)
1240                 del_timer_sync(&lp->ipg_data.ipg_timer);
1241
1242         spin_unlock_irq(&lp->lock);
1243         free_irq(dev->irq, dev);
1244         amd8111e_free_ring(lp);
1245
1246         /* Update the statistics before closing */
1247         amd8111e_get_stats(dev);
1248         lp->opened = 0;
1249         return 0;
1250 }
1251 /* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device.
1252 */
1253 static int amd8111e_open(struct net_device * dev )
1254 {
1255         struct amd8111e_priv *lp = netdev_priv(dev);
1256
1257         if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED,
1258                                          dev->name, dev))
1259                 return -EAGAIN;
1260
1261         napi_enable(&lp->napi);
1262
1263         spin_lock_irq(&lp->lock);
1264
1265         amd8111e_init_hw_default(lp);
1266
1267         if(amd8111e_restart(dev)){
1268                 spin_unlock_irq(&lp->lock);
1269                 napi_disable(&lp->napi);
1270                 if (dev->irq)
1271                         free_irq(dev->irq, dev);
1272                 return -ENOMEM;
1273         }
1274         /* Start ipg timer */
1275         if(lp->options & OPTION_DYN_IPG_ENABLE){
1276                 add_timer(&lp->ipg_data.ipg_timer);
1277                 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
1278         }
1279
1280         lp->opened = 1;
1281
1282         spin_unlock_irq(&lp->lock);
1283
1284         netif_start_queue(dev);
1285
1286         return 0;
1287 }
1288 /*
1289 This function checks if there is any transmit  descriptors available to queue more packet.
1290 */
1291 static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp )
1292 {
1293         int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1294         if (lp->tx_skbuff[tx_index])
1295                 return -1;
1296         else
1297                 return 0;
1298
1299 }
1300 /*
1301 This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
1302 */
1303
1304 static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
1305 {
1306         struct amd8111e_priv *lp = netdev_priv(dev);
1307         int tx_index;
1308         unsigned long flags;
1309
1310         spin_lock_irqsave(&lp->lock, flags);
1311
1312         tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1313
1314         lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1315
1316         lp->tx_skbuff[tx_index] = skb;
1317         lp->tx_ring[tx_index].tx_flags = 0;
1318
1319 #if AMD8111E_VLAN_TAG_USED
1320         if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
1321                 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1322                                 cpu_to_le16(TCC_VLAN_INSERT);
1323                 lp->tx_ring[tx_index].tag_ctrl_info =
1324                                 cpu_to_le16(vlan_tx_tag_get(skb));
1325
1326         }
1327 #endif
1328         lp->tx_dma_addr[tx_index] =
1329             pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1330         lp->tx_ring[tx_index].buff_phy_addr =
1331             cpu_to_le32(lp->tx_dma_addr[tx_index]);
1332
1333         /*  Set FCS and LTINT bits */
1334         wmb();
1335         lp->tx_ring[tx_index].tx_flags |=
1336             cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1337
1338         lp->tx_idx++;
1339
1340         /* Trigger an immediate send poll. */
1341         writel( VAL1 | TDMD0, lp->mmio + CMD0);
1342         writel( VAL2 | RDMD0,lp->mmio + CMD0);
1343
1344         dev->trans_start = jiffies;
1345
1346         if(amd8111e_tx_queue_avail(lp) < 0){
1347                 netif_stop_queue(dev);
1348         }
1349         spin_unlock_irqrestore(&lp->lock, flags);
1350         return 0;
1351 }
1352 /*
1353 This function returns all the memory mapped registers of the device.
1354 */
1355 static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1356 {
1357         void __iomem *mmio = lp->mmio;
1358         /* Read only necessary registers */
1359         buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1360         buf[1] = readl(mmio + XMT_RING_LEN0);
1361         buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1362         buf[3] = readl(mmio + RCV_RING_LEN0);
1363         buf[4] = readl(mmio + CMD0);
1364         buf[5] = readl(mmio + CMD2);
1365         buf[6] = readl(mmio + CMD3);
1366         buf[7] = readl(mmio + CMD7);
1367         buf[8] = readl(mmio + INT0);
1368         buf[9] = readl(mmio + INTEN0);
1369         buf[10] = readl(mmio + LADRF);
1370         buf[11] = readl(mmio + LADRF+4);
1371         buf[12] = readl(mmio + STAT0);
1372 }
1373
1374
1375 /*
1376 This function sets promiscuos mode, all-multi mode or the multicast address
1377 list to the device.
1378 */
1379 static void amd8111e_set_multicast_list(struct net_device *dev)
1380 {
1381         struct dev_mc_list* mc_ptr;
1382         struct amd8111e_priv *lp = netdev_priv(dev);
1383         u32 mc_filter[2] ;
1384         int i,bit_num;
1385         if(dev->flags & IFF_PROMISC){
1386                 writel( VAL2 | PROM, lp->mmio + CMD2);
1387                 return;
1388         }
1389         else
1390                 writel( PROM, lp->mmio + CMD2);
1391         if(dev->flags & IFF_ALLMULTI || dev->mc_count > MAX_FILTER_SIZE){
1392                 /* get all multicast packet */
1393                 mc_filter[1] = mc_filter[0] = 0xffffffff;
1394                 lp->mc_list = dev->mc_list;
1395                 lp->options |= OPTION_MULTICAST_ENABLE;
1396                 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1397                 return;
1398         }
1399         if( dev->mc_count == 0 ){
1400                 /* get only own packets */
1401                 mc_filter[1] = mc_filter[0] = 0;
1402                 lp->mc_list = NULL;
1403                 lp->options &= ~OPTION_MULTICAST_ENABLE;
1404                 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1405                 /* disable promiscous mode */
1406                 writel(PROM, lp->mmio + CMD2);
1407                 return;
1408         }
1409         /* load all the multicast addresses in the logic filter */
1410         lp->options |= OPTION_MULTICAST_ENABLE;
1411         lp->mc_list = dev->mc_list;
1412         mc_filter[1] = mc_filter[0] = 0;
1413         for (i = 0, mc_ptr = dev->mc_list; mc_ptr && i < dev->mc_count;
1414                      i++, mc_ptr = mc_ptr->next) {
1415                 bit_num = (ether_crc_le(ETH_ALEN, mc_ptr->dmi_addr) >> 26) & 0x3f;
1416                 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1417         }
1418         amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
1419
1420         /* To eliminate PCI posting bug */
1421         readl(lp->mmio + CMD2);
1422
1423 }
1424
1425 static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info)
1426 {
1427         struct amd8111e_priv *lp = netdev_priv(dev);
1428         struct pci_dev *pci_dev = lp->pci_dev;
1429         strcpy (info->driver, MODULE_NAME);
1430         strcpy (info->version, MODULE_VERS);
1431         sprintf(info->fw_version,"%u",chip_version);
1432         strcpy (info->bus_info, pci_name(pci_dev));
1433 }
1434
1435 static int amd8111e_get_regs_len(struct net_device *dev)
1436 {
1437         return AMD8111E_REG_DUMP_LEN;
1438 }
1439
1440 static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1441 {
1442         struct amd8111e_priv *lp = netdev_priv(dev);
1443         regs->version = 0;
1444         amd8111e_read_regs(lp, buf);
1445 }
1446
1447 static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1448 {
1449         struct amd8111e_priv *lp = netdev_priv(dev);
1450         spin_lock_irq(&lp->lock);
1451         mii_ethtool_gset(&lp->mii_if, ecmd);
1452         spin_unlock_irq(&lp->lock);
1453         return 0;
1454 }
1455
1456 static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1457 {
1458         struct amd8111e_priv *lp = netdev_priv(dev);
1459         int res;
1460         spin_lock_irq(&lp->lock);
1461         res = mii_ethtool_sset(&lp->mii_if, ecmd);
1462         spin_unlock_irq(&lp->lock);
1463         return res;
1464 }
1465
1466 static int amd8111e_nway_reset(struct net_device *dev)
1467 {
1468         struct amd8111e_priv *lp = netdev_priv(dev);
1469         return mii_nway_restart(&lp->mii_if);
1470 }
1471
1472 static u32 amd8111e_get_link(struct net_device *dev)
1473 {
1474         struct amd8111e_priv *lp = netdev_priv(dev);
1475         return mii_link_ok(&lp->mii_if);
1476 }
1477
1478 static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1479 {
1480         struct amd8111e_priv *lp = netdev_priv(dev);
1481         wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1482         if (lp->options & OPTION_WOL_ENABLE)
1483                 wol_info->wolopts = WAKE_MAGIC;
1484 }
1485
1486 static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1487 {
1488         struct amd8111e_priv *lp = netdev_priv(dev);
1489         if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1490                 return -EINVAL;
1491         spin_lock_irq(&lp->lock);
1492         if (wol_info->wolopts & WAKE_MAGIC)
1493                 lp->options |=
1494                         (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1495         else if(wol_info->wolopts & WAKE_PHY)
1496                 lp->options |=
1497                         (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1498         else
1499                 lp->options &= ~OPTION_WOL_ENABLE;
1500         spin_unlock_irq(&lp->lock);
1501         return 0;
1502 }
1503
1504 static const struct ethtool_ops ops = {
1505         .get_drvinfo = amd8111e_get_drvinfo,
1506         .get_regs_len = amd8111e_get_regs_len,
1507         .get_regs = amd8111e_get_regs,
1508         .get_settings = amd8111e_get_settings,
1509         .set_settings = amd8111e_set_settings,
1510         .nway_reset = amd8111e_nway_reset,
1511         .get_link = amd8111e_get_link,
1512         .get_wol = amd8111e_get_wol,
1513         .set_wol = amd8111e_set_wol,
1514 };
1515
1516 /*
1517 This function handles all the  ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
1518 */
1519
1520 static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
1521 {
1522         struct mii_ioctl_data *data = if_mii(ifr);
1523         struct amd8111e_priv *lp = netdev_priv(dev);
1524         int err;
1525         u32 mii_regval;
1526
1527         if (!capable(CAP_NET_ADMIN))
1528                 return -EPERM;
1529
1530         switch(cmd) {
1531         case SIOCGMIIPHY:
1532                 data->phy_id = lp->ext_phy_addr;
1533
1534         /* fallthru */
1535         case SIOCGMIIREG:
1536
1537                 spin_lock_irq(&lp->lock);
1538                 err = amd8111e_read_phy(lp, data->phy_id,
1539                         data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1540                 spin_unlock_irq(&lp->lock);
1541
1542                 data->val_out = mii_regval;
1543                 return err;
1544
1545         case SIOCSMIIREG:
1546
1547                 spin_lock_irq(&lp->lock);
1548                 err = amd8111e_write_phy(lp, data->phy_id,
1549                         data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1550                 spin_unlock_irq(&lp->lock);
1551
1552                 return err;
1553
1554         default:
1555                 /* do nothing */
1556                 break;
1557         }
1558         return -EOPNOTSUPP;
1559 }
1560 static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1561 {
1562         struct amd8111e_priv *lp = netdev_priv(dev);
1563         int i;
1564         struct sockaddr *addr = p;
1565
1566         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1567         spin_lock_irq(&lp->lock);
1568         /* Setting the MAC address to the device */
1569         for(i = 0; i < ETH_ADDR_LEN; i++)
1570                 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1571
1572         spin_unlock_irq(&lp->lock);
1573
1574         return 0;
1575 }
1576
1577 /*
1578 This function changes the mtu of the device. It restarts the device  to initialize the descriptor with new receive buffers.
1579 */
1580 static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1581 {
1582         struct amd8111e_priv *lp = netdev_priv(dev);
1583         int err;
1584
1585         if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU))
1586                 return -EINVAL;
1587
1588         if (!netif_running(dev)) {
1589                 /* new_mtu will be used
1590                    when device starts netxt time */
1591                 dev->mtu = new_mtu;
1592                 return 0;
1593         }
1594
1595         spin_lock_irq(&lp->lock);
1596
1597         /* stop the chip */
1598         writel(RUN, lp->mmio + CMD0);
1599
1600         dev->mtu = new_mtu;
1601
1602         err = amd8111e_restart(dev);
1603         spin_unlock_irq(&lp->lock);
1604         if(!err)
1605                 netif_start_queue(dev);
1606         return err;
1607 }
1608
1609 #if AMD8111E_VLAN_TAG_USED
1610 static void amd8111e_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1611 {
1612         struct  amd8111e_priv *lp = netdev_priv(dev);
1613         spin_lock_irq(&lp->lock);
1614         lp->vlgrp = grp;
1615         spin_unlock_irq(&lp->lock);
1616 }
1617 #endif
1618
1619 static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
1620 {
1621         writel( VAL1|MPPLBA, lp->mmio + CMD3);
1622         writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1623
1624         /* To eliminate PCI posting bug */
1625         readl(lp->mmio + CMD7);
1626         return 0;
1627 }
1628
1629 static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
1630 {
1631
1632         /* Adapter is already stoped/suspended/interrupt-disabled */
1633         writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
1634
1635         /* To eliminate PCI posting bug */
1636         readl(lp->mmio + CMD7);
1637         return 0;
1638 }
1639 /* This function is called when a packet transmission fails to complete within a  resonable period, on the assumption that an interrupts have been failed or the  interface is locked up. This function will reinitialize the hardware */
1640
1641 static void amd8111e_tx_timeout(struct net_device *dev)
1642 {
1643         struct amd8111e_priv* lp = netdev_priv(dev);
1644         int err;
1645
1646         printk(KERN_ERR "%s: transmit timed out, resetting\n",
1647                                                       dev->name);
1648         spin_lock_irq(&lp->lock);
1649         err = amd8111e_restart(dev);
1650         spin_unlock_irq(&lp->lock);
1651         if(!err)
1652                 netif_wake_queue(dev);
1653 }
1654 static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
1655 {
1656         struct net_device *dev = pci_get_drvdata(pci_dev);
1657         struct amd8111e_priv *lp = netdev_priv(dev);
1658
1659         if (!netif_running(dev))
1660                 return 0;
1661
1662         /* disable the interrupt */
1663         spin_lock_irq(&lp->lock);
1664         amd8111e_disable_interrupt(lp);
1665         spin_unlock_irq(&lp->lock);
1666
1667         netif_device_detach(dev);
1668
1669         /* stop chip */
1670         spin_lock_irq(&lp->lock);
1671         if(lp->options & OPTION_DYN_IPG_ENABLE)
1672                 del_timer_sync(&lp->ipg_data.ipg_timer);
1673         amd8111e_stop_chip(lp);
1674         spin_unlock_irq(&lp->lock);
1675
1676         if(lp->options & OPTION_WOL_ENABLE){
1677                  /* enable wol */
1678                 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
1679                         amd8111e_enable_magicpkt(lp);
1680                 if(lp->options & OPTION_WAKE_PHY_ENABLE)
1681                         amd8111e_enable_link_change(lp);
1682
1683                 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1684                 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1685
1686         }
1687         else{
1688                 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1689                 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1690         }
1691
1692         pci_save_state(pci_dev);
1693         pci_set_power_state(pci_dev, PCI_D3hot);
1694
1695         return 0;
1696 }
1697 static int amd8111e_resume(struct pci_dev *pci_dev)
1698 {
1699         struct net_device *dev = pci_get_drvdata(pci_dev);
1700         struct amd8111e_priv *lp = netdev_priv(dev);
1701
1702         if (!netif_running(dev))
1703                 return 0;
1704
1705         pci_set_power_state(pci_dev, PCI_D0);
1706         pci_restore_state(pci_dev);
1707
1708         pci_enable_wake(pci_dev, PCI_D3hot, 0);
1709         pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1710
1711         netif_device_attach(dev);
1712
1713         spin_lock_irq(&lp->lock);
1714         amd8111e_restart(dev);
1715         /* Restart ipg timer */
1716         if(lp->options & OPTION_DYN_IPG_ENABLE)
1717                 mod_timer(&lp->ipg_data.ipg_timer,
1718                                 jiffies + IPG_CONVERGE_JIFFIES);
1719         spin_unlock_irq(&lp->lock);
1720
1721         return 0;
1722 }
1723
1724
1725 static void __devexit amd8111e_remove_one(struct pci_dev *pdev)
1726 {
1727         struct net_device *dev = pci_get_drvdata(pdev);
1728         if (dev) {
1729                 unregister_netdev(dev);
1730                 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio);
1731                 free_netdev(dev);
1732                 pci_release_regions(pdev);
1733                 pci_disable_device(pdev);
1734                 pci_set_drvdata(pdev, NULL);
1735         }
1736 }
1737 static void amd8111e_config_ipg(struct net_device* dev)
1738 {
1739         struct amd8111e_priv *lp = netdev_priv(dev);
1740         struct ipg_info* ipg_data = &lp->ipg_data;
1741         void __iomem *mmio = lp->mmio;
1742         unsigned int prev_col_cnt = ipg_data->col_cnt;
1743         unsigned int total_col_cnt;
1744         unsigned int tmp_ipg;
1745
1746         if(lp->link_config.duplex == DUPLEX_FULL){
1747                 ipg_data->ipg = DEFAULT_IPG;
1748                 return;
1749         }
1750
1751         if(ipg_data->ipg_state == SSTATE){
1752
1753                 if(ipg_data->timer_tick == IPG_STABLE_TIME){
1754
1755                         ipg_data->timer_tick = 0;
1756                         ipg_data->ipg = MIN_IPG - IPG_STEP;
1757                         ipg_data->current_ipg = MIN_IPG;
1758                         ipg_data->diff_col_cnt = 0xFFFFFFFF;
1759                         ipg_data->ipg_state = CSTATE;
1760                 }
1761                 else
1762                         ipg_data->timer_tick++;
1763         }
1764
1765         if(ipg_data->ipg_state == CSTATE){
1766
1767                 /* Get the current collision count */
1768
1769                 total_col_cnt = ipg_data->col_cnt =
1770                                 amd8111e_read_mib(mmio, xmt_collisions);
1771
1772                 if ((total_col_cnt - prev_col_cnt) <
1773                                 (ipg_data->diff_col_cnt)){
1774
1775                         ipg_data->diff_col_cnt =
1776                                 total_col_cnt - prev_col_cnt ;
1777
1778                         ipg_data->ipg = ipg_data->current_ipg;
1779                 }
1780
1781                 ipg_data->current_ipg += IPG_STEP;
1782
1783                 if (ipg_data->current_ipg <= MAX_IPG)
1784                         tmp_ipg = ipg_data->current_ipg;
1785                 else{
1786                         tmp_ipg = ipg_data->ipg;
1787                         ipg_data->ipg_state = SSTATE;
1788                 }
1789                 writew((u32)tmp_ipg, mmio + IPG);
1790                 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1791         }
1792          mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1793         return;
1794
1795 }
1796
1797 static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
1798 {
1799         struct amd8111e_priv *lp = netdev_priv(dev);
1800         int i;
1801
1802         for (i = 0x1e; i >= 0; i--) {
1803                 u32 id1, id2;
1804
1805                 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1806                         continue;
1807                 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1808                         continue;
1809                 lp->ext_phy_id = (id1 << 16) | id2;
1810                 lp->ext_phy_addr = i;
1811                 return;
1812         }
1813         lp->ext_phy_id = 0;
1814         lp->ext_phy_addr = 1;
1815 }
1816
1817 static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
1818                                   const struct pci_device_id *ent)
1819 {
1820         int err,i,pm_cap;
1821         unsigned long reg_addr,reg_len;
1822         struct amd8111e_priv* lp;
1823         struct net_device* dev;
1824         DECLARE_MAC_BUF(mac);
1825
1826         err = pci_enable_device(pdev);
1827         if(err){
1828                 printk(KERN_ERR "amd8111e: Cannot enable new PCI device, "
1829                         "exiting.\n");
1830                 return err;
1831         }
1832
1833         if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
1834                 printk(KERN_ERR "amd8111e: Cannot find PCI base address, "
1835                        "exiting.\n");
1836                 err = -ENODEV;
1837                 goto err_disable_pdev;
1838         }
1839
1840         err = pci_request_regions(pdev, MODULE_NAME);
1841         if(err){
1842                 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, "
1843                        "exiting.\n");
1844                 goto err_disable_pdev;
1845         }
1846
1847         pci_set_master(pdev);
1848
1849         /* Find power-management capability. */
1850         if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){
1851                 printk(KERN_ERR "amd8111e: No Power Management capability, "
1852                        "exiting.\n");
1853                 goto err_free_reg;
1854         }
1855
1856         /* Initialize DMA */
1857         if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) < 0) {
1858                 printk(KERN_ERR "amd8111e: DMA not supported,"
1859                         "exiting.\n");
1860                 goto err_free_reg;
1861         }
1862
1863         reg_addr = pci_resource_start(pdev, 0);
1864         reg_len = pci_resource_len(pdev, 0);
1865
1866         dev = alloc_etherdev(sizeof(struct amd8111e_priv));
1867         if (!dev) {
1868                 printk(KERN_ERR "amd8111e: Etherdev alloc failed, exiting.\n");
1869                 err = -ENOMEM;
1870                 goto err_free_reg;
1871         }
1872
1873         SET_NETDEV_DEV(dev, &pdev->dev);
1874
1875 #if AMD8111E_VLAN_TAG_USED
1876         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ;
1877         dev->vlan_rx_register =amd8111e_vlan_rx_register;
1878 #endif
1879
1880         lp = netdev_priv(dev);
1881         lp->pci_dev = pdev;
1882         lp->amd8111e_net_dev = dev;
1883         lp->pm_cap = pm_cap;
1884
1885         spin_lock_init(&lp->lock);
1886
1887         lp->mmio = ioremap(reg_addr, reg_len);
1888         if (!lp->mmio) {
1889                 printk(KERN_ERR "amd8111e: Cannot map device registers, "
1890                        "exiting\n");
1891                 err = -ENOMEM;
1892                 goto err_free_dev;
1893         }
1894
1895         /* Initializing MAC address */
1896         for(i = 0; i < ETH_ADDR_LEN; i++)
1897                 dev->dev_addr[i] = readb(lp->mmio + PADR + i);
1898
1899         /* Setting user defined parametrs */
1900         lp->ext_phy_option = speed_duplex[card_idx];
1901         if(coalesce[card_idx])
1902                 lp->options |= OPTION_INTR_COAL_ENABLE;
1903         if(dynamic_ipg[card_idx++])
1904                 lp->options |= OPTION_DYN_IPG_ENABLE;
1905
1906         /* Initialize driver entry points */
1907         dev->open = amd8111e_open;
1908         dev->hard_start_xmit = amd8111e_start_xmit;
1909         dev->stop = amd8111e_close;
1910         dev->get_stats = amd8111e_get_stats;
1911         dev->set_multicast_list = amd8111e_set_multicast_list;
1912         dev->set_mac_address = amd8111e_set_mac_address;
1913         dev->do_ioctl = amd8111e_ioctl;
1914         dev->change_mtu = amd8111e_change_mtu;
1915         SET_ETHTOOL_OPS(dev, &ops);
1916         dev->irq =pdev->irq;
1917         dev->tx_timeout = amd8111e_tx_timeout;
1918         dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
1919         netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32);
1920 #ifdef CONFIG_NET_POLL_CONTROLLER
1921         dev->poll_controller = amd8111e_poll;
1922 #endif
1923
1924 #if AMD8111E_VLAN_TAG_USED
1925         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1926         dev->vlan_rx_register =amd8111e_vlan_rx_register;
1927 #endif
1928         /* Probe the external PHY */
1929         amd8111e_probe_ext_phy(dev);
1930
1931         /* setting mii default values */
1932         lp->mii_if.dev = dev;
1933         lp->mii_if.mdio_read = amd8111e_mdio_read;
1934         lp->mii_if.mdio_write = amd8111e_mdio_write;
1935         lp->mii_if.phy_id = lp->ext_phy_addr;
1936
1937         /* Set receive buffer length and set jumbo option*/
1938         amd8111e_set_rx_buff_len(dev);
1939
1940
1941         err = register_netdev(dev);
1942         if (err) {
1943                 printk(KERN_ERR "amd8111e: Cannot register net device, "
1944                        "exiting.\n");
1945                 goto err_iounmap;
1946         }
1947
1948         pci_set_drvdata(pdev, dev);
1949
1950         /* Initialize software ipg timer */
1951         if(lp->options & OPTION_DYN_IPG_ENABLE){
1952                 init_timer(&lp->ipg_data.ipg_timer);
1953                 lp->ipg_data.ipg_timer.data = (unsigned long) dev;
1954                 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
1955                 lp->ipg_data.ipg_timer.expires = jiffies +
1956                                                  IPG_CONVERGE_JIFFIES;
1957                 lp->ipg_data.ipg = DEFAULT_IPG;
1958                 lp->ipg_data.ipg_state = CSTATE;
1959         };
1960
1961         /*  display driver and device information */
1962
1963         chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
1964         printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n",
1965                dev->name,MODULE_VERS);
1966         printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet %s\n",
1967                dev->name, chip_version, print_mac(mac, dev->dev_addr));
1968         if (lp->ext_phy_id)
1969                 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
1970                        dev->name, lp->ext_phy_id, lp->ext_phy_addr);
1971         else
1972                 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
1973                        dev->name);
1974         return 0;
1975 err_iounmap:
1976         iounmap(lp->mmio);
1977
1978 err_free_dev:
1979         free_netdev(dev);
1980
1981 err_free_reg:
1982         pci_release_regions(pdev);
1983
1984 err_disable_pdev:
1985         pci_disable_device(pdev);
1986         pci_set_drvdata(pdev, NULL);
1987         return err;
1988
1989 }
1990
1991 static struct pci_driver amd8111e_driver = {
1992         .name           = MODULE_NAME,
1993         .id_table       = amd8111e_pci_tbl,
1994         .probe          = amd8111e_probe_one,
1995         .remove         = __devexit_p(amd8111e_remove_one),
1996         .suspend        = amd8111e_suspend,
1997         .resume         = amd8111e_resume
1998 };
1999
2000 static int __init amd8111e_init(void)
2001 {
2002         return pci_register_driver(&amd8111e_driver);
2003 }
2004
2005 static void __exit amd8111e_cleanup(void)
2006 {
2007         pci_unregister_driver(&amd8111e_driver);
2008 }
2009
2010 module_init(amd8111e_init);
2011 module_exit(amd8111e_cleanup);