drivers/mtd/onenand/omap2.c

   1 /*
   2  *  linux/drivers/mtd/onenand/omap2.c
   3  *
   4  *  OneNAND driver for OMAP2
   5  *
   6  *  Copyright (C) 2005-2006 Nokia Corporation
   7  *
   8  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjola
   9  *  IRQ and DMA support written by Timo Teras
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License version 2 as published by
  13  * the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program; see the file COPYING. If not, write to the Free Software
  22  * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23  *
  24  */
  25
  26 #include <linux/device.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/onenand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/delay.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/mach/flash.h>
  38 #include <asm/arch/gpmc.h>
  39 #include <asm/arch/onenand.h>
  40 #include <asm/arch/gpio.h>
  41 #include <asm/arch/gpmc.h>
  42 #include <asm/arch/pm.h>
  43
  44 #include <linux/dma-mapping.h>
  45 #include <asm/dma-mapping.h>
  46 #include <asm/arch/dma.h>
  47
  48 #include <asm/arch/board.h>
  49
  50 #define DRIVER_NAME "omap2-onenand"
  51
  52 #define ONENAND_IO_SIZE         SZ_128K
  53 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
  54
  55 struct omap2_onenand {
  56         struct platform_device *pdev;
  57         int gpmc_cs;
  58         unsigned long phys_base;
  59         int gpio_irq;
  60         struct mtd_info mtd;
  61         struct mtd_partition *parts;
  62         struct onenand_chip onenand;
  63         struct completion irq_done;
  64         struct completion dma_done;
  65         int dma_channel;
  66         int freq;
  67         int (*setup)(void __iomem *base, int freq);
  68 };
  69
  70 static unsigned short omap2_onenand_readw(void __iomem *addr)
  71 {
  72         return readw(addr);
  73 }
  74
  75 static void omap2_onenand_writew(unsigned short value, void __iomem *addr)
  76 {
  77         writew(value, addr);
  78 }
  79
  80 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
  81 {
  82         struct omap2_onenand *info = data;
  83
  84         complete(&info->dma_done);
  85 }
  86
  87 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
  88 {
  89         struct omap2_onenand *info = dev_id;
  90
  91         complete(&info->irq_done);
  92
  93         return IRQ_HANDLED;
  94 }
  95
  96 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
  97 {
  98         struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
  99         unsigned int interrupt = 0;
 100         unsigned int ctrl;
 101         unsigned long timeout;
 102         u32 syscfg;
 103
 104         if (state == FL_RESETING) {
 105                 int i;
 106
 107                 for (i = 0; i < 20; i++) {
 108                         udelay(1);
 109                         interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 110                         if (interrupt & ONENAND_INT_MASTER)
 111                                 break;
 112                 }
 113                 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 114                 if (ctrl & ONENAND_CTRL_ERROR) {
 115                         printk(KERN_ERR "onenand_wait: reset error! ctrl 0x%04x intr 0x%04x\n", ctrl, interrupt);
 116                         return -EIO;
 117                 }
 118                 if (!(interrupt & ONENAND_INT_RESET)) {
 119                         printk(KERN_ERR "onenand_wait: reset timeout! ctrl 0x%04x intr 0x%04x\n", ctrl, interrupt);
 120                         return -EIO;
 121                 }
 122                 return 0;
 123         }
 124
 125         if (state != FL_READING) {
 126                 int result;
 127                 /* Turn interrupts on */
 128                 syscfg = omap2_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
 129                 syscfg |= ONENAND_SYS_CFG1_IOBE;
 130                 omap2_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
 131
 132                 INIT_COMPLETION(info->irq_done);
 133                 if (info->gpio_irq) {
 134                         result = omap_get_gpio_datain(info->gpio_irq);
 135                         if (result == -1) {
 136                                 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 137                                 printk(KERN_ERR "onenand_wait: gpio error, state = %d, ctrl = 0x%04x\n", state, ctrl);
 138                                 return -EIO;
 139                         }
 140                 } else {
 141                         result = 0;
 142                 }
 143                 if (result == 0) {
 144                         int retry_cnt = 0;
 145 retry:
 146                         result = wait_for_completion_timeout(&info->irq_done,
 147                                                     msecs_to_jiffies(20));
 148                         if (result == 0) {
 149                                 /* Timeout after 20ms */
 150                                 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 151                                 if (ctrl & ONENAND_CTRL_ONGO) {
 152                                         /* The operation seems to be still going - so give it some more time */
 153                                         retry_cnt += 1;
 154                                         if (retry_cnt < 3)
 155                                                 goto retry;
 156                                         interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 157                                         printk(KERN_ERR "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
 158                                         return -EIO;
 159                                 }
 160                                 interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 161                                 if ((interrupt & ONENAND_INT_MASTER) == 0)
 162                                         printk(KERN_WARNING "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
 163                         }
 164                 }
 165         } else {
 166                 /* Turn interrupts off */
 167                 syscfg = omap2_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
 168                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
 169                 omap2_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
 170
 171                 timeout = jiffies + msecs_to_jiffies(20);
 172                 while (time_before(jiffies, timeout)) {
 173                         if (omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT) &
 174                             ONENAND_INT_MASTER)
 175                                 break;
 176                 }
 177         }
 178
 179         /* To get correct interrupt status in timeout case */
 180         interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 181         ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 182
 183         if (ctrl & ONENAND_CTRL_ERROR) {
 184                 printk(KERN_ERR "onenand_wait: controller error = 0x%04x\n", ctrl);
 185                 if (ctrl & ONENAND_CTRL_LOCK)
 186                         printk(KERN_ERR "onenand_erase: Device is write protected!!!\n");
 187                 return -EIO;
 188         }
 189
 190         if (ctrl & 0xFE9F)
 191                 printk(KERN_WARNING "onenand_wait: unexpected controller status = 0x%04x  state = %d  interrupt = 0x%04x\n", ctrl, state, interrupt);
 192
 193         if (interrupt & ONENAND_INT_READ) {
 194                 int ecc = omap2_onenand_readw(info->onenand.base + ONENAND_REG_ECC_STATUS);
 195                 if (ecc) {
 196                         if (ecc & ONENAND_ECC_2BIT_ALL) {
 197                                 printk(KERN_ERR "onenand_wait: ECC error = 0x%04x\n", ecc);
 198                                 mtd->ecc_stats.failed++;
 199                                 return -EBADMSG;
 200                         } else if (ecc & ONENAND_ECC_1BIT_ALL)
 201                                 printk(KERN_NOTICE "onenand_wait: correctable ECC error = 0x%04x\n", ecc);
 202                                 mtd->ecc_stats.corrected++;
 203                 }
 204         } else if (state == FL_READING) {
 205                 printk(KERN_ERR "onenand_wait: read timeout! ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt);
 206                 return -EIO;
 207         }
 208
 209         return 0;
 210 }
 211
 212 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 213 {
 214         struct onenand_chip *this = mtd->priv;
 215
 216         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 217                 if (area == ONENAND_DATARAM)
 218                         return mtd->writesize;
 219                 if (area == ONENAND_SPARERAM)
 220                         return mtd->oobsize;
 221         }
 222
 223         return 0;
 224 }
 225
 226 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 227                                         unsigned char *buffer, int offset,
 228                                         size_t count)
 229 {
 230         struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
 231         struct onenand_chip *this = mtd->priv;
 232         dma_addr_t dma_src, dma_dst;
 233         int bram_offset;
 234
 235         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 236         if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
 237             (bram_offset & 3) || (((unsigned int) buffer) & 3) ||
 238             (count < 1024) || (count & 3)) {
 239                 memcpy(buffer, (void *)(this->base + bram_offset), count);
 240                 return 0;
 241         }
 242
 243         dma_src = info->phys_base + bram_offset;
 244         dma_dst = dma_map_single(&info->pdev->dev, buffer, count, DMA_FROM_DEVICE);
 245         if (dma_mapping_error(dma_dst)) {
 246                 dev_err(&info->pdev->dev,
 247                         "Couldn't DMA map a %d byte buffer\n",
 248                         count);
 249                 return -1;
 250         }
 251
 252         omap_set_dma_transfer_params(info->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 253                                      count / 4, 1, 0, 0, 0);
 254         omap_set_dma_src_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 255                                 dma_src, 0, 0);
 256         omap_set_dma_dest_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 257                                  dma_dst, 0, 0);
 258
 259         INIT_COMPLETION(info->dma_done);
 260         omap2_block_sleep();
 261         omap_start_dma(info->dma_channel);
 262         wait_for_completion(&info->dma_done);
 263         omap2_allow_sleep();
 264
 265         dma_unmap_single(&info->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 266
 267         return 0;
 268 }
 269
 270 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 271                                          const unsigned char *buffer, int offset,
 272                                          size_t count)
 273 {
 274         struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
 275         struct onenand_chip *this = mtd->priv;
 276         dma_addr_t dma_src, dma_dst;
 277         int bram_offset;
 278
 279         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 280         if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
 281             (bram_offset & 3) || (((unsigned int) buffer) & 3) ||
 282             (count < 1024) || (count & 3)) {
 283                 memcpy((void *)(this->base + bram_offset), buffer, count);
 284                 return 0;
 285         }
 286
 287         dma_src = dma_map_single(&info->pdev->dev, (void *) buffer, count,
 288                                  DMA_TO_DEVICE);
 289         dma_dst = info->phys_base + bram_offset;
 290         if (dma_mapping_error(dma_dst)) {
 291                 dev_err(&info->pdev->dev,
 292                         "Couldn't DMA map a %d byte buffer\n",
 293                         count);
 294                 return -1;
 295         }
 296
 297         omap_set_dma_transfer_params(info->dma_channel, OMAP_DMA_DATA_TYPE_S16,
 298                                      count / 2, 1, 0, 0, 0);
 299         omap_set_dma_src_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 300                                 dma_src, 0, 0);
 301         omap_set_dma_dest_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 302                                  dma_dst, 0, 0);
 303
 304         INIT_COMPLETION(info->dma_done);
 305         omap_start_dma(info->dma_channel);
 306         wait_for_completion(&info->dma_done);
 307
 308         dma_unmap_single(&info->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
 309
 310         return 0;
 311 }
 312
 313 static struct platform_driver omap2_onenand_driver;
 314
 315 static int __adjust_timing(struct device *dev, void *data)
 316 {
 317         int ret = 0;
 318         struct omap2_onenand *info;
 319
 320         info = dev_get_drvdata(dev);
 321
 322         BUG_ON(info->setup == NULL);
 323
 324         /* DMA is not in use so this is all that is needed */
 325         ret = info->setup(info->onenand.base, info->freq);
 326
 327         return ret;
 328 }
 329
 330 int omap2_onenand_rephase(void)
 331 {
 332         return driver_for_each_device(&omap2_onenand_driver.driver, NULL,
 333                                       NULL, __adjust_timing);
 334 }
 335
 336 static void __devexit omap2_onenand_shutdown(struct platform_device *pdev)
 337 {
 338         struct omap2_onenand *info = dev_get_drvdata(&pdev->dev);
 339
 340         /* With certain content in the buffer RAM, the OMAP boot ROM code
 341          * can recognize the flash chip incorrectly. Zero it out before
 342          * soft reset.
 343          */
 344         memset(info->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 345 }
 346
 347 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
 348 {
 349         struct omap_onenand_platform_data *pdata;
 350         struct omap2_onenand *info;
 351         int r;
 352
 353         pdata = pdev->dev.platform_data;
 354         if (pdata == NULL) {
 355                 dev_err(&pdev->dev, "platform data missing\n");
 356                 return -ENODEV;
 357         }
 358
 359         info = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
 360         if (!info)
 361                 return -ENOMEM;
 362
 363         init_completion(&info->irq_done);
 364         init_completion(&info->dma_done);
 365         info->gpmc_cs = pdata->cs;
 366         info->gpio_irq = pdata->gpio_irq;
 367         info->dma_channel = pdata->dma_channel;
 368         if (info->dma_channel < 0) {
 369                 /* if -1, don't use DMA */
 370                 info->gpio_irq = 0;
 371         }
 372
 373         r = gpmc_cs_request(info->gpmc_cs, ONENAND_IO_SIZE, &info->phys_base);
 374         if (r < 0) {
 375                 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
 376                 goto err_kfree;
 377         }
 378
 379         if (request_mem_region(info->phys_base, ONENAND_IO_SIZE,
 380                                pdev->dev.driver->name) == NULL) {
 381                 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
 382                         info->phys_base, ONENAND_IO_SIZE);
 383                 r = -EBUSY;
 384                 goto err_free_cs;
 385         }
 386         info->onenand.base = ioremap(info->phys_base, ONENAND_IO_SIZE);
 387         if (info->onenand.base == NULL) {
 388                 r = -ENOMEM;
 389                 goto err_release_mem_region;
 390         }
 391
 392         if (pdata->onenand_setup != NULL) {
 393                 r = pdata->onenand_setup(info->onenand.base, info->freq);
 394                 if (r < 0) {
 395                         dev_err(&pdev->dev, "Onenand platform setup failed: %d\n", r);
 396                         goto err_iounmap;
 397                 }
 398                 info->setup = pdata->onenand_setup;
 399         }
 400
 401         if (info->gpio_irq) {
 402                 if ((r = omap_request_gpio(info->gpio_irq)) < 0) {
 403                         dev_err(&pdev->dev,  "Failed to request GPIO%d for OneNAND\n",
 404                                 info->gpio_irq);
 405                         goto err_iounmap;
 406         }
 407         omap_set_gpio_direction(info->gpio_irq, 1);
 408
 409         if ((r = request_irq(OMAP_GPIO_IRQ(info->gpio_irq),
 410                              omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
 411                              pdev->dev.driver->name, info)) < 0)
 412                 goto err_release_gpio;
 413         }
 414
 415         if (info->dma_channel >= 0) {
 416                 r = omap_request_dma(0, pdev->dev.driver->name,
 417                                      omap2_onenand_dma_cb, (void *) info,
 418                                      &info->dma_channel);
 419                 if (r == 0) {
 420                         omap_set_dma_write_mode(info->dma_channel, OMAP_DMA_WRITE_NON_POSTED);
 421                         omap_set_dma_src_data_pack(info->dma_channel, 1);
 422                         omap_set_dma_src_burst_mode(info->dma_channel, OMAP_DMA_DATA_BURST_8);
 423                         omap_set_dma_dest_data_pack(info->dma_channel, 1);
 424                         omap_set_dma_dest_burst_mode(info->dma_channel, OMAP_DMA_DATA_BURST_8);
 425                 } else {
 426                         dev_info(&pdev->dev,
 427                                  "failed to allocate DMA for OneNAND, using PIO instead\n");
 428                         info->dma_channel = -1;
 429                 }
 430         }
 431
 432         dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual base %p\n",
 433                  info->gpmc_cs, info->phys_base, info->onenand.base);
 434
 435         info->pdev = pdev;
 436         info->mtd.name = pdev->dev.bus_id;
 437         info->mtd.priv = &info->onenand;
 438         info->mtd.owner = THIS_MODULE;
 439
 440         if (info->dma_channel >= 0) {
 441                 info->onenand.wait = omap2_onenand_wait;
 442                 info->onenand.read_bufferram = omap2_onenand_read_bufferram;
 443                 info->onenand.write_bufferram = omap2_onenand_write_bufferram;
 444         }
 445
 446         if ((r = onenand_scan(&info->mtd, 1)) < 0)
 447                 goto err_release_dma;
 448
 449         switch ((info->onenand.version_id >> 4) & 0xf) {
 450         case 0:
 451                 info->freq = 40;
 452                 break;
 453         case 1:
 454                 info->freq = 54;
 455                 break;
 456         case 2:
 457                 info->freq = 66;
 458                 break;
 459         case 3:
 460                 info->freq = 83;
 461                 break;
 462         }
 463
 464 #ifdef CONFIG_MTD_PARTITIONS
 465         if (pdata->parts != NULL)
 466                 r = add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
 467         else
 468 #endif
 469                 r = add_mtd_device(&info->mtd);
 470         if (r < 0)
 471                 goto err_release_onenand;
 472
 473         platform_set_drvdata(pdev, info);
 474
 475         return 0;
 476
 477 err_release_onenand:
 478         onenand_release(&info->mtd);
 479 err_release_dma:
 480         if (info->dma_channel != -1)
 481                 omap_free_dma(info->dma_channel);
 482         if (info->gpio_irq)
 483                 free_irq(OMAP_GPIO_IRQ(info->gpio_irq), info);
 484 err_release_gpio:
 485         if (info->gpio_irq)
 486                 omap_free_gpio(info->gpio_irq);
 487 err_iounmap:
 488         iounmap(info->onenand.base);
 489 err_release_mem_region:
 490         release_mem_region(info->phys_base, ONENAND_IO_SIZE);
 491 err_free_cs:
 492         gpmc_cs_free(info->gpmc_cs);
 493 err_kfree:
 494         kfree(info);
 495
 496         return r;
 497 }
 498
 499 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
 500 {
 501         struct omap2_onenand *info = dev_get_drvdata(&pdev->dev);
 502
 503         BUG_ON(info == NULL);
 504
 505 #ifdef CONFIG_MTD_PARTITIONS
 506         if (info->parts)
 507                 del_mtd_partitions(&info->mtd);
 508         else
 509                 del_mtd_device(&info->mtd);
 510 #else
 511         del_mtd_device(&info->mtd);
 512 #endif
 513
 514         onenand_release(&info->mtd);
 515         if (info->dma_channel != -1)
 516                 omap_free_dma(info->dma_channel);
 517         omap2_onenand_shutdown(pdev);
 518         platform_set_drvdata(pdev, NULL);
 519         if (info->gpio_irq) {
 520                 free_irq(OMAP_GPIO_IRQ(info->gpio_irq), info);
 521                 omap_free_gpio(info->gpio_irq);
 522         }
 523         iounmap(info->onenand.base);
 524         release_mem_region(info->phys_base, ONENAND_IO_SIZE);
 525         kfree(info);
 526
 527         return 0;
 528 }
 529
 530 static struct platform_driver omap2_onenand_driver = {
 531         .probe          = omap2_onenand_probe,
 532         .remove         = omap2_onenand_remove,
 533         .shutdown       = omap2_onenand_shutdown,
 534         .driver         = {
 535                 .name   = DRIVER_NAME,
 536                 .owner  = THIS_MODULE,
 537         },
 538 };
 539
 540 static int __init omap2_onenand_init(void)
 541 {
 542         printk(KERN_INFO "OMAP2 OneNAND driver initializing\n");
 543         return platform_driver_register(&omap2_onenand_driver);
 544 }
 545
 546 static void __exit omap2_onenand_exit(void)
 547 {
 548         platform_driver_unregister(&omap2_onenand_driver);
 549 }
 550
 551 module_init(omap2_onenand_init);
 552 module_exit(omap2_onenand_exit);
 553
 554 MODULE_ALIAS(DRIVER_NAME);
 555 MODULE_LICENSE("GPL");
 556 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
 557 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2");