drivers/mtd/onenand/omap2.c

   1 /*
   2  *  linux/drivers/mtd/onenand/omap2.c
   3  *
   4  *  OneNAND driver for OMAP2
   5  *
   6  *  Copyright (C) 2005-2006 Nokia Corporation
   7  *
   8  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjola
   9  *  IRQ and DMA support written by Timo Teras
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License version 2 as published by
  13  * the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program; see the file COPYING. If not, write to the Free Software
  22  * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23  *
  24  */
  25
  26 #include <linux/device.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/onenand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/delay.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/mach/flash.h>
  38 #include <asm/arch/gpmc.h>
  39 #include <asm/arch/onenand.h>
  40 #include <asm/arch/gpio.h>
  41 #include <asm/arch/gpmc.h>
  42 #include <asm/arch/pm.h>
  43
  44 #include <linux/dma-mapping.h>
  45 #include <asm/dma-mapping.h>
  46 #include <asm/arch/dma.h>
  47
  48 #include <asm/arch/board.h>
  49
  50 #define ONENAND_IO_SIZE         SZ_128K
  51 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
  52
  53 struct omap2_onenand {
  54         struct platform_device *pdev;
  55         int gpmc_cs;
  56         unsigned long phys_base;
  57         int gpio_irq;
  58         struct mtd_info mtd;
  59         struct mtd_partition *parts;
  60         struct onenand_chip onenand;
  61         struct completion irq_done;
  62         struct completion dma_done;
  63         int dma_channel;
  64 };
  65
  66 static unsigned short omap2_onenand_readw(void __iomem *addr)
  67 {
  68         return readw(addr);
  69 }
  70
  71 static void omap2_onenand_writew(unsigned short value, void __iomem *addr)
  72 {
  73         writew(value, addr);
  74 }
  75
  76 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
  77 {
  78         struct omap2_onenand *info = data;
  79
  80         complete(&info->dma_done);
  81 }
  82
  83 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
  84 {
  85         struct omap2_onenand *info = dev_id;
  86
  87         complete(&info->irq_done);
  88
  89         return IRQ_HANDLED;
  90 }
  91
  92 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
  93 {
  94         struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
  95         unsigned int interrupt = 0;
  96         unsigned int ctrl;
  97         unsigned long timeout;
  98         u32 syscfg;
  99
 100         if (state == FL_RESETING) {
 101                 udelay(1);
 102                 return 0;
 103         }
 104
 105         if (state != FL_READING) {
 106                 int result;
 107                 /* Turn interrupts on */
 108                 syscfg = omap2_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
 109                 syscfg |= ONENAND_SYS_CFG1_IOBE;
 110                 omap2_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
 111
 112                 INIT_COMPLETION(info->irq_done);
 113                 if (info->gpio_irq) {
 114                         result = omap_get_gpio_datain(info->gpio_irq);
 115                         if (result == -1) {
 116                                 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 117                                 printk(KERN_ERR "onenand_wait: gpio error, state = %d, ctrl = 0x%04x\n", state, ctrl);
 118                                 return -EIO;
 119                         }
 120                 } else {
 121                         result = 0;
 122                 }
 123                 if (result == 0) {
 124                         int retry_cnt = 0;
 125 retry:
 126                         result = wait_for_completion_timeout(&info->irq_done,
 127                                                     msecs_to_jiffies(20));
 128                         if (result == 0) {
 129                                 /* Timeout after 20ms */
 130                                 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 131                                 if (ctrl & ONENAND_CTRL_ONGO) {
 132                                         /* The operation seems to be still going - so give it some more time */
 133                                         retry_cnt += 1;
 134                                         if (retry_cnt < 3)
 135                                                 goto retry;
 136                                         interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 137                                         printk(KERN_ERR "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
 138                                         return -EIO;
 139                                 }
 140                                 interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 141                                 if ((interrupt & ONENAND_INT_MASTER) == 0)
 142                                         printk(KERN_WARNING "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
 143                         }
 144                 }
 145         } else {
 146                 /* Turn interrupts off */
 147                 syscfg = omap2_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
 148                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
 149                 omap2_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
 150
 151                 timeout = jiffies + msecs_to_jiffies(20);
 152                 while (time_before(jiffies, timeout)) {
 153                         if (omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT) &
 154                             ONENAND_INT_MASTER)
 155                                 break;
 156                 }
 157         }
 158
 159         /* To get correct interrupt status in timeout case */
 160         interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 161         ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 162
 163         if (ctrl & ONENAND_CTRL_ERROR) {
 164                 printk(KERN_ERR "onenand_wait: controller error = 0x%04x\n", ctrl);
 165                 if (ctrl & ONENAND_CTRL_LOCK)
 166                         printk(KERN_ERR "onenand_erase: Device is write protected!!!\n");
 167                 return ctrl;
 168         }
 169
 170         if (ctrl & 0xFE9F)
 171                 printk(KERN_WARNING "onenand_wait: unexpected controller status = 0x%04x  state = %d  interrupt = 0x%04x\n", ctrl, state, interrupt);
 172
 173         if (interrupt & ONENAND_INT_READ) {
 174                 int ecc = omap2_onenand_readw(info->onenand.base + ONENAND_REG_ECC_STATUS);
 175                 if (ecc) {
 176                         printk(KERN_ERR "onenand_wait: ECC error = 0x%04x\n", ecc);
 177                         if (ecc & ONENAND_ECC_2BIT_ALL) {
 178                                 mtd->ecc_stats.failed++;
 179                                 return ecc;
 180                         } else if (ecc & ONENAND_ECC_1BIT_ALL)
 181                                 mtd->ecc_stats.corrected++;
 182                 }
 183         } else if (state == FL_READING) {
 184                 printk(KERN_ERR "onenand_wait: read timeout! ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt);
 185                 return -EIO;
 186         }
 187
 188         return 0;
 189 }
 190
 191 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 192 {
 193         struct onenand_chip *this = mtd->priv;
 194
 195         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 196                 if (area == ONENAND_DATARAM)
 197                         return mtd->writesize;
 198                 if (area == ONENAND_SPARERAM)
 199                         return mtd->oobsize;
 200         }
 201
 202         return 0;
 203 }
 204
 205 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 206                                         unsigned char *buffer, int offset,
 207                                         size_t count)
 208 {
 209         struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
 210         struct onenand_chip *this = mtd->priv;
 211         dma_addr_t dma_src, dma_dst;
 212         int bram_offset;
 213
 214         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 215         if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
 216             (bram_offset & 3) || (((unsigned int) buffer) & 3) ||
 217             (count < 1024) || (count & 3)) {
 218                 memcpy(buffer, (void *)(this->base + bram_offset), count);
 219                 return 0;
 220         }
 221
 222         dma_src = info->phys_base + bram_offset;
 223         dma_dst = dma_map_single(&info->pdev->dev, buffer, count, DMA_FROM_DEVICE);
 224         if (dma_mapping_error(dma_dst)) {
 225                 dev_err(&info->pdev->dev,
 226                         "Couldn't DMA map a %d byte buffer\n",
 227                         count);
 228                 return -1;
 229         }
 230
 231         omap_set_dma_transfer_params(info->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 232                                      count / 4, 1, 0, 0, 0);
 233         omap_set_dma_src_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 234                                 dma_src, 0, 0);
 235         omap_set_dma_dest_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 236                                  dma_dst, 0, 0);
 237
 238         INIT_COMPLETION(info->dma_done);
 239         omap2_block_sleep();
 240         omap_start_dma(info->dma_channel);
 241         wait_for_completion(&info->dma_done);
 242         omap2_allow_sleep();
 243
 244         dma_unmap_single(&info->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 245
 246         return 0;
 247 }
 248
 249 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 250                                          const unsigned char *buffer, int offset,
 251                                          size_t count)
 252 {
 253         struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
 254         struct onenand_chip *this = mtd->priv;
 255         dma_addr_t dma_src, dma_dst;
 256         int bram_offset;
 257
 258         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 259         if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
 260             (bram_offset & 3) || (((unsigned int) buffer) & 3) ||
 261             (count < 1024) || (count & 3)) {
 262                 memcpy((void *)(this->base + bram_offset), buffer, count);
 263                 return 0;
 264         }
 265
 266         dma_src = dma_map_single(&info->pdev->dev, (void *) buffer, count,
 267                                  DMA_TO_DEVICE);
 268         dma_dst = info->phys_base + bram_offset;
 269         if (dma_mapping_error(dma_dst)) {
 270                 dev_err(&info->pdev->dev,
 271                         "Couldn't DMA map a %d byte buffer\n",
 272                         count);
 273                 return -1;
 274         }
 275
 276         omap_set_dma_transfer_params(info->dma_channel, OMAP_DMA_DATA_TYPE_S16,
 277                                      count / 2, 1, 0, 0, 0);
 278         omap_set_dma_src_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 279                                 dma_src, 0, 0);
 280         omap_set_dma_dest_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 281                                  dma_dst, 0, 0);
 282
 283         INIT_COMPLETION(info->dma_done);
 284         omap_start_dma(info->dma_channel);
 285         wait_for_completion(&info->dma_done);
 286
 287         dma_unmap_single(&info->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
 288
 289         return 0;
 290 }
 291
 292 static void __devexit omap2_onenand_shutdown(struct platform_device *pdev)
 293 {
 294         struct omap2_onenand *info = dev_get_drvdata(&pdev->dev);
 295
 296         /* With certain content in the buffer RAM, the OMAP boot ROM code
 297          * can recognize the flash chip incorrectly. Zero it out before
 298          * soft reset.
 299          */
 300         memset(info->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 301 }
 302
 303 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
 304 {
 305         struct omap_onenand_platform_data *pdata;
 306         struct omap2_onenand *info;
 307         int r;
 308
 309         pdata = pdev->dev.platform_data;
 310         if (pdata == NULL) {
 311                 dev_err(&pdev->dev, "platform data missing\n");
 312                 return -ENODEV;
 313         }
 314
 315         info = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
 316         if (!info)
 317                 return -ENOMEM;
 318
 319         init_completion(&info->irq_done);
 320         init_completion(&info->dma_done);
 321         info->gpmc_cs = pdata->cs;
 322         info->gpio_irq = pdata->gpio_irq;
 323         info->dma_channel = pdata->dma_channel;
 324         if (info->dma_channel < 0) {
 325                 /* if -1, don't use DMA */
 326                 info->gpio_irq = 0;
 327         }
 328
 329         r = gpmc_cs_request(info->gpmc_cs, ONENAND_IO_SIZE, &info->phys_base);
 330         if (r < 0) {
 331                 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
 332                 goto err_kfree;
 333         }
 334
 335         if (request_mem_region(info->phys_base, ONENAND_IO_SIZE,
 336                                pdev->dev.driver->name) == NULL) {
 337                 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
 338                         info->phys_base, ONENAND_IO_SIZE);
 339                 r = -EBUSY;
 340                 goto err_free_cs;
 341         }
 342         info->onenand.base = ioremap(info->phys_base, ONENAND_IO_SIZE);
 343         if (info->onenand.base == NULL) {
 344                 r = -ENOMEM;
 345                 goto err_release_mem_region;
 346         }
 347
 348         if (pdata->onenand_setup != NULL) {
 349                 r = pdata->onenand_setup(info->onenand.base);
 350                 if (r < 0) {
 351                         dev_err(&pdev->dev, "Onenand platform setup failed: %d\n", r);
 352                         goto err_iounmap;
 353                 }
 354         }
 355
 356         if (info->gpio_irq) {
 357                 if ((r = omap_request_gpio(info->gpio_irq)) < 0) {
 358                         dev_err(&pdev->dev,  "Failed to request GPIO%d for OneNAND\n",
 359                                 info->gpio_irq);
 360                         goto err_iounmap;
 361         }
 362         omap_set_gpio_direction(info->gpio_irq, 1);
 363
 364         if ((r = request_irq(OMAP_GPIO_IRQ(info->gpio_irq),
 365                              omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
 366                              pdev->dev.driver->name, info)) < 0)
 367                 goto err_release_gpio;
 368         }
 369
 370         if (info->dma_channel >= 0) {
 371                 r = omap_request_dma(0, pdev->dev.driver->name,
 372                                      omap2_onenand_dma_cb, (void *) info,
 373                                      &info->dma_channel);
 374                 if (r == 0) {
 375                         omap_set_dma_write_mode(info->dma_channel, OMAP_DMA_WRITE_NON_POSTED);
 376                         omap_set_dma_src_data_pack(info->dma_channel, 1);
 377                         omap_set_dma_src_burst_mode(info->dma_channel, OMAP_DMA_DATA_BURST_8);
 378                         omap_set_dma_dest_data_pack(info->dma_channel, 1);
 379                         omap_set_dma_dest_burst_mode(info->dma_channel, OMAP_DMA_DATA_BURST_8);
 380                 } else {
 381                         dev_info(&pdev->dev,
 382                                  "failed to allocate DMA for OneNAND, using PIO instead\n");
 383                         info->dma_channel = -1;
 384                 }
 385         }
 386
 387         dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual base %p\n",
 388                  info->gpmc_cs, info->phys_base, info->onenand.base);
 389
 390         info->pdev = pdev;
 391         info->mtd.name = pdev->dev.bus_id;
 392         info->mtd.priv = &info->onenand;
 393         info->mtd.owner = THIS_MODULE;
 394
 395         if (info->dma_channel >= 0) {
 396                 info->onenand.wait = omap2_onenand_wait;
 397                 info->onenand.read_bufferram = omap2_onenand_read_bufferram;
 398                 info->onenand.write_bufferram = omap2_onenand_write_bufferram;
 399         }
 400
 401         if ((r = onenand_scan(&info->mtd, 1)) < 0)
 402                 goto err_release_dma;
 403
 404 #ifdef CONFIG_MTD_PARTITIONS
 405         if (pdata->parts != NULL)
 406                 r = add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
 407         else
 408 #endif
 409                 r = add_mtd_device(&info->mtd);
 410         if (r < 0)
 411                 goto err_release_onenand;
 412
 413         platform_set_drvdata(pdev, info);
 414
 415         return 0;
 416
 417 err_release_onenand:
 418         onenand_release(&info->mtd);
 419 err_release_dma:
 420         if (info->dma_channel != -1)
 421                 omap_free_dma(info->dma_channel);
 422         if (info->gpio_irq)
 423                 free_irq(OMAP_GPIO_IRQ(info->gpio_irq), info);
 424 err_release_gpio:
 425         if (info->gpio_irq)
 426                 omap_free_gpio(info->gpio_irq);
 427 err_iounmap:
 428         iounmap(info->onenand.base);
 429 err_release_mem_region:
 430         release_mem_region(info->phys_base, ONENAND_IO_SIZE);
 431 err_free_cs:
 432         gpmc_cs_free(info->gpmc_cs);
 433 err_kfree:
 434         kfree(info);
 435
 436         return r;
 437 }
 438
 439 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
 440 {
 441         struct omap2_onenand *info = dev_get_drvdata(&pdev->dev);
 442
 443         BUG_ON(info == NULL);
 444
 445 #ifdef CONFIG_MTD_PARTITIONS
 446         if (info->parts)
 447                 del_mtd_partitions(&info->mtd);
 448         else
 449                 del_mtd_device(&info->mtd);
 450 #else
 451         del_mtd_device(&info->mtd);
 452 #endif
 453
 454         onenand_release(&info->mtd);
 455         if (info->dma_channel != -1)
 456                 omap_free_dma(info->dma_channel);
 457         omap2_onenand_shutdown(pdev);
 458         platform_set_drvdata(pdev, NULL);
 459         if (info->gpio_irq) {
 460                 free_irq(OMAP_GPIO_IRQ(info->gpio_irq), info);
 461                 omap_free_gpio(info->gpio_irq);
 462         }
 463         iounmap(info->onenand.base);
 464         release_mem_region(info->phys_base, ONENAND_IO_SIZE);
 465         kfree(info);
 466
 467         return 0;
 468 }
 469
 470 static struct platform_driver omap2_onenand_driver = {
 471         .probe          = omap2_onenand_probe,
 472         .remove         = omap2_onenand_remove,
 473         .shutdown       = omap2_onenand_shutdown,
 474         .driver         = {
 475                 .name   = "omap2-onenand",
 476                 .owner  = THIS_MODULE,
 477         },
 478 };
 479
 480 MODULE_ALIAS(DRIVER_NAME);
 481
 482 static int __init omap2_onenand_init(void)
 483 {
 484         printk(KERN_INFO "OMAP2 OneNAND driver initializing\n");
 485         return platform_driver_register(&omap2_onenand_driver);
 486 }
 487
 488 static void __exit omap2_onenand_exit(void)
 489 {
 490         platform_driver_unregister(&omap2_onenand_driver);
 491 }
 492
 493 module_init(omap2_onenand_init);
 494 module_exit(omap2_onenand_exit);
 495
 496 MODULE_LICENSE("GPL");
 497 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
 498 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2");