drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/pci.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/scatterlist.h>
  21
  22 #include <linux/leds.h>
  23
  24 #include <linux/mmc/host.h>
  25
  26 #include "sdhci.h"
  27
  28 #define DRIVER_NAME "sdhci"
  29
  30 #define DBG(f, x...) \
  31         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  32
  33 static unsigned int debug_quirks = 0;
  34
  35 /*
  36  * Different quirks to handle when the hardware deviates from a strict
  37  * interpretation of the SDHCI specification.
  38  */
  39
  40 /* Controller doesn't honor resets unless we touch the clock register */
  41 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
  42 /* Controller has bad caps bits, but really supports DMA */
  43 #define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
  44 /* Controller doesn't like to be reset when there is no card inserted. */
  45 #define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
  46 /* Controller doesn't like clearing the power reg before a change */
  47 #define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
  48 /* Controller has flaky internal state so reset it on each ios change */
  49 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1<<4)
  50 /* Controller has an unusable DMA engine */
  51 #define SDHCI_QUIRK_BROKEN_DMA                          (1<<5)
  52 /* Controller can only DMA from 32-bit aligned addresses */
  53 #define SDHCI_QUIRK_32BIT_DMA_ADDR                      (1<<6)
  54 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
  55 #define SDHCI_QUIRK_32BIT_DMA_SIZE                      (1<<7)
  56 /* Controller needs to be reset after each request to stay stable */
  57 #define SDHCI_QUIRK_RESET_AFTER_REQUEST                 (1<<8)
  58 /* Controller needs voltage and power writes to happen separately */
  59 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER             (1<<9)
  60 /* Controller has an off-by-one issue with timeout value */
  61 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL                (1<<10)
  62
  63 static const struct pci_device_id pci_ids[] __devinitdata = {
  64         {
  65                 .vendor         = PCI_VENDOR_ID_RICOH,
  66                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  67                 .subvendor      = PCI_VENDOR_ID_IBM,
  68                 .subdevice      = PCI_ANY_ID,
  69                 .driver_data    = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
  70                                   SDHCI_QUIRK_FORCE_DMA,
  71         },
  72
  73         {
  74                 .vendor         = PCI_VENDOR_ID_RICOH,
  75                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  76                 .subvendor      = PCI_VENDOR_ID_SAMSUNG,
  77                 .subdevice      = PCI_ANY_ID,
  78                 .driver_data    = SDHCI_QUIRK_FORCE_DMA |
  79                                   SDHCI_QUIRK_NO_CARD_NO_RESET,
  80         },
  81
  82         {
  83                 .vendor         = PCI_VENDOR_ID_RICOH,
  84                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  85                 .subvendor      = PCI_ANY_ID,
  86                 .subdevice      = PCI_ANY_ID,
  87                 .driver_data    = SDHCI_QUIRK_FORCE_DMA,
  88         },
  89
  90         {
  91                 .vendor         = PCI_VENDOR_ID_TI,
  92                 .device         = PCI_DEVICE_ID_TI_XX21_XX11_SD,
  93                 .subvendor      = PCI_ANY_ID,
  94                 .subdevice      = PCI_ANY_ID,
  95                 .driver_data    = SDHCI_QUIRK_FORCE_DMA,
  96         },
  97
  98         {
  99                 .vendor         = PCI_VENDOR_ID_ENE,
 100                 .device         = PCI_DEVICE_ID_ENE_CB712_SD,
 101                 .subvendor      = PCI_ANY_ID,
 102                 .subdevice      = PCI_ANY_ID,
 103                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
 104                                   SDHCI_QUIRK_BROKEN_DMA,
 105         },
 106
 107         {
 108                 .vendor         = PCI_VENDOR_ID_ENE,
 109                 .device         = PCI_DEVICE_ID_ENE_CB712_SD_2,
 110                 .subvendor      = PCI_ANY_ID,
 111                 .subdevice      = PCI_ANY_ID,
 112                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
 113                                   SDHCI_QUIRK_BROKEN_DMA,
 114         },
 115
 116         {
 117                 .vendor         = PCI_VENDOR_ID_ENE,
 118                 .device         = PCI_DEVICE_ID_ENE_CB714_SD,
 119                 .subvendor      = PCI_ANY_ID,
 120                 .subdevice      = PCI_ANY_ID,
 121                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
 122                                   SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
 123         },
 124
 125         {
 126                 .vendor         = PCI_VENDOR_ID_ENE,
 127                 .device         = PCI_DEVICE_ID_ENE_CB714_SD_2,
 128                 .subvendor      = PCI_ANY_ID,
 129                 .subdevice      = PCI_ANY_ID,
 130                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
 131                                   SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
 132         },
 133
 134         {
 135                 .vendor         = PCI_VENDOR_ID_MARVELL,
 136                 .device         = PCI_DEVICE_ID_MARVELL_CAFE_SD,
 137                 .subvendor      = PCI_ANY_ID,
 138                 .subdevice      = PCI_ANY_ID,
 139                 .driver_data    = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
 140                                   SDHCI_QUIRK_INCR_TIMEOUT_CONTROL,
 141         },
 142
 143         {
 144                 .vendor         = PCI_VENDOR_ID_JMICRON,
 145                 .device         = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
 146                 .subvendor      = PCI_ANY_ID,
 147                 .subdevice      = PCI_ANY_ID,
 148                 .driver_data    = SDHCI_QUIRK_32BIT_DMA_ADDR |
 149                                   SDHCI_QUIRK_32BIT_DMA_SIZE |
 150                                   SDHCI_QUIRK_RESET_AFTER_REQUEST,
 151         },
 152
 153         {       /* Generic SD host controller */
 154                 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
 155         },
 156
 157         { /* end: all zeroes */ },
 158 };
 159
 160 MODULE_DEVICE_TABLE(pci, pci_ids);
 161
 162 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
 163 static void sdhci_finish_data(struct sdhci_host *);
 164
 165 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
 166 static void sdhci_finish_command(struct sdhci_host *);
 167
 168 static void sdhci_dumpregs(struct sdhci_host *host)
 169 {
 170         printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
 171
 172         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
 173                 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
 174                 readw(host->ioaddr + SDHCI_HOST_VERSION));
 175         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
 176                 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
 177                 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
 178         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
 179                 readl(host->ioaddr + SDHCI_ARGUMENT),
 180                 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
 181         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
 182                 readl(host->ioaddr + SDHCI_PRESENT_STATE),
 183                 readb(host->ioaddr + SDHCI_HOST_CONTROL));
 184         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 185                 readb(host->ioaddr + SDHCI_POWER_CONTROL),
 186                 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
 187         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 188                 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
 189                 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
 190         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 191                 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
 192                 readl(host->ioaddr + SDHCI_INT_STATUS));
 193         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 194                 readl(host->ioaddr + SDHCI_INT_ENABLE),
 195                 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
 196         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 197                 readw(host->ioaddr + SDHCI_ACMD12_ERR),
 198                 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
 199         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
 200                 readl(host->ioaddr + SDHCI_CAPABILITIES),
 201                 readl(host->ioaddr + SDHCI_MAX_CURRENT));
 202
 203         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
 204 }
 205
 206 /*****************************************************************************\
 207  *                                                                           *
 208  * Low level functions                                                       *
 209  *                                                                           *
 210 \*****************************************************************************/
 211
 212 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 213 {
 214         unsigned long timeout;
 215
 216         if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 217                 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 218                         SDHCI_CARD_PRESENT))
 219                         return;
 220         }
 221
 222         writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
 223
 224         if (mask & SDHCI_RESET_ALL)
 225                 host->clock = 0;
 226
 227         /* Wait max 100 ms */
 228         timeout = 100;
 229
 230         /* hw clears the bit when it's done */
 231         while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
 232                 if (timeout == 0) {
 233                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 234                                 mmc_hostname(host->mmc), (int)mask);
 235                         sdhci_dumpregs(host);
 236                         return;
 237                 }
 238                 timeout--;
 239                 mdelay(1);
 240         }
 241 }
 242
 243 static void sdhci_init(struct sdhci_host *host)
 244 {
 245         u32 intmask;
 246
 247         sdhci_reset(host, SDHCI_RESET_ALL);
 248
 249         intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 250                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 251                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 252                 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
 253                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
 254                 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
 255
 256         writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
 257         writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 258 }
 259
 260 static void sdhci_activate_led(struct sdhci_host *host)
 261 {
 262         u8 ctrl;
 263
 264         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 265         ctrl |= SDHCI_CTRL_LED;
 266         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 267 }
 268
 269 static void sdhci_deactivate_led(struct sdhci_host *host)
 270 {
 271         u8 ctrl;
 272
 273         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 274         ctrl &= ~SDHCI_CTRL_LED;
 275         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 276 }
 277
 278 #ifdef CONFIG_LEDS_CLASS
 279 static void sdhci_led_control(struct led_classdev *led,
 280         enum led_brightness brightness)
 281 {
 282         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 283         unsigned long flags;
 284
 285         spin_lock_irqsave(&host->lock, flags);
 286
 287         if (brightness == LED_OFF)
 288                 sdhci_deactivate_led(host);
 289         else
 290                 sdhci_activate_led(host);
 291
 292         spin_unlock_irqrestore(&host->lock, flags);
 293 }
 294 #endif
 295
 296 /*****************************************************************************\
 297  *                                                                           *
 298  * Core functions                                                            *
 299  *                                                                           *
 300 \*****************************************************************************/
 301
 302 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
 303 {
 304         return sg_virt(host->cur_sg);
 305 }
 306
 307 static inline int sdhci_next_sg(struct sdhci_host* host)
 308 {
 309         /*
 310          * Skip to next SG entry.
 311          */
 312         host->cur_sg++;
 313         host->num_sg--;
 314
 315         /*
 316          * Any entries left?
 317          */
 318         if (host->num_sg > 0) {
 319                 host->offset = 0;
 320                 host->remain = host->cur_sg->length;
 321         }
 322
 323         return host->num_sg;
 324 }
 325
 326 static void sdhci_read_block_pio(struct sdhci_host *host)
 327 {
 328         int blksize, chunk_remain;
 329         u32 data;
 330         char *buffer;
 331         int size;
 332
 333         DBG("PIO reading\n");
 334
 335         blksize = host->data->blksz;
 336         chunk_remain = 0;
 337         data = 0;
 338
 339         buffer = sdhci_sg_to_buffer(host) + host->offset;
 340
 341         while (blksize) {
 342                 if (chunk_remain == 0) {
 343                         data = readl(host->ioaddr + SDHCI_BUFFER);
 344                         chunk_remain = min(blksize, 4);
 345                 }
 346
 347                 size = min(host->remain, chunk_remain);
 348
 349                 chunk_remain -= size;
 350                 blksize -= size;
 351                 host->offset += size;
 352                 host->remain -= size;
 353
 354                 while (size) {
 355                         *buffer = data & 0xFF;
 356                         buffer++;
 357                         data >>= 8;
 358                         size--;
 359                 }
 360
 361                 if (host->remain == 0) {
 362                         if (sdhci_next_sg(host) == 0) {
 363                                 BUG_ON(blksize != 0);
 364                                 return;
 365                         }
 366                         buffer = sdhci_sg_to_buffer(host);
 367                 }
 368         }
 369 }
 370
 371 static void sdhci_write_block_pio(struct sdhci_host *host)
 372 {
 373         int blksize, chunk_remain;
 374         u32 data;
 375         char *buffer;
 376         int bytes, size;
 377
 378         DBG("PIO writing\n");
 379
 380         blksize = host->data->blksz;
 381         chunk_remain = 4;
 382         data = 0;
 383
 384         bytes = 0;
 385         buffer = sdhci_sg_to_buffer(host) + host->offset;
 386
 387         while (blksize) {
 388                 size = min(host->remain, chunk_remain);
 389
 390                 chunk_remain -= size;
 391                 blksize -= size;
 392                 host->offset += size;
 393                 host->remain -= size;
 394
 395                 while (size) {
 396                         data >>= 8;
 397                         data |= (u32)*buffer << 24;
 398                         buffer++;
 399                         size--;
 400                 }
 401
 402                 if (chunk_remain == 0) {
 403                         writel(data, host->ioaddr + SDHCI_BUFFER);
 404                         chunk_remain = min(blksize, 4);
 405                 }
 406
 407                 if (host->remain == 0) {
 408                         if (sdhci_next_sg(host) == 0) {
 409                                 BUG_ON(blksize != 0);
 410                                 return;
 411                         }
 412                         buffer = sdhci_sg_to_buffer(host);
 413                 }
 414         }
 415 }
 416
 417 static void sdhci_transfer_pio(struct sdhci_host *host)
 418 {
 419         u32 mask;
 420
 421         BUG_ON(!host->data);
 422
 423         if (host->num_sg == 0)
 424                 return;
 425
 426         if (host->data->flags & MMC_DATA_READ)
 427                 mask = SDHCI_DATA_AVAILABLE;
 428         else
 429                 mask = SDHCI_SPACE_AVAILABLE;
 430
 431         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 432                 if (host->data->flags & MMC_DATA_READ)
 433                         sdhci_read_block_pio(host);
 434                 else
 435                         sdhci_write_block_pio(host);
 436
 437                 if (host->num_sg == 0)
 438                         break;
 439         }
 440
 441         DBG("PIO transfer complete.\n");
 442 }
 443
 444 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 445 {
 446         u8 count;
 447         unsigned target_timeout, current_timeout;
 448
 449         WARN_ON(host->data);
 450
 451         if (data == NULL)
 452                 return;
 453
 454         /* Sanity checks */
 455         BUG_ON(data->blksz * data->blocks > 524288);
 456         BUG_ON(data->blksz > host->mmc->max_blk_size);
 457         BUG_ON(data->blocks > 65535);
 458
 459         host->data = data;
 460         host->data_early = 0;
 461
 462         /* timeout in us */
 463         target_timeout = data->timeout_ns / 1000 +
 464                 data->timeout_clks / host->clock;
 465
 466         /*
 467          * Figure out needed cycles.
 468          * We do this in steps in order to fit inside a 32 bit int.
 469          * The first step is the minimum timeout, which will have a
 470          * minimum resolution of 6 bits:
 471          * (1) 2^13*1000 > 2^22,
 472          * (2) host->timeout_clk < 2^16
 473          *     =>
 474          *     (1) / (2) > 2^6
 475          */
 476         count = 0;
 477         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 478         while (current_timeout < target_timeout) {
 479                 count++;
 480                 current_timeout <<= 1;
 481                 if (count >= 0xF)
 482                         break;
 483         }
 484
 485         /*
 486          * Compensate for an off-by-one error in the CaFe hardware; otherwise,
 487          * a too-small count gives us interrupt timeouts.
 488          */
 489         if ((host->chip->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL))
 490                 count++;
 491
 492         if (count >= 0xF) {
 493                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
 494                         mmc_hostname(host->mmc));
 495                 count = 0xE;
 496         }
 497
 498         writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
 499
 500         if (host->flags & SDHCI_USE_DMA)
 501                 host->flags |= SDHCI_REQ_USE_DMA;
 502
 503         if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
 504                 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
 505                 ((data->blksz * data->blocks) & 0x3))) {
 506                 DBG("Reverting to PIO because of transfer size (%d)\n",
 507                         data->blksz * data->blocks);
 508                 host->flags &= ~SDHCI_REQ_USE_DMA;
 509         }
 510
 511         /*
 512          * The assumption here being that alignment is the same after
 513          * translation to device address space.
 514          */
 515         if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
 516                 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 517                 (data->sg->offset & 0x3))) {
 518                 DBG("Reverting to PIO because of bad alignment\n");
 519                 host->flags &= ~SDHCI_REQ_USE_DMA;
 520         }
 521
 522         if (host->flags & SDHCI_REQ_USE_DMA) {
 523                 int count;
 524
 525                 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
 526                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 527                 BUG_ON(count != 1);
 528
 529                 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
 530         } else {
 531                 host->cur_sg = data->sg;
 532                 host->num_sg = data->sg_len;
 533
 534                 host->offset = 0;
 535                 host->remain = host->cur_sg->length;
 536         }
 537
 538         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
 539         writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
 540                 host->ioaddr + SDHCI_BLOCK_SIZE);
 541         writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
 542 }
 543
 544 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 545         struct mmc_data *data)
 546 {
 547         u16 mode;
 548
 549         if (data == NULL)
 550                 return;
 551
 552         WARN_ON(!host->data);
 553
 554         mode = SDHCI_TRNS_BLK_CNT_EN;
 555         if (data->blocks > 1)
 556                 mode |= SDHCI_TRNS_MULTI;
 557         if (data->flags & MMC_DATA_READ)
 558                 mode |= SDHCI_TRNS_READ;
 559         if (host->flags & SDHCI_REQ_USE_DMA)
 560                 mode |= SDHCI_TRNS_DMA;
 561
 562         writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
 563 }
 564
 565 static void sdhci_finish_data(struct sdhci_host *host)
 566 {
 567         struct mmc_data *data;
 568         u16 blocks;
 569
 570         BUG_ON(!host->data);
 571
 572         data = host->data;
 573         host->data = NULL;
 574
 575         if (host->flags & SDHCI_REQ_USE_DMA) {
 576                 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
 577                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 578         }
 579
 580         /*
 581          * Controller doesn't count down when in single block mode.
 582          */
 583         if (data->blocks == 1)
 584                 blocks = (data->error == 0) ? 0 : 1;
 585         else
 586                 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
 587         data->bytes_xfered = data->blksz * (data->blocks - blocks);
 588
 589         if (!data->error && blocks) {
 590                 printk(KERN_ERR "%s: Controller signalled completion even "
 591                         "though there were blocks left.\n",
 592                         mmc_hostname(host->mmc));
 593                 data->error = -EIO;
 594         }
 595
 596         if (data->stop) {
 597                 /*
 598                  * The controller needs a reset of internal state machines
 599                  * upon error conditions.
 600                  */
 601                 if (data->error) {
 602                         sdhci_reset(host, SDHCI_RESET_CMD);
 603                         sdhci_reset(host, SDHCI_RESET_DATA);
 604                 }
 605
 606                 sdhci_send_command(host, data->stop);
 607         } else
 608                 tasklet_schedule(&host->finish_tasklet);
 609 }
 610
 611 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 612 {
 613         int flags;
 614         u32 mask;
 615         unsigned long timeout;
 616
 617         WARN_ON(host->cmd);
 618
 619         /* Wait max 10 ms */
 620         timeout = 10;
 621
 622         mask = SDHCI_CMD_INHIBIT;
 623         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 624                 mask |= SDHCI_DATA_INHIBIT;
 625
 626         /* We shouldn't wait for data inihibit for stop commands, even
 627            though they might use busy signaling */
 628         if (host->mrq->data && (cmd == host->mrq->data->stop))
 629                 mask &= ~SDHCI_DATA_INHIBIT;
 630
 631         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 632                 if (timeout == 0) {
 633                         printk(KERN_ERR "%s: Controller never released "
 634                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 635                         sdhci_dumpregs(host);
 636                         cmd->error = -EIO;
 637                         tasklet_schedule(&host->finish_tasklet);
 638                         return;
 639                 }
 640                 timeout--;
 641                 mdelay(1);
 642         }
 643
 644         mod_timer(&host->timer, jiffies + 10 * HZ);
 645
 646         host->cmd = cmd;
 647
 648         sdhci_prepare_data(host, cmd->data);
 649
 650         writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
 651
 652         sdhci_set_transfer_mode(host, cmd->data);
 653
 654         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 655                 printk(KERN_ERR "%s: Unsupported response type!\n",
 656                         mmc_hostname(host->mmc));
 657                 cmd->error = -EINVAL;
 658                 tasklet_schedule(&host->finish_tasklet);
 659                 return;
 660         }
 661
 662         if (!(cmd->flags & MMC_RSP_PRESENT))
 663                 flags = SDHCI_CMD_RESP_NONE;
 664         else if (cmd->flags & MMC_RSP_136)
 665                 flags = SDHCI_CMD_RESP_LONG;
 666         else if (cmd->flags & MMC_RSP_BUSY)
 667                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 668         else
 669                 flags = SDHCI_CMD_RESP_SHORT;
 670
 671         if (cmd->flags & MMC_RSP_CRC)
 672                 flags |= SDHCI_CMD_CRC;
 673         if (cmd->flags & MMC_RSP_OPCODE)
 674                 flags |= SDHCI_CMD_INDEX;
 675         if (cmd->data)
 676                 flags |= SDHCI_CMD_DATA;
 677
 678         writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
 679                 host->ioaddr + SDHCI_COMMAND);
 680 }
 681
 682 static void sdhci_finish_command(struct sdhci_host *host)
 683 {
 684         int i;
 685
 686         BUG_ON(host->cmd == NULL);
 687
 688         if (host->cmd->flags & MMC_RSP_PRESENT) {
 689                 if (host->cmd->flags & MMC_RSP_136) {
 690                         /* CRC is stripped so we need to do some shifting. */
 691                         for (i = 0;i < 4;i++) {
 692                                 host->cmd->resp[i] = readl(host->ioaddr +
 693                                         SDHCI_RESPONSE + (3-i)*4) << 8;
 694                                 if (i != 3)
 695                                         host->cmd->resp[i] |=
 696                                                 readb(host->ioaddr +
 697                                                 SDHCI_RESPONSE + (3-i)*4-1);
 698                         }
 699                 } else {
 700                         host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
 701                 }
 702         }
 703
 704         host->cmd->error = 0;
 705
 706         if (host->data && host->data_early)
 707                 sdhci_finish_data(host);
 708
 709         if (!host->cmd->data)
 710                 tasklet_schedule(&host->finish_tasklet);
 711
 712         host->cmd = NULL;
 713 }
 714
 715 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 716 {
 717         int div;
 718         u16 clk;
 719         unsigned long timeout;
 720
 721         if (clock == host->clock)
 722                 return;
 723
 724         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
 725
 726         if (clock == 0)
 727                 goto out;
 728
 729         for (div = 1;div < 256;div *= 2) {
 730                 if ((host->max_clk / div) <= clock)
 731                         break;
 732         }
 733         div >>= 1;
 734
 735         clk = div << SDHCI_DIVIDER_SHIFT;
 736         clk |= SDHCI_CLOCK_INT_EN;
 737         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 738
 739         /* Wait max 10 ms */
 740         timeout = 10;
 741         while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
 742                 & SDHCI_CLOCK_INT_STABLE)) {
 743                 if (timeout == 0) {
 744                         printk(KERN_ERR "%s: Internal clock never "
 745                                 "stabilised.\n", mmc_hostname(host->mmc));
 746                         sdhci_dumpregs(host);
 747                         return;
 748                 }
 749                 timeout--;
 750                 mdelay(1);
 751         }
 752
 753         clk |= SDHCI_CLOCK_CARD_EN;
 754         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 755
 756 out:
 757         host->clock = clock;
 758 }
 759
 760 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 761 {
 762         u8 pwr;
 763
 764         if (host->power == power)
 765                 return;
 766
 767         if (power == (unsigned short)-1) {
 768                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 769                 goto out;
 770         }
 771
 772         /*
 773          * Spec says that we should clear the power reg before setting
 774          * a new value. Some controllers don't seem to like this though.
 775          */
 776         if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
 777                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 778
 779         pwr = SDHCI_POWER_ON;
 780
 781         switch (1 << power) {
 782         case MMC_VDD_165_195:
 783                 pwr |= SDHCI_POWER_180;
 784                 break;
 785         case MMC_VDD_29_30:
 786         case MMC_VDD_30_31:
 787                 pwr |= SDHCI_POWER_300;
 788                 break;
 789         case MMC_VDD_32_33:
 790         case MMC_VDD_33_34:
 791                 pwr |= SDHCI_POWER_330;
 792                 break;
 793         default:
 794                 BUG();
 795         }
 796
 797         /*
 798          * At least the CaFe chip gets confused if we set the voltage
 799          * and set turn on power at the same time, so set the voltage first.
 800          */
 801         if ((host->chip->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
 802                 writeb(pwr & ~SDHCI_POWER_ON,
 803                                 host->ioaddr + SDHCI_POWER_CONTROL);
 804
 805         writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
 806
 807 out:
 808         host->power = power;
 809 }
 810
 811 /*****************************************************************************\
 812  *                                                                           *
 813  * MMC callbacks                                                             *
 814  *                                                                           *
 815 \*****************************************************************************/
 816
 817 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 818 {
 819         struct sdhci_host *host;
 820         unsigned long flags;
 821
 822         host = mmc_priv(mmc);
 823
 824         spin_lock_irqsave(&host->lock, flags);
 825
 826         WARN_ON(host->mrq != NULL);
 827
 828 #ifndef CONFIG_LEDS_CLASS
 829         sdhci_activate_led(host);
 830 #endif
 831
 832         host->mrq = mrq;
 833
 834         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 835                 host->mrq->cmd->error = -ENOMEDIUM;
 836                 tasklet_schedule(&host->finish_tasklet);
 837         } else
 838                 sdhci_send_command(host, mrq->cmd);
 839
 840         mmiowb();
 841         spin_unlock_irqrestore(&host->lock, flags);
 842 }
 843
 844 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 845 {
 846         struct sdhci_host *host;
 847         unsigned long flags;
 848         u8 ctrl;
 849
 850         host = mmc_priv(mmc);
 851
 852         spin_lock_irqsave(&host->lock, flags);
 853
 854         /*
 855          * Reset the chip on each power off.
 856          * Should clear out any weird states.
 857          */
 858         if (ios->power_mode == MMC_POWER_OFF) {
 859                 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 860                 sdhci_init(host);
 861         }
 862
 863         sdhci_set_clock(host, ios->clock);
 864
 865         if (ios->power_mode == MMC_POWER_OFF)
 866                 sdhci_set_power(host, -1);
 867         else
 868                 sdhci_set_power(host, ios->vdd);
 869
 870         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 871
 872         if (ios->bus_width == MMC_BUS_WIDTH_4)
 873                 ctrl |= SDHCI_CTRL_4BITBUS;
 874         else
 875                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 876
 877         if (ios->timing == MMC_TIMING_SD_HS)
 878                 ctrl |= SDHCI_CTRL_HISPD;
 879         else
 880                 ctrl &= ~SDHCI_CTRL_HISPD;
 881
 882         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 883
 884         /*
 885          * Some (ENE) controllers go apeshit on some ios operation,
 886          * signalling timeout and CRC errors even on CMD0. Resetting
 887          * it on each ios seems to solve the problem.
 888          */
 889         if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
 890                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 891
 892         mmiowb();
 893         spin_unlock_irqrestore(&host->lock, flags);
 894 }
 895
 896 static int sdhci_get_ro(struct mmc_host *mmc)
 897 {
 898         struct sdhci_host *host;
 899         unsigned long flags;
 900         int present;
 901
 902         host = mmc_priv(mmc);
 903
 904         spin_lock_irqsave(&host->lock, flags);
 905
 906         present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
 907
 908         spin_unlock_irqrestore(&host->lock, flags);
 909
 910         return !(present & SDHCI_WRITE_PROTECT);
 911 }
 912
 913 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
 914 {
 915         struct sdhci_host *host;
 916         unsigned long flags;
 917         u32 ier;
 918
 919         host = mmc_priv(mmc);
 920
 921         spin_lock_irqsave(&host->lock, flags);
 922
 923         ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
 924
 925         ier &= ~SDHCI_INT_CARD_INT;
 926         if (enable)
 927                 ier |= SDHCI_INT_CARD_INT;
 928
 929         writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
 930         writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 931
 932         mmiowb();
 933
 934         spin_unlock_irqrestore(&host->lock, flags);
 935 }
 936
 937 static const struct mmc_host_ops sdhci_ops = {
 938         .request        = sdhci_request,
 939         .set_ios        = sdhci_set_ios,
 940         .get_ro         = sdhci_get_ro,
 941         .enable_sdio_irq = sdhci_enable_sdio_irq,
 942 };
 943
 944 /*****************************************************************************\
 945  *                                                                           *
 946  * Tasklets                                                                  *
 947  *                                                                           *
 948 \*****************************************************************************/
 949
 950 static void sdhci_tasklet_card(unsigned long param)
 951 {
 952         struct sdhci_host *host;
 953         unsigned long flags;
 954
 955         host = (struct sdhci_host*)param;
 956
 957         spin_lock_irqsave(&host->lock, flags);
 958
 959         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 960                 if (host->mrq) {
 961                         printk(KERN_ERR "%s: Card removed during transfer!\n",
 962                                 mmc_hostname(host->mmc));
 963                         printk(KERN_ERR "%s: Resetting controller.\n",
 964                                 mmc_hostname(host->mmc));
 965
 966                         sdhci_reset(host, SDHCI_RESET_CMD);
 967                         sdhci_reset(host, SDHCI_RESET_DATA);
 968
 969                         host->mrq->cmd->error = -ENOMEDIUM;
 970                         tasklet_schedule(&host->finish_tasklet);
 971                 }
 972         }
 973
 974         spin_unlock_irqrestore(&host->lock, flags);
 975
 976         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
 977 }
 978
 979 static void sdhci_tasklet_finish(unsigned long param)
 980 {
 981         struct sdhci_host *host;
 982         unsigned long flags;
 983         struct mmc_request *mrq;
 984
 985         host = (struct sdhci_host*)param;
 986
 987         spin_lock_irqsave(&host->lock, flags);
 988
 989         del_timer(&host->timer);
 990
 991         mrq = host->mrq;
 992
 993         /*
 994          * The controller needs a reset of internal state machines
 995          * upon error conditions.
 996          */
 997         if (mrq->cmd->error ||
 998                 (mrq->data && (mrq->data->error ||
 999                 (mrq->data->stop && mrq->data->stop->error))) ||
1000                 (host->chip->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1001
1002                 /* Some controllers need this kick or reset won't work here */
1003                 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1004                         unsigned int clock;
1005
1006                         /* This is to force an update */
1007                         clock = host->clock;
1008                         host->clock = 0;
1009                         sdhci_set_clock(host, clock);
1010                 }
1011
1012                 /* Spec says we should do both at the same time, but Ricoh
1013                    controllers do not like that. */
1014                 sdhci_reset(host, SDHCI_RESET_CMD);
1015                 sdhci_reset(host, SDHCI_RESET_DATA);
1016         }
1017
1018         host->mrq = NULL;
1019         host->cmd = NULL;
1020         host->data = NULL;
1021
1022 #ifndef CONFIG_LEDS_CLASS
1023         sdhci_deactivate_led(host);
1024 #endif
1025
1026         mmiowb();
1027         spin_unlock_irqrestore(&host->lock, flags);
1028
1029         mmc_request_done(host->mmc, mrq);
1030 }
1031
1032 static void sdhci_timeout_timer(unsigned long data)
1033 {
1034         struct sdhci_host *host;
1035         unsigned long flags;
1036
1037         host = (struct sdhci_host*)data;
1038
1039         spin_lock_irqsave(&host->lock, flags);
1040
1041         if (host->mrq) {
1042                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1043                         "interrupt.\n", mmc_hostname(host->mmc));
1044                 sdhci_dumpregs(host);
1045
1046                 if (host->data) {
1047                         host->data->error = -ETIMEDOUT;
1048                         sdhci_finish_data(host);
1049                 } else {
1050                         if (host->cmd)
1051                                 host->cmd->error = -ETIMEDOUT;
1052                         else
1053                                 host->mrq->cmd->error = -ETIMEDOUT;
1054
1055                         tasklet_schedule(&host->finish_tasklet);
1056                 }
1057         }
1058
1059         mmiowb();
1060         spin_unlock_irqrestore(&host->lock, flags);
1061 }
1062
1063 /*****************************************************************************\
1064  *                                                                           *
1065  * Interrupt handling                                                        *
1066  *                                                                           *
1067 \*****************************************************************************/
1068
1069 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1070 {
1071         BUG_ON(intmask == 0);
1072
1073         if (!host->cmd) {
1074                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1075                         "though no command operation was in progress.\n",
1076                         mmc_hostname(host->mmc), (unsigned)intmask);
1077                 sdhci_dumpregs(host);
1078                 return;
1079         }
1080
1081         if (intmask & SDHCI_INT_TIMEOUT)
1082                 host->cmd->error = -ETIMEDOUT;
1083         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1084                         SDHCI_INT_INDEX))
1085                 host->cmd->error = -EILSEQ;
1086
1087         if (host->cmd->error)
1088                 tasklet_schedule(&host->finish_tasklet);
1089         else if (intmask & SDHCI_INT_RESPONSE)
1090                 sdhci_finish_command(host);
1091 }
1092
1093 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1094 {
1095         BUG_ON(intmask == 0);
1096
1097         if (!host->data) {
1098                 /*
1099                  * A data end interrupt is sent together with the response
1100                  * for the stop command.
1101                  */
1102                 if (intmask & SDHCI_INT_DATA_END)
1103                         return;
1104
1105                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1106                         "though no data operation was in progress.\n",
1107                         mmc_hostname(host->mmc), (unsigned)intmask);
1108                 sdhci_dumpregs(host);
1109
1110                 return;
1111         }
1112
1113         if (intmask & SDHCI_INT_DATA_TIMEOUT)
1114                 host->data->error = -ETIMEDOUT;
1115         else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1116                 host->data->error = -EILSEQ;
1117
1118         if (host->data->error)
1119                 sdhci_finish_data(host);
1120         else {
1121                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1122                         sdhci_transfer_pio(host);
1123
1124                 /*
1125                  * We currently don't do anything fancy with DMA
1126                  * boundaries, but as we can't disable the feature
1127                  * we need to at least restart the transfer.
1128                  */
1129                 if (intmask & SDHCI_INT_DMA_END)
1130                         writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1131                                 host->ioaddr + SDHCI_DMA_ADDRESS);
1132
1133                 if (intmask & SDHCI_INT_DATA_END) {
1134                         if (host->cmd) {
1135                                 /*
1136                                  * Data managed to finish before the
1137                                  * command completed. Make sure we do
1138                                  * things in the proper order.
1139                                  */
1140                                 host->data_early = 1;
1141                         } else {
1142                                 sdhci_finish_data(host);
1143                         }
1144                 }
1145         }
1146 }
1147
1148 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1149 {
1150         irqreturn_t result;
1151         struct sdhci_host* host = dev_id;
1152         u32 intmask;
1153         int cardint = 0;
1154
1155         spin_lock(&host->lock);
1156
1157         intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1158
1159         if (!intmask || intmask == 0xffffffff) {
1160                 result = IRQ_NONE;
1161                 goto out;
1162         }
1163
1164         DBG("*** %s got interrupt: 0x%08x\n",
1165                 mmc_hostname(host->mmc), intmask);
1166
1167         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1168                 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1169                         host->ioaddr + SDHCI_INT_STATUS);
1170                 tasklet_schedule(&host->card_tasklet);
1171         }
1172
1173         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1174
1175         if (intmask & SDHCI_INT_CMD_MASK) {
1176                 writel(intmask & SDHCI_INT_CMD_MASK,
1177                         host->ioaddr + SDHCI_INT_STATUS);
1178                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1179         }
1180
1181         if (intmask & SDHCI_INT_DATA_MASK) {
1182                 writel(intmask & SDHCI_INT_DATA_MASK,
1183                         host->ioaddr + SDHCI_INT_STATUS);
1184                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1185         }
1186
1187         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1188
1189         intmask &= ~SDHCI_INT_ERROR;
1190
1191         if (intmask & SDHCI_INT_BUS_POWER) {
1192                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1193                         mmc_hostname(host->mmc));
1194                 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1195         }
1196
1197         intmask &= ~SDHCI_INT_BUS_POWER;
1198
1199         if (intmask & SDHCI_INT_CARD_INT)
1200                 cardint = 1;
1201
1202         intmask &= ~SDHCI_INT_CARD_INT;
1203
1204         if (intmask) {
1205                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1206                         mmc_hostname(host->mmc), intmask);
1207                 sdhci_dumpregs(host);
1208
1209                 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1210         }
1211
1212         result = IRQ_HANDLED;
1213
1214         mmiowb();
1215 out:
1216         spin_unlock(&host->lock);
1217
1218         /*
1219          * We have to delay this as it calls back into the driver.
1220          */
1221         if (cardint)
1222                 mmc_signal_sdio_irq(host->mmc);
1223
1224         return result;
1225 }
1226
1227 /*****************************************************************************\
1228  *                                                                           *
1229  * Suspend/resume                                                            *
1230  *                                                                           *
1231 \*****************************************************************************/
1232
1233 #ifdef CONFIG_PM
1234
1235 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1236 {
1237         struct sdhci_chip *chip;
1238         int i, ret;
1239
1240         chip = pci_get_drvdata(pdev);
1241         if (!chip)
1242                 return 0;
1243
1244         DBG("Suspending...\n");
1245
1246         for (i = 0;i < chip->num_slots;i++) {
1247                 if (!chip->hosts[i])
1248                         continue;
1249                 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1250                 if (ret) {
1251                         for (i--;i >= 0;i--)
1252                                 mmc_resume_host(chip->hosts[i]->mmc);
1253                         return ret;
1254                 }
1255         }
1256
1257         pci_save_state(pdev);
1258         pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1259
1260         for (i = 0;i < chip->num_slots;i++) {
1261                 if (!chip->hosts[i])
1262                         continue;
1263                 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1264         }
1265
1266         pci_disable_device(pdev);
1267         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1268
1269         return 0;
1270 }
1271
1272 static int sdhci_resume (struct pci_dev *pdev)
1273 {
1274         struct sdhci_chip *chip;
1275         int i, ret;
1276
1277         chip = pci_get_drvdata(pdev);
1278         if (!chip)
1279                 return 0;
1280
1281         DBG("Resuming...\n");
1282
1283         pci_set_power_state(pdev, PCI_D0);
1284         pci_restore_state(pdev);
1285         ret = pci_enable_device(pdev);
1286         if (ret)
1287                 return ret;
1288
1289         for (i = 0;i < chip->num_slots;i++) {
1290                 if (!chip->hosts[i])
1291                         continue;
1292                 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1293                         pci_set_master(pdev);
1294                 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1295                         IRQF_SHARED, mmc_hostname(chip->hosts[i]->mmc),
1296                         chip->hosts[i]);
1297                 if (ret)
1298                         return ret;
1299                 sdhci_init(chip->hosts[i]);
1300                 mmiowb();
1301                 ret = mmc_resume_host(chip->hosts[i]->mmc);
1302                 if (ret)
1303                         return ret;
1304         }
1305
1306         return 0;
1307 }
1308
1309 #else /* CONFIG_PM */
1310
1311 #define sdhci_suspend NULL
1312 #define sdhci_resume NULL
1313
1314 #endif /* CONFIG_PM */
1315
1316 /*****************************************************************************\
1317  *                                                                           *
1318  * Device probing/removal                                                    *
1319  *                                                                           *
1320 \*****************************************************************************/
1321
1322 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1323 {
1324         int ret;
1325         unsigned int version;
1326         struct sdhci_chip *chip;
1327         struct mmc_host *mmc;
1328         struct sdhci_host *host;
1329
1330         u8 first_bar;
1331         unsigned int caps;
1332
1333         chip = pci_get_drvdata(pdev);
1334         BUG_ON(!chip);
1335
1336         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1337         if (ret)
1338                 return ret;
1339
1340         first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1341
1342         if (first_bar > 5) {
1343                 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1344                 return -ENODEV;
1345         }
1346
1347         if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1348                 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1349                 return -ENODEV;
1350         }
1351
1352         if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1353                 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1354                         "You may experience problems.\n");
1355         }
1356
1357         if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1358                 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1359                 return -ENODEV;
1360         }
1361
1362         if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1363                 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1364                 return -ENODEV;
1365         }
1366
1367         mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1368         if (!mmc)
1369                 return -ENOMEM;
1370
1371         host = mmc_priv(mmc);
1372         host->mmc = mmc;
1373
1374         host->chip = chip;
1375         chip->hosts[slot] = host;
1376
1377         host->bar = first_bar + slot;
1378
1379         host->addr = pci_resource_start(pdev, host->bar);
1380         host->irq = pdev->irq;
1381
1382         DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1383
1384         ret = pci_request_region(pdev, host->bar, mmc_hostname(mmc));
1385         if (ret)
1386                 goto free;
1387
1388         host->ioaddr = ioremap_nocache(host->addr,
1389                 pci_resource_len(pdev, host->bar));
1390         if (!host->ioaddr) {
1391                 ret = -ENOMEM;
1392                 goto release;
1393         }
1394
1395         sdhci_reset(host, SDHCI_RESET_ALL);
1396
1397         version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1398         version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1399         if (version > 1) {
1400                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1401                         "You may experience problems.\n", mmc_hostname(mmc),
1402                         version);
1403         }
1404
1405         caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1406
1407         if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1408                 host->flags |= SDHCI_USE_DMA;
1409         else if (!(caps & SDHCI_CAN_DO_DMA))
1410                 DBG("Controller doesn't have DMA capability\n");
1411         else
1412                 host->flags |= SDHCI_USE_DMA;
1413
1414         if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1415                 (host->flags & SDHCI_USE_DMA)) {
1416                 DBG("Disabling DMA as it is marked broken\n");
1417                 host->flags &= ~SDHCI_USE_DMA;
1418         }
1419
1420         if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1421                 (host->flags & SDHCI_USE_DMA)) {
1422                 printk(KERN_WARNING "%s: Will use DMA "
1423                         "mode even though HW doesn't fully "
1424                         "claim to support it.\n", mmc_hostname(mmc));
1425         }
1426
1427         if (host->flags & SDHCI_USE_DMA) {
1428                 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1429                         printk(KERN_WARNING "%s: No suitable DMA available. "
1430                                 "Falling back to PIO.\n", mmc_hostname(mmc));
1431                         host->flags &= ~SDHCI_USE_DMA;
1432                 }
1433         }
1434
1435         if (host->flags & SDHCI_USE_DMA)
1436                 pci_set_master(pdev);
1437         else /* XXX: Hack to get MMC layer to avoid highmem */
1438                 pdev->dma_mask = 0;
1439
1440         host->max_clk =
1441                 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1442         if (host->max_clk == 0) {
1443                 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1444                         "frequency.\n", mmc_hostname(mmc));
1445                 ret = -ENODEV;
1446                 goto unmap;
1447         }
1448         host->max_clk *= 1000000;
1449
1450         host->timeout_clk =
1451                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1452         if (host->timeout_clk == 0) {
1453                 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1454                         "frequency.\n", mmc_hostname(mmc));
1455                 ret = -ENODEV;
1456                 goto unmap;
1457         }
1458         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1459                 host->timeout_clk *= 1000;
1460
1461         /*
1462          * Set host parameters.
1463          */
1464         mmc->ops = &sdhci_ops;
1465         mmc->f_min = host->max_clk / 256;
1466         mmc->f_max = host->max_clk;
1467         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ;
1468
1469         if (caps & SDHCI_CAN_DO_HISPD)
1470                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1471
1472         mmc->ocr_avail = 0;
1473         if (caps & SDHCI_CAN_VDD_330)
1474                 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1475         if (caps & SDHCI_CAN_VDD_300)
1476                 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1477         if (caps & SDHCI_CAN_VDD_180)
1478                 mmc->ocr_avail |= MMC_VDD_165_195;
1479
1480         if (mmc->ocr_avail == 0) {
1481                 printk(KERN_ERR "%s: Hardware doesn't report any "
1482                         "support voltages.\n", mmc_hostname(mmc));
1483                 ret = -ENODEV;
1484                 goto unmap;
1485         }
1486
1487         spin_lock_init(&host->lock);
1488
1489         /*
1490          * Maximum number of segments. Hardware cannot do scatter lists.
1491          */
1492         if (host->flags & SDHCI_USE_DMA)
1493                 mmc->max_hw_segs = 1;
1494         else
1495                 mmc->max_hw_segs = 16;
1496         mmc->max_phys_segs = 16;
1497
1498         /*
1499          * Maximum number of sectors in one transfer. Limited by DMA boundary
1500          * size (512KiB).
1501          */
1502         mmc->max_req_size = 524288;
1503
1504         /*
1505          * Maximum segment size. Could be one segment with the maximum number
1506          * of bytes.
1507          */
1508         mmc->max_seg_size = mmc->max_req_size;
1509
1510         /*
1511          * Maximum block size. This varies from controller to controller and
1512          * is specified in the capabilities register.
1513          */
1514         mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1515         if (mmc->max_blk_size >= 3) {
1516                 printk(KERN_WARNING "%s: Invalid maximum block size, "
1517                         "assuming 512 bytes\n", mmc_hostname(mmc));
1518                 mmc->max_blk_size = 512;
1519         } else
1520                 mmc->max_blk_size = 512 << mmc->max_blk_size;
1521
1522         /*
1523          * Maximum block count.
1524          */
1525         mmc->max_blk_count = 65535;
1526
1527         /*
1528          * Init tasklets.
1529          */
1530         tasklet_init(&host->card_tasklet,
1531                 sdhci_tasklet_card, (unsigned long)host);
1532         tasklet_init(&host->finish_tasklet,
1533                 sdhci_tasklet_finish, (unsigned long)host);
1534
1535         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1536
1537         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1538                 mmc_hostname(mmc), host);
1539         if (ret)
1540                 goto untasklet;
1541
1542         sdhci_init(host);
1543
1544 #ifdef CONFIG_MMC_DEBUG
1545         sdhci_dumpregs(host);
1546 #endif
1547
1548 #ifdef CONFIG_LEDS_CLASS
1549         host->led.name = mmc_hostname(mmc);
1550         host->led.brightness = LED_OFF;
1551         host->led.default_trigger = mmc_hostname(mmc);
1552         host->led.brightness_set = sdhci_led_control;
1553
1554         ret = led_classdev_register(&pdev->dev, &host->led);
1555         if (ret)
1556                 goto reset;
1557 #endif
1558
1559         mmiowb();
1560
1561         mmc_add_host(mmc);
1562
1563         printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n",
1564                 mmc_hostname(mmc), host->addr, host->irq,
1565                 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1566
1567         return 0;
1568
1569 #ifdef CONFIG_LEDS_CLASS
1570 reset:
1571         sdhci_reset(host, SDHCI_RESET_ALL);
1572         free_irq(host->irq, host);
1573 #endif
1574 untasklet:
1575         tasklet_kill(&host->card_tasklet);
1576         tasklet_kill(&host->finish_tasklet);
1577 unmap:
1578         iounmap(host->ioaddr);
1579 release:
1580         pci_release_region(pdev, host->bar);
1581 free:
1582         mmc_free_host(mmc);
1583
1584         return ret;
1585 }
1586
1587 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1588 {
1589         struct sdhci_chip *chip;
1590         struct mmc_host *mmc;
1591         struct sdhci_host *host;
1592
1593         chip = pci_get_drvdata(pdev);
1594         host = chip->hosts[slot];
1595         mmc = host->mmc;
1596
1597         chip->hosts[slot] = NULL;
1598
1599         mmc_remove_host(mmc);
1600
1601 #ifdef CONFIG_LEDS_CLASS
1602         led_classdev_unregister(&host->led);
1603 #endif
1604
1605         sdhci_reset(host, SDHCI_RESET_ALL);
1606
1607         free_irq(host->irq, host);
1608
1609         del_timer_sync(&host->timer);
1610
1611         tasklet_kill(&host->card_tasklet);
1612         tasklet_kill(&host->finish_tasklet);
1613
1614         iounmap(host->ioaddr);
1615
1616         pci_release_region(pdev, host->bar);
1617
1618         mmc_free_host(mmc);
1619 }
1620
1621 static int __devinit sdhci_probe(struct pci_dev *pdev,
1622         const struct pci_device_id *ent)
1623 {
1624         int ret, i;
1625         u8 slots, rev;
1626         struct sdhci_chip *chip;
1627
1628         BUG_ON(pdev == NULL);
1629         BUG_ON(ent == NULL);
1630
1631         pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1632
1633         printk(KERN_INFO DRIVER_NAME
1634                 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1635                 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1636                 (int)rev);
1637
1638         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1639         if (ret)
1640                 return ret;
1641
1642         slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1643         DBG("found %d slot(s)\n", slots);
1644         if (slots == 0)
1645                 return -ENODEV;
1646
1647         ret = pci_enable_device(pdev);
1648         if (ret)
1649                 return ret;
1650
1651         chip = kzalloc(sizeof(struct sdhci_chip) +
1652                 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1653         if (!chip) {
1654                 ret = -ENOMEM;
1655                 goto err;
1656         }
1657
1658         chip->pdev = pdev;
1659         chip->quirks = ent->driver_data;
1660
1661         if (debug_quirks)
1662                 chip->quirks = debug_quirks;
1663
1664         chip->num_slots = slots;
1665         pci_set_drvdata(pdev, chip);
1666
1667         for (i = 0;i < slots;i++) {
1668                 ret = sdhci_probe_slot(pdev, i);
1669                 if (ret) {
1670                         for (i--;i >= 0;i--)
1671                                 sdhci_remove_slot(pdev, i);
1672                         goto free;
1673                 }
1674         }
1675
1676         return 0;
1677
1678 free:
1679         pci_set_drvdata(pdev, NULL);
1680         kfree(chip);
1681
1682 err:
1683         pci_disable_device(pdev);
1684         return ret;
1685 }
1686
1687 static void __devexit sdhci_remove(struct pci_dev *pdev)
1688 {
1689         int i;
1690         struct sdhci_chip *chip;
1691
1692         chip = pci_get_drvdata(pdev);
1693
1694         if (chip) {
1695                 for (i = 0;i < chip->num_slots;i++)
1696                         sdhci_remove_slot(pdev, i);
1697
1698                 pci_set_drvdata(pdev, NULL);
1699
1700                 kfree(chip);
1701         }
1702
1703         pci_disable_device(pdev);
1704 }
1705
1706 static struct pci_driver sdhci_driver = {
1707         .name =         DRIVER_NAME,
1708         .id_table =     pci_ids,
1709         .probe =        sdhci_probe,
1710         .remove =       __devexit_p(sdhci_remove),
1711         .suspend =      sdhci_suspend,
1712         .resume =       sdhci_resume,
1713 };
1714
1715 /*****************************************************************************\
1716  *                                                                           *
1717  * Driver init/exit                                                          *
1718  *                                                                           *
1719 \*****************************************************************************/
1720
1721 static int __init sdhci_drv_init(void)
1722 {
1723         printk(KERN_INFO DRIVER_NAME
1724                 ": Secure Digital Host Controller Interface driver\n");
1725         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1726
1727         return pci_register_driver(&sdhci_driver);
1728 }
1729
1730 static void __exit sdhci_drv_exit(void)
1731 {
1732         DBG("Exiting\n");
1733
1734         pci_unregister_driver(&sdhci_driver);
1735 }
1736
1737 module_init(sdhci_drv_init);
1738 module_exit(sdhci_drv_exit);
1739
1740 module_param(debug_quirks, uint, 0444);
1741
1742 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1743 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1744 MODULE_LICENSE("GPL");
1745
1746 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");