2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_device.h>
24 #include <linux/workqueue.h>
25 #include <linux/timer.h>
26 #include <linux/clk.h>
27 #include <linux/mmc/host.h>
29 #include <linux/semaphore.h>
31 #include <mach/hardware.h>
32 #include <mach/board.h>
36 /* OMAP HSMMC Host Controller Registers */
37 #define OMAP_HSMMC_SYSCONFIG 0x0010
38 #define OMAP_HSMMC_CON 0x002C
39 #define OMAP_HSMMC_BLK 0x0104
40 #define OMAP_HSMMC_ARG 0x0108
41 #define OMAP_HSMMC_CMD 0x010C
42 #define OMAP_HSMMC_RSP10 0x0110
43 #define OMAP_HSMMC_RSP32 0x0114
44 #define OMAP_HSMMC_RSP54 0x0118
45 #define OMAP_HSMMC_RSP76 0x011C
46 #define OMAP_HSMMC_DATA 0x0120
47 #define OMAP_HSMMC_HCTL 0x0128
48 #define OMAP_HSMMC_SYSCTL 0x012C
49 #define OMAP_HSMMC_STAT 0x0130
50 #define OMAP_HSMMC_IE 0x0134
51 #define OMAP_HSMMC_ISE 0x0138
52 #define OMAP_HSMMC_CAPA 0x0140
54 #define VS18 (1 << 26)
55 #define VS30 (1 << 25)
56 #define SDVS18 (0x5 << 9)
57 #define SDVS30 (0x6 << 9)
58 #define SDVSCLR 0xFFFFF1FF
59 #define SDVSDET 0x00000400
66 #define CLKD_MASK 0x0000FFC0
68 #define DTO_MASK 0x000F0000
70 #define INT_EN_MASK 0x307F0033
71 #define INIT_STREAM (1 << 1)
72 #define DP_SELECT (1 << 21)
77 #define FOUR_BIT (1 << 1)
82 #define CMD_TIMEOUT (1 << 16)
83 #define DATA_TIMEOUT (1 << 20)
84 #define CMD_CRC (1 << 17)
85 #define DATA_CRC (1 << 21)
86 #define CARD_ERR (1 << 28)
87 #define STAT_CLEAR 0xFFFFFFFF
88 #define INIT_STREAM_CMD 0x00000000
89 #define DUAL_VOLT_OCR_BIT 7
94 * FIXME: Most likely all the data using these _DEVID defines should come
95 * from the platform_data, or implemented in controller and slot specific
98 #define OMAP_MMC1_DEVID 0
99 #define OMAP_MMC2_DEVID 1
101 #define OMAP_MMC_DATADIR_NONE 0
102 #define OMAP_MMC_DATADIR_READ 1
103 #define OMAP_MMC_DATADIR_WRITE 2
104 #define MMC_TIMEOUT_MS 20
105 #define OMAP_MMC_MASTER_CLOCK 96000000
106 #define DRIVER_NAME "mmci-omap-hs"
109 * One controller can have multiple slots, like on some omap boards using
110 * omap.c controller driver. Luckily this is not currently done on any known
111 * omap_hsmmc.c device.
113 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
116 * MMC Host controller read/write API's
118 #define OMAP_HSMMC_READ(base, reg) \
119 __raw_readl((base) + OMAP_HSMMC_##reg)
121 #define OMAP_HSMMC_WRITE(base, reg, val) \
122 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
125 #define IDLE_TIMEOUT (jiffies_to_msecs(10))
127 struct mmc_omap_host {
129 struct mmc_host *mmc;
130 struct mmc_request *mrq;
131 struct mmc_command *cmd;
132 struct mmc_data *data;
136 struct semaphore sem;
137 struct work_struct mmc_carddetect_work;
139 resource_size_t mapbase;
141 unsigned int dma_len;
142 unsigned int dma_dir;
143 unsigned char bus_mode;
144 unsigned char datadir;
155 struct timer_list idle_timer;
156 spinlock_t clk_lock; /* for changing enabled state */
157 unsigned int fclk_enabled:1;
159 struct omap_mmc_platform_data *pdata;
162 static int mmc_omap_fclk_state(struct mmc_omap_host *host, unsigned int state)
167 spin_lock_irqsave(&host->clk_lock, flags);
168 del_timer(&host->idle_timer);
169 if (host->fclk_enabled != state) {
171 ret = clk_enable(host->fclk);
175 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
177 clk_disable(host->fclk);
178 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
180 host->fclk_enabled = state;
184 spin_unlock_irqrestore(&host->clk_lock, flags);
188 static void mmc_omap_idle_timer(unsigned long data)
190 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
192 mmc_omap_fclk_state(host, OFF);
195 static void mmc_omap_fclk_lazy_disable(struct mmc_omap_host *host)
197 mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
201 * Stop clock to the card
203 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
205 OMAP_HSMMC_WRITE(host->base, SYSCTL,
206 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
207 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
208 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
212 * Send init stream sequence to card
213 * before sending IDLE command
215 static void send_init_stream(struct mmc_omap_host *host)
218 unsigned long timeout;
220 disable_irq(host->irq);
221 OMAP_HSMMC_WRITE(host->base, CON,
222 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
223 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
225 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
226 while ((reg != CC) && time_before(jiffies, timeout))
227 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
229 OMAP_HSMMC_WRITE(host->base, CON,
230 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
231 enable_irq(host->irq);
235 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
239 if (host->pdata->slots[host->slot_id].get_cover_state)
240 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
246 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
249 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
250 struct mmc_omap_host *host = mmc_priv(mmc);
252 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
256 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
259 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
262 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
263 struct mmc_omap_host *host = mmc_priv(mmc);
264 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
266 return sprintf(buf, "slot:%s\n", slot.name);
269 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
272 * Configure the response type and send the cmd.
275 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
276 struct mmc_data *data)
278 int cmdreg = 0, resptype = 0, cmdtype = 0;
280 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
281 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
285 * Clear status bits and enable interrupts
287 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
288 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
289 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
291 if (cmd->flags & MMC_RSP_PRESENT) {
292 if (cmd->flags & MMC_RSP_136)
299 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
300 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
301 * a val of 0x3, rest 0x0.
303 if (cmd == host->mrq->stop)
306 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
309 cmdreg |= DP_SELECT | MSBS | BCE;
310 if (data->flags & MMC_DATA_READ)
319 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
320 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
324 * Notify the transfer complete to MMC core
327 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
331 if (host->use_dma && host->dma_ch != -1)
332 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
335 host->datadir = OMAP_MMC_DATADIR_NONE;
338 data->bytes_xfered += data->blocks * (data->blksz);
340 data->bytes_xfered = 0;
344 mmc_omap_fclk_lazy_disable(host);
345 mmc_request_done(host->mmc, data->mrq);
348 mmc_omap_start_command(host, data->stop, NULL);
352 * Notify the core about command completion
355 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
359 if (cmd->flags & MMC_RSP_PRESENT) {
360 if (cmd->flags & MMC_RSP_136) {
361 /* response type 2 */
362 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
363 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
364 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
365 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
367 /* response types 1, 1b, 3, 4, 5, 6 */
368 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
371 if (host->data == NULL || cmd->error) {
373 mmc_omap_fclk_lazy_disable(host);
374 mmc_request_done(host->mmc, cmd->mrq);
379 * DMA clean up for command errors
381 static void mmc_dma_cleanup(struct mmc_omap_host *host)
383 host->data->error = -ETIMEDOUT;
385 if (host->use_dma && host->dma_ch != -1) {
386 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
388 omap_free_dma(host->dma_ch);
393 host->datadir = OMAP_MMC_DATADIR_NONE;
397 * Readable error output
399 #ifdef CONFIG_MMC_DEBUG
400 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
402 /* --- means reserved bit without definition at documentation */
403 static const char *mmc_omap_status_bits[] = {
404 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
405 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
406 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
407 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
413 len = sprintf(buf, "MMC IRQ 0x%x :", status);
416 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
417 if (status & (1 << i)) {
418 len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
422 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
424 #endif /* CONFIG_MMC_DEBUG */
428 * MMC controller IRQ handler
430 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
432 struct mmc_omap_host *host = dev_id;
433 struct mmc_data *data;
434 int end_cmd = 0, end_trans = 0, status;
436 if (host->cmd == NULL && host->data == NULL) {
437 OMAP_HSMMC_WRITE(host->base, STAT,
438 OMAP_HSMMC_READ(host->base, STAT));
443 status = OMAP_HSMMC_READ(host->base, STAT);
444 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
447 #ifdef CONFIG_MMC_DEBUG
448 mmc_omap_report_irq(host, status);
450 if ((status & CMD_TIMEOUT) ||
451 (status & CMD_CRC)) {
453 if (status & CMD_TIMEOUT) {
454 OMAP_HSMMC_WRITE(host->base, SYSCTL,
455 OMAP_HSMMC_READ(host->base,
457 while (OMAP_HSMMC_READ(host->base,
461 host->cmd->error = -ETIMEDOUT;
463 host->cmd->error = -EILSEQ;
468 mmc_dma_cleanup(host);
470 if ((status & DATA_TIMEOUT) ||
471 (status & DATA_CRC)) {
473 if (status & DATA_TIMEOUT)
474 mmc_dma_cleanup(host);
476 host->data->error = -EILSEQ;
477 OMAP_HSMMC_WRITE(host->base, SYSCTL,
478 OMAP_HSMMC_READ(host->base,
480 while (OMAP_HSMMC_READ(host->base,
486 if (status & CARD_ERR) {
487 dev_dbg(mmc_dev(host->mmc),
488 "Ignoring card err CMD%d\n", host->cmd->opcode);
496 OMAP_HSMMC_WRITE(host->base, STAT, status);
498 if (end_cmd || (status & CC))
499 mmc_omap_cmd_done(host, host->cmd);
500 if (end_trans || (status & TC))
501 mmc_omap_xfer_done(host, data);
507 * Switch MMC operating voltage
509 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
514 /* Disable the clocks */
515 mmc_omap_fclk_state(host, OFF);
516 clk_disable(host->iclk);
517 clk_disable(host->dbclk);
519 /* Turn the power off */
520 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
524 /* Turn the power ON with given VDD 1.8 or 3.0v */
525 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
529 mmc_omap_fclk_state(host, ON);
530 clk_enable(host->iclk);
531 clk_enable(host->dbclk);
533 OMAP_HSMMC_WRITE(host->base, HCTL,
534 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
535 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
537 * If a MMC dual voltage card is detected, the set_ios fn calls
538 * this fn with VDD bit set for 1.8V. Upon card removal from the
539 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
541 * Only MMC1 supports 3.0V. MMC2 will not function if SDVS30 is
544 if (host->id == OMAP_MMC1_DEVID) {
545 if (((1 << vdd) == MMC_VDD_32_33) ||
546 ((1 << vdd) == MMC_VDD_33_34))
548 else if ((1 << vdd) == MMC_VDD_165_195)
553 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
555 OMAP_HSMMC_WRITE(host->base, HCTL,
556 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
560 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
565 * Work Item to notify the core about card insertion/removal
567 static void mmc_omap_detect(struct work_struct *work)
569 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
570 mmc_carddetect_work);
572 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
573 mmc_omap_fclk_state(host, ON);
574 if (host->carddetect) {
575 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
577 OMAP_HSMMC_WRITE(host->base, SYSCTL,
578 OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
579 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD)
582 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
584 mmc_omap_fclk_lazy_disable(host);
588 * ISR for handling card insertion and removal
590 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
592 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
594 host->carddetect = mmc_slot(host).card_detect(irq);
595 schedule_work(&host->mmc_carddetect_work);
601 * DMA call back function
603 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
605 struct mmc_omap_host *host = data;
607 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
608 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
610 if (host->dma_ch < 0)
613 omap_free_dma(host->dma_ch);
616 * DMA Callback: run in interrupt context.
617 * mutex_unlock will through a kernel warning if used.
623 * Configure dma src and destination parameters
625 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
626 struct mmc_data *data)
629 omap_set_dma_dest_params(host->dma_ch, 0,
630 OMAP_DMA_AMODE_CONSTANT,
631 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
632 omap_set_dma_src_params(host->dma_ch, 0,
633 OMAP_DMA_AMODE_POST_INC,
634 sg_dma_address(&data->sg[0]), 0, 0);
636 omap_set_dma_src_params(host->dma_ch, 0,
637 OMAP_DMA_AMODE_CONSTANT,
638 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
639 omap_set_dma_dest_params(host->dma_ch, 0,
640 OMAP_DMA_AMODE_POST_INC,
641 sg_dma_address(&data->sg[0]), 0, 0);
646 * Routine to configure and start DMA for the MMC card
649 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
651 int sync_dev, sync_dir = 0;
652 int dma_ch = 0, ret = 0, err = 1;
653 struct mmc_data *data = req->data;
656 * If for some reason the DMA transfer is still active,
657 * we wait for timeout period and free the dma
659 if (host->dma_ch != -1) {
660 set_current_state(TASK_UNINTERRUPTIBLE);
661 schedule_timeout(100);
662 if (down_trylock(&host->sem)) {
663 omap_free_dma(host->dma_ch);
669 if (down_trylock(&host->sem))
673 if (!(data->flags & MMC_DATA_WRITE)) {
674 host->dma_dir = DMA_FROM_DEVICE;
675 if (host->id == OMAP_MMC1_DEVID)
676 sync_dev = OMAP24XX_DMA_MMC1_RX;
678 sync_dev = OMAP24XX_DMA_MMC2_RX;
680 host->dma_dir = DMA_TO_DEVICE;
681 if (host->id == OMAP_MMC1_DEVID)
682 sync_dev = OMAP24XX_DMA_MMC1_TX;
684 sync_dev = OMAP24XX_DMA_MMC2_TX;
687 ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
690 dev_dbg(mmc_dev(host->mmc),
691 "%s: omap_request_dma() failed with %d\n",
692 mmc_hostname(host->mmc), ret);
696 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
697 data->sg_len, host->dma_dir);
698 host->dma_ch = dma_ch;
700 if (!(data->flags & MMC_DATA_WRITE))
701 mmc_omap_config_dma_param(1, host, data);
703 mmc_omap_config_dma_param(0, host, data);
705 if ((data->blksz % 4) == 0)
706 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
707 (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
710 /* REVISIT: The MMC buffer increments only when MSB is written.
711 * Return error for blksz which is non multiple of four.
715 omap_start_dma(dma_ch);
719 static void set_data_timeout(struct mmc_omap_host *host,
720 struct mmc_request *req)
722 unsigned int timeout, cycle_ns;
723 uint32_t reg, clkd, dto = 0;
725 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
726 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
730 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
731 timeout = req->data->timeout_ns / cycle_ns;
732 timeout += req->data->timeout_clks;
734 while ((timeout & 0x80000000) == 0) {
751 reg |= dto << DTO_SHIFT;
752 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
756 * Configure block length for MMC/SD cards and initiate the transfer.
759 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
762 host->data = req->data;
764 if (req->data == NULL) {
765 host->datadir = OMAP_MMC_DATADIR_NONE;
766 OMAP_HSMMC_WRITE(host->base, BLK, 0);
770 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
771 | (req->data->blocks << 16));
772 set_data_timeout(host, req);
774 host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
775 OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
778 ret = mmc_omap_start_dma_transfer(host, req);
780 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
788 * Request function. for read/write operation
790 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
792 struct mmc_omap_host *host = mmc_priv(mmc);
794 WARN_ON(host->mrq != NULL);
796 mmc_omap_fclk_state(host, ON);
797 mmc_omap_prepare_data(host, req);
798 mmc_omap_start_command(host, req->cmd, req->data);
801 /* Routine to configure clock values. Exposed API to core */
802 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
804 struct mmc_omap_host *host = mmc_priv(mmc);
806 unsigned long regval;
807 unsigned long timeout;
809 mmc_omap_fclk_state(host, ON);
811 switch (ios->power_mode) {
813 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
815 * Reset bus voltage to 3V if it got set to 1.8V earlier.
816 * REVISIT: If we are able to detect cards after unplugging
817 * a 1.8V card, this code should not be needed.
819 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
820 int vdd = fls(host->mmc->ocr_avail) - 1;
821 if (omap_mmc_switch_opcond(host, vdd) != 0)
822 host->mmc->ios.vdd = vdd;
826 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
830 switch (mmc->ios.bus_width) {
831 case MMC_BUS_WIDTH_4:
832 OMAP_HSMMC_WRITE(host->base, HCTL,
833 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
835 case MMC_BUS_WIDTH_1:
836 OMAP_HSMMC_WRITE(host->base, HCTL,
837 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
841 if (host->id == OMAP_MMC1_DEVID) {
842 /* Only MMC1 can operate at 3V/1.8V */
843 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
844 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
846 * The mmc_select_voltage fn of the core does
847 * not seem to set the power_mode to
848 * MMC_POWER_UP upon recalculating the voltage.
851 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
852 dev_dbg(mmc_dev(host->mmc),
853 "Switch operation failed\n");
858 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
862 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
868 omap_mmc_stop_clock(host);
869 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
870 regval = regval & ~(CLKD_MASK);
871 regval = regval | (dsor << 6) | (DTO << 16);
872 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
873 OMAP_HSMMC_WRITE(host->base, SYSCTL,
874 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
876 /* Wait till the ICS bit is set */
877 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
878 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
879 && time_before(jiffies, timeout))
882 OMAP_HSMMC_WRITE(host->base, SYSCTL,
883 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
885 if (ios->power_mode == MMC_POWER_ON)
886 send_init_stream(host);
888 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
889 OMAP_HSMMC_WRITE(host->base, CON,
890 OMAP_HSMMC_READ(host->base, CON) | OD);
892 mmc_omap_fclk_lazy_disable(host);
895 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
897 struct mmc_omap_host *host = mmc_priv(mmc);
898 struct omap_mmc_platform_data *pdata = host->pdata;
900 if (!pdata->slots[0].card_detect)
902 return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
905 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
907 struct mmc_omap_host *host = mmc_priv(mmc);
908 struct omap_mmc_platform_data *pdata = host->pdata;
910 if (!pdata->slots[0].get_ro)
912 return pdata->slots[0].get_ro(host->dev, 0);
915 static struct mmc_host_ops mmc_omap_ops = {
916 .request = omap_mmc_request,
917 .set_ios = omap_mmc_set_ios,
918 .get_cd = omap_hsmmc_get_cd,
919 .get_ro = omap_hsmmc_get_ro,
920 /* NYET -- enable_sdio_irq */
923 static int __init omap_mmc_probe(struct platform_device *pdev)
925 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
926 struct mmc_host *mmc;
927 struct mmc_omap_host *host = NULL;
928 struct resource *res;
933 dev_err(&pdev->dev, "Platform Data is missing\n");
937 if (pdata->nr_slots == 0) {
938 dev_err(&pdev->dev, "No Slots\n");
942 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
943 irq = platform_get_irq(pdev, 0);
944 if (res == NULL || irq < 0)
947 res = request_mem_region(res->start, res->end - res->start + 1,
952 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
958 host = mmc_priv(mmc);
961 host->dev = &pdev->dev;
963 host->dev->dma_mask = &pdata->dma_mask;
968 host->mapbase = res->start;
969 host->base = ioremap(host->mapbase, SZ_4K);
971 platform_set_drvdata(pdev, host);
972 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
974 mmc->ops = &mmc_omap_ops;
976 mmc->f_max = 52000000;
978 sema_init(&host->sem, 1);
980 host->iclk = clk_get(&pdev->dev, "mmchs_ick");
981 if (IS_ERR(host->iclk)) {
982 ret = PTR_ERR(host->iclk);
986 host->fclk = clk_get(&pdev->dev, "mmchs_fck");
987 if (IS_ERR(host->fclk)) {
988 ret = PTR_ERR(host->fclk);
994 spin_lock_init(&host->clk_lock);
995 setup_timer(&host->idle_timer, mmc_omap_idle_timer,
996 (unsigned long) host);
998 if (mmc_omap_fclk_state(host, ON) != 0) {
1000 clk_put(host->fclk);
1003 if (clk_enable(host->iclk) != 0) {
1004 mmc_omap_fclk_state(host, OFF);
1005 clk_put(host->iclk);
1006 clk_put(host->fclk);
1010 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1012 * MMC can still work without debounce clock.
1014 if (IS_ERR(host->dbclk))
1015 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1017 if (clk_enable(host->dbclk) != 0)
1018 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1021 host->dbclk_enabled = 1;
1023 #ifdef CONFIG_MMC_BLOCK_BOUNCE
1024 mmc->max_phys_segs = 1;
1025 mmc->max_hw_segs = 1;
1027 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1028 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1029 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1030 mmc->max_seg_size = mmc->max_req_size;
1032 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1033 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1035 if (pdata->slots[host->slot_id].wires >= 4)
1036 mmc->caps |= MMC_CAP_4_BIT_DATA;
1038 /* Only MMC1 supports 3.0V */
1039 if (host->id == OMAP_MMC1_DEVID) {
1047 OMAP_HSMMC_WRITE(host->base, HCTL,
1048 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
1050 OMAP_HSMMC_WRITE(host->base, CAPA,
1051 OMAP_HSMMC_READ(host->base, CAPA) | capa);
1053 /* Set the controller to AUTO IDLE mode */
1054 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
1055 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
1057 /* Set SD bus power bit */
1058 OMAP_HSMMC_WRITE(host->base, HCTL,
1059 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1061 /* Request IRQ for MMC operations */
1062 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1063 mmc_hostname(mmc), host);
1065 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1069 if (pdata->init != NULL) {
1070 if (pdata->init(&pdev->dev) != 0) {
1071 dev_dbg(mmc_dev(host->mmc),
1072 "Unable to configure MMC IRQs\n");
1073 goto err_irq_cd_init;
1077 /* Request IRQ for card detect */
1078 if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1079 ret = request_irq(mmc_slot(host).card_detect_irq,
1080 omap_mmc_cd_handler,
1081 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1083 mmc_hostname(mmc), host);
1085 dev_dbg(mmc_dev(host->mmc),
1086 "Unable to grab MMC CD IRQ\n");
1091 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1092 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1096 if (host->pdata->slots[host->slot_id].name != NULL) {
1097 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1101 if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1102 host->pdata->slots[host->slot_id].get_cover_state) {
1103 ret = device_create_file(&mmc->class_dev,
1104 &dev_attr_cover_switch);
1106 goto err_cover_switch;
1108 mmc_omap_fclk_lazy_disable(host);
1113 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1115 mmc_remove_host(mmc);
1117 free_irq(mmc_slot(host).card_detect_irq, host);
1119 free_irq(host->irq, host);
1121 mmc_omap_fclk_state(host, OFF);
1122 clk_disable(host->iclk);
1123 clk_put(host->fclk);
1124 clk_put(host->iclk);
1125 if (host->dbclk_enabled) {
1126 clk_disable(host->dbclk);
1127 clk_put(host->dbclk);
1131 iounmap(host->base);
1133 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1134 release_mem_region(res->start, res->end - res->start + 1);
1140 static int omap_mmc_remove(struct platform_device *pdev)
1142 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1143 struct resource *res;
1146 mmc_remove_host(host->mmc);
1147 if (host->pdata->cleanup)
1148 host->pdata->cleanup(&pdev->dev);
1149 free_irq(host->irq, host);
1150 if (mmc_slot(host).card_detect_irq)
1151 free_irq(mmc_slot(host).card_detect_irq, host);
1152 flush_scheduled_work();
1154 mmc_omap_fclk_state(host, OFF);
1155 clk_disable(host->iclk);
1156 clk_put(host->fclk);
1157 clk_put(host->iclk);
1158 if (host->dbclk_enabled) {
1159 clk_disable(host->dbclk);
1160 clk_put(host->dbclk);
1163 mmc_free_host(host->mmc);
1164 iounmap(host->base);
1167 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1169 release_mem_region(res->start, res->end - res->start + 1);
1170 platform_set_drvdata(pdev, NULL);
1176 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1179 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1181 if (host && host->suspended)
1185 ret = mmc_suspend_host(host->mmc, state);
1187 host->suspended = 1;
1189 mmc_omap_fclk_state(host, ON);
1190 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1191 OMAP_HSMMC_WRITE(host->base, IE, 0);
1193 if (host->pdata->suspend) {
1194 ret = host->pdata->suspend(&pdev->dev,
1197 dev_dbg(mmc_dev(host->mmc),
1198 "Unable to handle MMC board"
1199 " level suspend\n");
1202 OMAP_HSMMC_WRITE(host->base, HCTL,
1203 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1204 mmc_omap_fclk_state(host, OFF);
1205 clk_disable(host->iclk);
1206 clk_disable(host->dbclk);
1213 /* Routine to resume the MMC device */
1214 static int omap_mmc_resume(struct platform_device *pdev)
1217 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1219 if (host && !host->suspended)
1224 if (mmc_omap_fclk_state(host, ON) != 0)
1227 ret = clk_enable(host->iclk);
1229 mmc_omap_fclk_state(host, OFF);
1230 clk_put(host->fclk);
1234 if (clk_enable(host->dbclk) != 0)
1235 dev_dbg(mmc_dev(host->mmc),
1236 "Enabling debounce clk failed\n");
1238 OMAP_HSMMC_WRITE(host->base, HCTL,
1239 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1241 for (i = 0; i < 100; i++)
1242 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1245 if (host->pdata->resume) {
1246 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1248 dev_dbg(mmc_dev(host->mmc),
1249 "Unmask interrupt failed\n");
1252 /* Notify the core to resume the host */
1253 ret = mmc_resume_host(host->mmc);
1255 host->suspended = 0;
1257 mmc_omap_fclk_lazy_disable(host);
1263 dev_dbg(mmc_dev(host->mmc),
1264 "Failed to enable MMC clocks during resume\n");
1269 #define omap_mmc_suspend NULL
1270 #define omap_mmc_resume NULL
1273 static struct platform_driver omap_mmc_driver = {
1274 .probe = omap_mmc_probe,
1275 .remove = omap_mmc_remove,
1276 .suspend = omap_mmc_suspend,
1277 .resume = omap_mmc_resume,
1279 .name = DRIVER_NAME,
1280 .owner = THIS_MODULE,
1284 static int __init omap_mmc_init(void)
1286 /* Register the MMC driver */
1287 return platform_driver_register(&omap_mmc_driver);
1290 static void __exit omap_mmc_cleanup(void)
1292 /* Unregister MMC driver */
1293 platform_driver_unregister(&omap_mmc_driver);
1296 module_init(omap_mmc_init);
1297 module_exit(omap_mmc_cleanup);
1299 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1300 MODULE_LICENSE("GPL");
1301 MODULE_ALIAS("platform:" DRIVER_NAME);
1302 MODULE_AUTHOR("Texas Instruments Inc");