drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <asm/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1 << 8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1 << 2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define CLKD_SHIFT              6
  68 #define DTO_MASK                0x000F0000
  69 #define DTO_SHIFT               16
  70 #define INT_EN_MASK             0x307F0033
  71 #define INIT_STREAM             (1 << 1)
  72 #define DP_SELECT               (1 << 21)
  73 #define DDIR                    (1 << 4)
  74 #define DMA_EN                  0x1
  75 #define MSBS                    (1 << 5)
  76 #define BCE                     (1 << 1)
  77 #define FOUR_BIT                (1 << 1)
  78 #define CC                      0x1
  79 #define TC                      0x02
  80 #define OD                      0x1
  81 #define ERR                     (1 << 15)
  82 #define CMD_TIMEOUT             (1 << 16)
  83 #define DATA_TIMEOUT            (1 << 20)
  84 #define CMD_CRC                 (1 << 17)
  85 #define DATA_CRC                (1 << 21)
  86 #define CARD_ERR                (1 << 28)
  87 #define STAT_CLEAR              0xFFFFFFFF
  88 #define INIT_STREAM_CMD         0x00000000
  89 #define DUAL_VOLT_OCR_BIT       7
  90 #define SRC                     (1 << 25)
  91 #define SRD                     (1 << 26)
  92
  93 /*
  94  * FIXME: Most likely all the data using these _DEVID defines should come
  95  * from the platform_data, or implemented in controller and slot specific
  96  * functions.
  97  */
  98 #define OMAP_MMC1_DEVID         0
  99 #define OMAP_MMC2_DEVID         1
 100
 101 #define OMAP_MMC_DATADIR_NONE   0
 102 #define OMAP_MMC_DATADIR_READ   1
 103 #define OMAP_MMC_DATADIR_WRITE  2
 104 #define MMC_TIMEOUT_MS          20
 105 #define OMAP_MMC_MASTER_CLOCK   96000000
 106 #define DRIVER_NAME             "mmci-omap-hs"
 107
 108 /*
 109  * One controller can have multiple slots, like on some omap boards using
 110  * omap.c controller driver. Luckily this is not currently done on any known
 111  * omap_hsmmc.c device.
 112  */
 113 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 114
 115 /*
 116  * MMC Host controller read/write API's
 117  */
 118 #define OMAP_HSMMC_READ(base, reg)      \
 119         __raw_readl((base) + OMAP_HSMMC_##reg)
 120
 121 #define OMAP_HSMMC_WRITE(base, reg, val) \
 122         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 123
 124 enum {OFF = 0, ON};
 125 #define IDLE_TIMEOUT (jiffies_to_msecs(10))
 126
 127 struct mmc_omap_host {
 128         struct  device          *dev;
 129         struct  mmc_host        *mmc;
 130         struct  mmc_request     *mrq;
 131         struct  mmc_command     *cmd;
 132         struct  mmc_data        *data;
 133         struct  clk             *fclk;
 134         struct  clk             *iclk;
 135         struct  clk             *dbclk;
 136         struct  semaphore       sem;
 137         struct  work_struct     mmc_carddetect_work;
 138         void    __iomem         *base;
 139         resource_size_t         mapbase;
 140         unsigned int            id;
 141         unsigned int            dma_len;
 142         unsigned int            dma_dir;
 143         unsigned char           bus_mode;
 144         unsigned char           datadir;
 145         u32                     *buffer;
 146         u32                     bytesleft;
 147         int                     suspended;
 148         int                     irq;
 149         int                     carddetect;
 150         int                     use_dma, dma_ch;
 151         int                     initstr;
 152         int                     slot_id;
 153         int                     dbclk_enabled;
 154
 155         struct timer_list       idle_timer;
 156         spinlock_t              clk_lock;     /* for changing enabled state */
 157         unsigned int            fclk_enabled:1;
 158
 159         struct  omap_mmc_platform_data  *pdata;
 160 };
 161
 162 static int mmc_omap_fclk_state(struct mmc_omap_host *host, unsigned int state)
 163 {
 164         unsigned long flags;
 165         int ret = 0;
 166
 167         spin_lock_irqsave(&host->clk_lock, flags);
 168         del_timer(&host->idle_timer);
 169         if (host->fclk_enabled != state) {
 170                 if (state == ON) {
 171                         ret = clk_enable(host->fclk);
 172                         if (ret != 0)
 173                                 goto err_out;
 174
 175                         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
 176                 } else {
 177                         clk_disable(host->fclk);
 178                         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
 179                 }
 180                 host->fclk_enabled = state;
 181         }
 182
 183 err_out:
 184         spin_unlock_irqrestore(&host->clk_lock, flags);
 185         return ret;
 186 }
 187
 188 static void mmc_omap_idle_timer(unsigned long data)
 189 {
 190         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 191
 192         mmc_omap_fclk_state(host, OFF);
 193 }
 194
 195 static void mmc_omap_fclk_lazy_disable(struct mmc_omap_host *host)
 196 {
 197         mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
 198 }
 199
 200 /*
 201  * Stop clock to the card
 202  */
 203 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 204 {
 205         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 206                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 207         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 208                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 209 }
 210
 211 /*
 212  * Send init stream sequence to card
 213  * before sending IDLE command
 214  */
 215 static void send_init_stream(struct mmc_omap_host *host)
 216 {
 217         int reg = 0;
 218         unsigned long timeout;
 219
 220         disable_irq(host->irq);
 221         OMAP_HSMMC_WRITE(host->base, CON,
 222                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 223         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 224
 225         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 226         while ((reg != CC) && time_before(jiffies, timeout))
 227                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 228
 229         OMAP_HSMMC_WRITE(host->base, CON,
 230                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 231         enable_irq(host->irq);
 232 }
 233
 234 static inline
 235 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 236 {
 237         if (host->pdata->slots[host->slot_id].get_cover_state)
 238                 return host->pdata->slots[host->slot_id].get_cover_state(host->dev, host->slot_id);
 239         return 1;
 240 }
 241
 242 static ssize_t
 243 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 244                            char *buf)
 245 {
 246         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 247         struct mmc_omap_host *host = mmc_priv(mmc);
 248
 249         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 250                        "open");
 251 }
 252
 253 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 254
 255 static ssize_t
 256 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 257                         char *buf)
 258 {
 259         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 260         struct mmc_omap_host *host = mmc_priv(mmc);
 261         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 262
 263         return sprintf(buf, "slot:%s\n", slot.name);
 264 }
 265
 266 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 267
 268 /*
 269  * Configure the response type and send the cmd.
 270  */
 271 static void
 272 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 273         struct mmc_data *data)
 274 {
 275         int cmdreg = 0, resptype = 0, cmdtype = 0;
 276
 277         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 278                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 279         host->cmd = cmd;
 280
 281         /*
 282          * Clear status bits and enable interrupts
 283          */
 284         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 285         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 286         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 287
 288         if (cmd->flags & MMC_RSP_PRESENT) {
 289                 if (cmd->flags & MMC_RSP_136)
 290                         resptype = 1;
 291                 else
 292                         resptype = 2;
 293         }
 294
 295         /*
 296          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 297          * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
 298          */
 299         if (cmd->opcode == 12)
 300                 cmdtype = 0x3;
 301
 302         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 303
 304         if (data) {
 305                 cmdreg |= DP_SELECT | MSBS | BCE;
 306                 if (data->flags & MMC_DATA_READ)
 307                         cmdreg |= DDIR;
 308                 else
 309                         cmdreg &= ~(DDIR);
 310         }
 311
 312         if (host->use_dma)
 313                 cmdreg |= DMA_EN;
 314
 315         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 316         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 317 }
 318
 319 /*
 320  * Notify the transfer complete to MMC core
 321  */
 322 static void
 323 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 324 {
 325         host->data = NULL;
 326
 327         if (host->use_dma && host->dma_ch != -1)
 328                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 329                         host->dma_dir);
 330
 331         host->datadir = OMAP_MMC_DATADIR_NONE;
 332
 333         if (!data->error)
 334                 data->bytes_xfered += data->blocks * (data->blksz);
 335         else
 336                 data->bytes_xfered = 0;
 337
 338         if (!data->stop) {
 339                 host->mrq = NULL;
 340                 mmc_omap_fclk_lazy_disable(host);
 341                 mmc_request_done(host->mmc, data->mrq);
 342                 return;
 343         }
 344         mmc_omap_start_command(host, data->stop, NULL);
 345 }
 346
 347 /*
 348  * Notify the core about command completion
 349  */
 350 static void
 351 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 352 {
 353         host->cmd = NULL;
 354
 355         if (cmd->flags & MMC_RSP_PRESENT) {
 356                 if (cmd->flags & MMC_RSP_136) {
 357                         /* response type 2 */
 358                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 359                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 360                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 361                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 362                 } else {
 363                         /* response types 1, 1b, 3, 4, 5, 6 */
 364                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 365                 }
 366         }
 367         if (host->data == NULL || cmd->error) {
 368                 host->mrq = NULL;
 369                 mmc_omap_fclk_lazy_disable(host);
 370                 mmc_request_done(host->mmc, cmd->mrq);
 371         }
 372 }
 373
 374 /*
 375  * DMA clean up for command errors
 376  */
 377 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 378 {
 379         host->data->error = -ETIMEDOUT;
 380
 381         if (host->use_dma && host->dma_ch != -1) {
 382                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 383                         host->dma_dir);
 384                 omap_free_dma(host->dma_ch);
 385                 host->dma_ch = -1;
 386                 up(&host->sem);
 387         }
 388         host->data = NULL;
 389         host->datadir = OMAP_MMC_DATADIR_NONE;
 390 }
 391
 392 /*
 393  * Readable error output
 394  */
 395 #ifdef CONFIG_MMC_DEBUG
 396 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 397 {
 398         /* --- means reserved bit without definition at documentation */
 399         static const char *mmc_omap_status_bits[] = {
 400                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 401                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 402                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 403                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 404         };
 405         int i;
 406
 407         dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
 408
 409         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 410                 if (status & (1 << i))
 411                         /*
 412                          * KERN_* facility is not used here because this should
 413                          * print a single line.
 414                          */
 415                         printk(" %s", mmc_omap_status_bits[i]);
 416
 417         printk("\n");
 418
 419 }
 420 #endif  /* CONFIG_MMC_DEBUG */
 421
 422
 423 /*
 424  * MMC controller IRQ handler
 425  */
 426 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 427 {
 428         struct mmc_omap_host *host = dev_id;
 429         struct mmc_data *data;
 430         int end_cmd = 0, end_trans = 0, status;
 431
 432         if (host->cmd == NULL && host->data == NULL) {
 433                 OMAP_HSMMC_WRITE(host->base, STAT,
 434                         OMAP_HSMMC_READ(host->base, STAT));
 435                 return IRQ_HANDLED;
 436         }
 437
 438         data = host->data;
 439         status = OMAP_HSMMC_READ(host->base, STAT);
 440         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 441
 442         if (status & ERR) {
 443 #ifdef CONFIG_MMC_DEBUG
 444                 mmc_omap_report_irq(host, status);
 445 #endif
 446                 if ((status & CMD_TIMEOUT) ||
 447                         (status & CMD_CRC)) {
 448                         if (host->cmd) {
 449                                 if (status & CMD_TIMEOUT) {
 450                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 451                                                 OMAP_HSMMC_READ(host->base,
 452                                                                 SYSCTL) | SRC);
 453                                         while (OMAP_HSMMC_READ(host->base,
 454                                                                 SYSCTL) & SRC) ;
 455                                         host->cmd->error = -ETIMEDOUT;
 456                                 } else {
 457                                         host->cmd->error = -EILSEQ;
 458                                 }
 459                                 end_cmd = 1;
 460                         }
 461                         if (host->data)
 462                                 mmc_dma_cleanup(host);
 463                 }
 464                 if ((status & DATA_TIMEOUT) ||
 465                         (status & DATA_CRC)) {
 466                         if (host->data) {
 467                                 if (status & DATA_TIMEOUT)
 468                                         mmc_dma_cleanup(host);
 469                                 else
 470                                         host->data->error = -EILSEQ;
 471                                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 472                                         OMAP_HSMMC_READ(host->base,
 473                                                         SYSCTL) | SRD);
 474                                 while (OMAP_HSMMC_READ(host->base,
 475                                                         SYSCTL) & SRD) ;
 476                                 end_trans = 1;
 477                         }
 478                 }
 479                 if (status & CARD_ERR) {
 480                         dev_dbg(mmc_dev(host->mmc),
 481                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 482                         if (host->cmd)
 483                                 end_cmd = 1;
 484                         if (host->data)
 485                                 end_trans = 1;
 486                 }
 487         }
 488
 489         OMAP_HSMMC_WRITE(host->base, STAT, status);
 490
 491         if (end_cmd || (status & CC))
 492                 mmc_omap_cmd_done(host, host->cmd);
 493         if (end_trans || (status & TC))
 494                 mmc_omap_xfer_done(host, data);
 495
 496         return IRQ_HANDLED;
 497 }
 498
 499 /*
 500  * Switch MMC operating voltage
 501  */
 502 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 503 {
 504         u32 reg_val = 0;
 505         int ret;
 506
 507         /* Disable the clocks */
 508         mmc_omap_fclk_state(host, OFF);
 509         clk_disable(host->iclk);
 510         clk_disable(host->dbclk);
 511
 512         /* Turn the power off */
 513         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 514         if (ret != 0)
 515                 goto err;
 516
 517         /* Turn the power ON with given VDD 1.8 or 3.0v */
 518         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 519         if (ret != 0)
 520                 goto err;
 521
 522         mmc_omap_fclk_state(host, ON);
 523         clk_enable(host->iclk);
 524         clk_enable(host->dbclk);
 525
 526         OMAP_HSMMC_WRITE(host->base, HCTL,
 527                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 528         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 529         /*
 530          * If a MMC dual voltage card is detected, the set_ios fn calls
 531          * this fn with VDD bit set for 1.8V. Upon card removal from the
 532          * slot, mmc_omap_detect fn sets the VDD back to 3V.
 533          *
 534          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 535          * set in HCTL.
 536          */
 537         if (host->id == OMAP_MMC1_DEVID) {
 538                 if (((1 << vdd) == MMC_VDD_32_33) ||
 539                     ((1 << vdd) == MMC_VDD_33_34))
 540                         reg_val |= SDVS30;
 541                 else if ((1 << vdd) == MMC_VDD_165_195)
 542                         reg_val |= SDVS18;
 543         } else
 544                 reg_val |= SDVS18;
 545
 546         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 547
 548         OMAP_HSMMC_WRITE(host->base, HCTL,
 549                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 550
 551         return 0;
 552 err:
 553         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 554         return ret;
 555 }
 556
 557 /*
 558  * Work Item to notify the core about card insertion/removal
 559  */
 560 static void mmc_omap_detect(struct work_struct *work)
 561 {
 562         u16 vdd = 0;
 563         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 564                                                 mmc_carddetect_work);
 565
 566         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 567         mmc_omap_fclk_state(host, ON);
 568         if (host->carddetect) {
 569                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 570                         /*
 571                          * Set the VDD back to 3V when the card is removed
 572                          * before the set_ios fn turns off the power.
 573                          */
 574                         vdd = fls(host->mmc->ocr_avail) - 1;
 575                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 576                                 host->mmc->ios.vdd = vdd;
 577                 }
 578                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 579         } else {
 580                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 581                         OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
 582                 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
 583                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 584         }
 585         mmc_omap_fclk_lazy_disable(host);
 586 }
 587
 588 /*
 589  * ISR for handling card insertion and removal
 590  */
 591 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 592 {
 593         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 594
 595         host->carddetect = mmc_slot(host).card_detect(irq);
 596         schedule_work(&host->mmc_carddetect_work);
 597
 598         return IRQ_HANDLED;
 599 }
 600
 601 /*
 602  * DMA call back function
 603  */
 604 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 605 {
 606         struct mmc_omap_host *host = data;
 607
 608         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 609                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 610
 611         if (host->dma_ch < 0)
 612                 return;
 613
 614         omap_free_dma(host->dma_ch);
 615         host->dma_ch = -1;
 616         /*
 617          * DMA Callback: run in interrupt context.
 618          * mutex_unlock will through a kernel warning if used.
 619          */
 620         up(&host->sem);
 621 }
 622
 623 /*
 624  * Configure dma src and destination parameters
 625  */
 626 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 627                                 struct mmc_data *data)
 628 {
 629         if (sync_dir == 0) {
 630                 omap_set_dma_dest_params(host->dma_ch, 0,
 631                         OMAP_DMA_AMODE_CONSTANT,
 632                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 633                 omap_set_dma_src_params(host->dma_ch, 0,
 634                         OMAP_DMA_AMODE_POST_INC,
 635                         sg_dma_address(&data->sg[0]), 0, 0);
 636         } else {
 637                 omap_set_dma_src_params(host->dma_ch, 0,
 638                         OMAP_DMA_AMODE_CONSTANT,
 639                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 640                 omap_set_dma_dest_params(host->dma_ch, 0,
 641                         OMAP_DMA_AMODE_POST_INC,
 642                         sg_dma_address(&data->sg[0]), 0, 0);
 643         }
 644         return 0;
 645 }
 646 /*
 647  * Routine to configure and start DMA for the MMC card
 648  */
 649 static int
 650 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 651 {
 652         int sync_dev, sync_dir = 0;
 653         int dma_ch = 0, ret = 0, err = 1;
 654         struct mmc_data *data = req->data;
 655
 656         /*
 657          * If for some reason the DMA transfer is still active,
 658          * we wait for timeout period and free the dma
 659          */
 660         if (host->dma_ch != -1) {
 661                 set_current_state(TASK_UNINTERRUPTIBLE);
 662                 schedule_timeout(100);
 663                 if (down_trylock(&host->sem)) {
 664                         omap_free_dma(host->dma_ch);
 665                         host->dma_ch = -1;
 666                         up(&host->sem);
 667                         return err;
 668                 }
 669         } else {
 670                 if (down_trylock(&host->sem))
 671                         return err;
 672         }
 673
 674         if (!(data->flags & MMC_DATA_WRITE)) {
 675                 host->dma_dir = DMA_FROM_DEVICE;
 676                 if (host->id == OMAP_MMC1_DEVID)
 677                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 678                 else
 679                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 680         } else {
 681                 host->dma_dir = DMA_TO_DEVICE;
 682                 if (host->id == OMAP_MMC1_DEVID)
 683                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 684                 else
 685                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 686         }
 687
 688         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 689                         host, &dma_ch);
 690         if (ret != 0) {
 691                 dev_dbg(mmc_dev(host->mmc),
 692                         "%s: omap_request_dma() failed with %d\n",
 693                         mmc_hostname(host->mmc), ret);
 694                 return ret;
 695         }
 696
 697         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 698                         data->sg_len, host->dma_dir);
 699         host->dma_ch = dma_ch;
 700
 701         if (!(data->flags & MMC_DATA_WRITE))
 702                 mmc_omap_config_dma_param(1, host, data);
 703         else
 704                 mmc_omap_config_dma_param(0, host, data);
 705
 706         if ((data->blksz % 4) == 0)
 707                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 708                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 709                         sync_dev, sync_dir);
 710         else
 711                 /* REVISIT: The MMC buffer increments only when MSB is written.
 712                  * Return error for blksz which is non multiple of four.
 713                  */
 714                 return -EINVAL;
 715
 716         omap_start_dma(dma_ch);
 717         return 0;
 718 }
 719
 720 static void set_data_timeout(struct mmc_omap_host *host,
 721                              struct mmc_request *req)
 722 {
 723         unsigned int timeout, cycle_ns;
 724         uint32_t reg, clkd, dto = 0;
 725
 726         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 727         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 728         if (clkd == 0)
 729                 clkd = 1;
 730
 731         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 732         timeout = req->data->timeout_ns / cycle_ns;
 733         timeout += req->data->timeout_clks;
 734         if (timeout) {
 735                 while ((timeout & 0x80000000) == 0) {
 736                         dto += 1;
 737                         timeout <<= 1;
 738                 }
 739                 dto = 31 - dto;
 740                 timeout <<= 1;
 741                 if (timeout && dto)
 742                         dto += 1;
 743                 if (dto >= 13)
 744                         dto -= 13;
 745                 else
 746                         dto = 0;
 747                 if (dto > 14)
 748                         dto = 14;
 749         }
 750
 751         reg &= ~DTO_MASK;
 752         reg |= dto << DTO_SHIFT;
 753         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 754 }
 755
 756 /*
 757  * Configure block length for MMC/SD cards and initiate the transfer.
 758  */
 759 static int
 760 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 761 {
 762         int ret;
 763         host->data = req->data;
 764
 765         if (req->data == NULL) {
 766                 host->datadir = OMAP_MMC_DATADIR_NONE;
 767                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 768                 return 0;
 769         }
 770
 771         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 772                                         | (req->data->blocks << 16));
 773         set_data_timeout(host, req);
 774
 775         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 776                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 777
 778         if (host->use_dma) {
 779                 ret = mmc_omap_start_dma_transfer(host, req);
 780                 if (ret != 0) {
 781                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 782                         return ret;
 783                 }
 784         }
 785         return 0;
 786 }
 787
 788 /*
 789  * Request function. for read/write operation
 790  */
 791 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 792 {
 793         struct mmc_omap_host *host = mmc_priv(mmc);
 794
 795         WARN_ON(host->mrq != NULL);
 796         host->mrq = req;
 797         mmc_omap_fclk_state(host, ON);
 798         mmc_omap_prepare_data(host, req);
 799         mmc_omap_start_command(host, req->cmd, req->data);
 800 }
 801
 802 /* Routine to configure clock values. Exposed API to core */
 803 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 804 {
 805         struct mmc_omap_host *host = mmc_priv(mmc);
 806         u16 dsor = 0;
 807         unsigned long regval;
 808         unsigned long timeout;
 809
 810         mmc_omap_fclk_state(host, ON);
 811
 812         switch (ios->power_mode) {
 813         case MMC_POWER_OFF:
 814                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 815                 break;
 816         case MMC_POWER_UP:
 817                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 818                 break;
 819         }
 820
 821         switch (mmc->ios.bus_width) {
 822         case MMC_BUS_WIDTH_4:
 823                 OMAP_HSMMC_WRITE(host->base, HCTL,
 824                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 825                 break;
 826         case MMC_BUS_WIDTH_1:
 827                 OMAP_HSMMC_WRITE(host->base, HCTL,
 828                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 829                 break;
 830         }
 831
 832         if (host->id == OMAP_MMC1_DEVID) {
 833                 /* Only MMC1 can operate at 3V/1.8V */
 834                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 835                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 836                                 /*
 837                                  * The mmc_select_voltage fn of the core does
 838                                  * not seem to set the power_mode to
 839                                  * MMC_POWER_UP upon recalculating the voltage.
 840                                  * vdd 1.8v.
 841                                  */
 842                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 843                                         dev_dbg(mmc_dev(host->mmc),
 844                                                 "Switch operation failed\n");
 845                 }
 846         }
 847
 848         if (ios->clock) {
 849                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 850                 if (dsor < 1)
 851                         dsor = 1;
 852
 853                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 854                         dsor++;
 855
 856                 if (dsor > 250)
 857                         dsor = 250;
 858         }
 859         omap_mmc_stop_clock(host);
 860         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 861         regval = regval & ~(CLKD_MASK);
 862         regval = regval | (dsor << 6) | (DTO << 16);
 863         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 864         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 865                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 866
 867         /* Wait till the ICS bit is set */
 868         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 869         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 870                 && time_before(jiffies, timeout))
 871                 msleep(1);
 872
 873         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 874                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 875
 876         if (ios->power_mode == MMC_POWER_ON)
 877                 send_init_stream(host);
 878
 879         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 880                 OMAP_HSMMC_WRITE(host->base, CON,
 881                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 882
 883         mmc_omap_fclk_lazy_disable(host);
 884 }
 885
 886 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 887 {
 888         struct mmc_omap_host *host = mmc_priv(mmc);
 889         struct omap_mmc_platform_data *pdata = host->pdata;
 890
 891         if (!pdata->slots[0].card_detect)
 892                 return -ENOSYS;
 893         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 894 }
 895
 896 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 897 {
 898         struct mmc_omap_host *host = mmc_priv(mmc);
 899         struct omap_mmc_platform_data *pdata = host->pdata;
 900
 901         if (!pdata->slots[0].get_ro)
 902                 return -ENOSYS;
 903         return pdata->slots[0].get_ro(host->dev, 0);
 904 }
 905
 906 static struct mmc_host_ops mmc_omap_ops = {
 907         .request = omap_mmc_request,
 908         .set_ios = omap_mmc_set_ios,
 909         .get_cd = omap_hsmmc_get_cd,
 910         .get_ro = omap_hsmmc_get_ro,
 911         /* NYET -- enable_sdio_irq */
 912 };
 913
 914 static int __init omap_mmc_probe(struct platform_device *pdev)
 915 {
 916         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 917         struct mmc_host *mmc;
 918         struct mmc_omap_host *host = NULL;
 919         struct resource *res;
 920         int ret = 0, irq, reg;
 921         u32 hctl, capa;
 922
 923         if (pdata == NULL) {
 924                 dev_err(&pdev->dev, "Platform Data is missing\n");
 925                 return -ENXIO;
 926         }
 927
 928         if (pdata->nr_slots == 0) {
 929                 dev_err(&pdev->dev, "No Slots\n");
 930                 return -ENXIO;
 931         }
 932
 933         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 934         irq = platform_get_irq(pdev, 0);
 935         if (res == NULL || irq < 0)
 936                 return -ENXIO;
 937
 938         res = request_mem_region(res->start, res->end - res->start + 1,
 939                                                         pdev->name);
 940         if (res == NULL)
 941                 return -EBUSY;
 942
 943         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 944         if (!mmc) {
 945                 ret = -ENOMEM;
 946                 goto err;
 947         }
 948
 949         host            = mmc_priv(mmc);
 950         host->mmc       = mmc;
 951         host->pdata     = pdata;
 952         host->dev       = &pdev->dev;
 953         host->use_dma   = 1;
 954         host->dev->dma_mask = &pdata->dma_mask;
 955         host->dma_ch    = -1;
 956         host->irq       = irq;
 957         host->id        = pdev->id;
 958         host->slot_id   = 0;
 959         host->mapbase   = res->start;
 960         host->base      = ioremap(host->mapbase, SZ_4K);
 961
 962         platform_set_drvdata(pdev, host);
 963         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 964
 965         mmc->ops        = &mmc_omap_ops;
 966         mmc->f_min      = 400000;
 967         mmc->f_max      = 52000000;
 968
 969         sema_init(&host->sem, 1);
 970
 971         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 972         if (IS_ERR(host->iclk)) {
 973                 ret = PTR_ERR(host->iclk);
 974                 host->iclk = NULL;
 975                 goto err1;
 976         }
 977         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 978         if (IS_ERR(host->fclk)) {
 979                 ret = PTR_ERR(host->fclk);
 980                 host->fclk = NULL;
 981                 clk_put(host->iclk);
 982                 goto err1;
 983         }
 984
 985         spin_lock_init(&host->clk_lock);
 986         setup_timer(&host->idle_timer, mmc_omap_idle_timer,
 987                     (unsigned long) host);
 988
 989         if (mmc_omap_fclk_state(host, ON) != 0) {
 990                 clk_put(host->iclk);
 991                 clk_put(host->fclk);
 992                 goto err1;
 993         }
 994         if (clk_enable(host->iclk) != 0) {
 995                 mmc_omap_fclk_state(host, OFF);
 996                 clk_put(host->iclk);
 997                 clk_put(host->fclk);
 998                 goto err1;
 999         }
1000
1001         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1002         /*
1003          * MMC can still work without debounce clock.
1004          */
1005         if (IS_ERR(host->dbclk))
1006                 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1007         else
1008                 if (clk_enable(host->dbclk) != 0)
1009                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1010                                                         " clk failed\n");
1011                 else
1012                         host->dbclk_enabled = 1;
1013
1014 #ifdef CONFIG_MMC_BLOCK_BOUNCE
1015         mmc->max_phys_segs = 1;
1016         mmc->max_hw_segs = 1;
1017 #endif
1018         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1019         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1020         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1021         mmc->max_seg_size = mmc->max_req_size;
1022
1023         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1024         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1025
1026         if (pdata->slots[host->slot_id].wires >= 4)
1027                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1028
1029         /* Only MMC1 supports 3.0V */
1030         if (host->id == OMAP_MMC1_DEVID) {
1031                 hctl = SDVS30;
1032                 capa = VS30 | VS18;
1033         } else {
1034                 hctl = SDVS18;
1035                 capa = VS18;
1036         }
1037
1038         OMAP_HSMMC_WRITE(host->base, HCTL,
1039                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
1040
1041         OMAP_HSMMC_WRITE(host->base, CAPA,
1042                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
1043
1044         /* Set the controller to AUTO IDLE mode */
1045         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
1046                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
1047
1048         /* Set SD bus power bit */
1049         OMAP_HSMMC_WRITE(host->base, HCTL,
1050                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1051
1052         /* Request IRQ for MMC operations */
1053         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1054                         mmc_hostname(mmc), host);
1055         if (ret) {
1056                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1057                 goto err_irq;
1058         }
1059
1060         if (pdata->init != NULL) {
1061                 if (pdata->init(&pdev->dev) != 0) {
1062                         dev_dbg(mmc_dev(host->mmc),
1063                                 "Unable to configure MMC IRQs\n");
1064                         goto err_irq_cd_init;
1065                 }
1066         }
1067
1068         /* Request IRQ for card detect */
1069         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1070                 ret = request_irq(mmc_slot(host).card_detect_irq,
1071                                   omap_mmc_cd_handler,
1072                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1073                                           | IRQF_DISABLED,
1074                                   mmc_hostname(mmc), host);
1075                 if (ret) {
1076                         dev_dbg(mmc_dev(host->mmc),
1077                                 "Unable to grab MMC CD IRQ\n");
1078                         goto err_irq_cd;
1079                 }
1080         }
1081
1082         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1083         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1084
1085         mmc_add_host(mmc);
1086
1087         if (host->pdata->slots[host->slot_id].name != NULL) {
1088                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1089                 if (ret < 0)
1090                         goto err_slot_name;
1091         }
1092         if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1093                         host->pdata->slots[host->slot_id].get_cover_state) {
1094                 ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch);
1095                 if (ret < 0)
1096                         goto err_cover_switch;
1097         }
1098         mmc_omap_fclk_lazy_disable(host);
1099
1100         return 0;
1101
1102 err_cover_switch:
1103         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1104 err_slot_name:
1105         mmc_remove_host(mmc);
1106 err_irq_cd:
1107         free_irq(mmc_slot(host).card_detect_irq, host);
1108 err_irq_cd_init:
1109         free_irq(host->irq, host);
1110 err_irq:
1111         mmc_omap_fclk_state(host, OFF);
1112         clk_disable(host->iclk);
1113         clk_put(host->fclk);
1114         clk_put(host->iclk);
1115         if (host->dbclk_enabled) {
1116                 clk_disable(host->dbclk);
1117                 clk_put(host->dbclk);
1118         }
1119
1120 err1:
1121         iounmap(host->base);
1122 err:
1123         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1124         release_mem_region(res->start, res->end - res->start + 1);
1125         if (host)
1126                 mmc_free_host(mmc);
1127         return ret;
1128 }
1129
1130 static int omap_mmc_remove(struct platform_device *pdev)
1131 {
1132         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1133         struct resource *res;
1134         u16 vdd = 0;
1135
1136         if (host) {
1137                 mmc_omap_fclk_state(host, ON);
1138                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1139                         /*
1140                          * Set the vdd back to 3V,
1141                          * applicable for dual volt support.
1142                          */
1143                         vdd = fls(host->mmc->ocr_avail) - 1;
1144                         if (omap_mmc_switch_opcond(host, vdd) != 0)
1145                                 host->mmc->ios.vdd = vdd;
1146                 }
1147         }
1148
1149         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1150         if (res)
1151                 release_mem_region(res->start, res->end - res->start + 1);
1152
1153         platform_set_drvdata(pdev, NULL);
1154         if (host) {
1155                 mmc_remove_host(host->mmc);
1156                 if (host->pdata->cleanup)
1157                         host->pdata->cleanup(&pdev->dev);
1158                 free_irq(host->irq, host);
1159                 if (mmc_slot(host).card_detect_irq)
1160                         free_irq(mmc_slot(host).card_detect_irq, host);
1161                 flush_scheduled_work();
1162
1163                 mmc_omap_fclk_state(host, OFF);
1164                 clk_disable(host->iclk);
1165                 clk_put(host->fclk);
1166                 clk_put(host->iclk);
1167                 if (host->dbclk_enabled) {
1168                         clk_disable(host->dbclk);
1169                         clk_put(host->dbclk);
1170                 }
1171
1172                 mmc_free_host(host->mmc);
1173                 iounmap(host->base);
1174         }
1175
1176         return 0;
1177 }
1178
1179 #ifdef CONFIG_PM
1180 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1181 {
1182         int ret = 0;
1183         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1184
1185         if (host && host->suspended)
1186                 return 0;
1187
1188         if (host) {
1189                 ret = mmc_suspend_host(host->mmc, state);
1190                 if (ret == 0) {
1191                         host->suspended = 1;
1192
1193                         mmc_omap_fclk_state(host, ON);
1194                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1195                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1196
1197                         if (host->pdata->suspend) {
1198                                 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1199                                 if (ret)
1200                                         dev_dbg(mmc_dev(host->mmc),
1201                                                 "Unable to handle MMC board"
1202                                                 " level suspend\n");
1203                         }
1204
1205                         OMAP_HSMMC_WRITE(host->base, HCTL,
1206                                          OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1207                         mmc_omap_fclk_state(host, OFF);
1208                         clk_disable(host->iclk);
1209                         clk_disable(host->dbclk);
1210                 }
1211
1212         }
1213         return ret;
1214 }
1215
1216 /* Routine to resume the MMC device */
1217 static int omap_mmc_resume(struct platform_device *pdev)
1218 {
1219         int ret = 0;
1220         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1221
1222         if (host && !host->suspended)
1223                 return 0;
1224
1225         if (host) {
1226                 int i;
1227                 if (mmc_omap_fclk_state(host, ON) != 0)
1228                         goto clk_en_err;
1229
1230                 ret = clk_enable(host->iclk);
1231                 if (ret) {
1232                         mmc_omap_fclk_state(host, OFF);
1233                         clk_put(host->fclk);
1234                         goto clk_en_err;
1235                 }
1236
1237                 if (clk_enable(host->dbclk) != 0)
1238                         dev_dbg(mmc_dev(host->mmc),
1239                                         "Enabling debounce clk failed\n");
1240
1241                 OMAP_HSMMC_WRITE(host->base, HCTL,
1242                                  OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1243
1244                 for (i = 0; i < 100; i++)
1245                         if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1246                                 break;
1247
1248                 if (host->pdata->resume) {
1249                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1250                         if (ret)
1251                                 dev_dbg(mmc_dev(host->mmc),
1252                                         "Unmask interrupt failed\n");
1253                 }
1254
1255                 /* Notify the core to resume the host */
1256                 ret = mmc_resume_host(host->mmc);
1257                 if (ret == 0)
1258                         host->suspended = 0;
1259
1260                 mmc_omap_fclk_lazy_disable(host);
1261         }
1262
1263         return ret;
1264
1265 clk_en_err:
1266         dev_dbg(mmc_dev(host->mmc),
1267                 "Failed to enable MMC clocks during resume\n");
1268         return ret;
1269 }
1270
1271 #else
1272 #define omap_mmc_suspend        NULL
1273 #define omap_mmc_resume         NULL
1274 #endif
1275
1276 static struct platform_driver omap_mmc_driver = {
1277         .probe          = omap_mmc_probe,
1278         .remove         = omap_mmc_remove,
1279         .suspend        = omap_mmc_suspend,
1280         .resume         = omap_mmc_resume,
1281         .driver         = {
1282                 .name = DRIVER_NAME,
1283                 .owner = THIS_MODULE,
1284         },
1285 };
1286
1287 static int __init omap_mmc_init(void)
1288 {
1289         /* Register the MMC driver */
1290         return platform_driver_register(&omap_mmc_driver);
1291 }
1292
1293 static void __exit omap_mmc_cleanup(void)
1294 {
1295         /* Unregister MMC driver */
1296         platform_driver_unregister(&omap_mmc_driver);
1297 }
1298
1299 module_init(omap_mmc_init);
1300 module_exit(omap_mmc_cleanup);
1301
1302 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1303 MODULE_LICENSE("GPL");
1304 MODULE_ALIAS("platform:" DRIVER_NAME);
1305 MODULE_AUTHOR("Texas Instruments Inc");