drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <asm/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1 << 8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1 << 2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define CLKD_SHIFT              6
  68 #define DTO_MASK                0x000F0000
  69 #define DTO_SHIFT               16
  70 #define INT_EN_MASK             0x307F0033
  71 #define INIT_STREAM             (1 << 1)
  72 #define DP_SELECT               (1 << 21)
  73 #define DDIR                    (1 << 4)
  74 #define DMA_EN                  0x1
  75 #define MSBS                    (1 << 5)
  76 #define BCE                     (1 << 1)
  77 #define FOUR_BIT                (1 << 1)
  78 #define CC                      0x1
  79 #define TC                      0x02
  80 #define OD                      0x1
  81 #define ERR                     (1 << 15)
  82 #define CMD_TIMEOUT             (1 << 16)
  83 #define DATA_TIMEOUT            (1 << 20)
  84 #define CMD_CRC                 (1 << 17)
  85 #define DATA_CRC                (1 << 21)
  86 #define CARD_ERR                (1 << 28)
  87 #define STAT_CLEAR              0xFFFFFFFF
  88 #define INIT_STREAM_CMD         0x00000000
  89 #define DUAL_VOLT_OCR_BIT       7
  90 #define SRC                     (1 << 25)
  91 #define SRD                     (1 << 26)
  92
  93 /*
  94  * FIXME: Most likely all the data using these _DEVID defines should come
  95  * from the platform_data, or implemented in controller and slot specific
  96  * functions.
  97  */
  98 #define OMAP_MMC1_DEVID         0
  99 #define OMAP_MMC2_DEVID         1
 100
 101 #define OMAP_MMC_DATADIR_NONE   0
 102 #define OMAP_MMC_DATADIR_READ   1
 103 #define OMAP_MMC_DATADIR_WRITE  2
 104 #define MMC_TIMEOUT_MS          20
 105 #define OMAP_MMC_MASTER_CLOCK   96000000
 106 #define DRIVER_NAME             "mmci-omap-hs"
 107
 108 /*
 109  * One controller can have multiple slots, like on some omap boards using
 110  * omap.c controller driver. Luckily this is not currently done on any known
 111  * omap_hsmmc.c device.
 112  */
 113 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 114
 115 /*
 116  * MMC Host controller read/write API's
 117  */
 118 #define OMAP_HSMMC_READ(base, reg)      \
 119         __raw_readl((base) + OMAP_HSMMC_##reg)
 120
 121 #define OMAP_HSMMC_WRITE(base, reg, val) \
 122         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 123
 124 enum {OFF = 0, ON};
 125 #define IDLE_TIMEOUT (jiffies_to_msecs(10))
 126
 127 struct mmc_omap_host {
 128         struct  device          *dev;
 129         struct  mmc_host        *mmc;
 130         struct  mmc_request     *mrq;
 131         struct  mmc_command     *cmd;
 132         struct  mmc_data        *data;
 133         struct  clk             *fclk;
 134         struct  clk             *iclk;
 135         struct  clk             *dbclk;
 136         struct  semaphore       sem;
 137         struct  work_struct     mmc_carddetect_work;
 138         void    __iomem         *base;
 139         resource_size_t         mapbase;
 140         unsigned int            id;
 141         unsigned int            dma_len;
 142         unsigned int            dma_dir;
 143         unsigned char           bus_mode;
 144         unsigned char           datadir;
 145         u32                     *buffer;
 146         u32                     bytesleft;
 147         int                     suspended;
 148         int                     irq;
 149         int                     carddetect;
 150         int                     use_dma, dma_ch;
 151         int                     initstr;
 152         int                     slot_id;
 153         int                     dbclk_enabled;
 154
 155         struct timer_list       idle_timer;
 156         spinlock_t              clk_lock;     /* for changing enabled state */
 157         unsigned int            fclk_enabled:1;
 158
 159         struct  omap_mmc_platform_data  *pdata;
 160 };
 161
 162 static int mmc_omap_fclk_state(struct mmc_omap_host *host, unsigned int state)
 163 {
 164         unsigned long flags;
 165         int ret = 0;
 166
 167         spin_lock_irqsave(&host->clk_lock, flags);
 168         del_timer(&host->idle_timer);
 169         if (host->fclk_enabled != state) {
 170                 if (state == ON) {
 171                         ret = clk_enable(host->fclk);
 172                         if (ret != 0)
 173                                 goto err_out;
 174
 175                         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
 176                 } else {
 177                         clk_disable(host->fclk);
 178                         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
 179                 }
 180                 host->fclk_enabled = state;
 181         }
 182
 183 err_out:
 184         spin_unlock_irqrestore(&host->clk_lock, flags);
 185         return ret;
 186 }
 187
 188 static void mmc_omap_idle_timer(unsigned long data)
 189 {
 190         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 191
 192         mmc_omap_fclk_state(host, OFF);
 193 }
 194
 195 static void mmc_omap_fclk_lazy_disable(struct mmc_omap_host *host)
 196 {
 197         mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
 198 }
 199
 200 /*
 201  * Stop clock to the card
 202  */
 203 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 204 {
 205         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 206                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 207         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 208                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 209 }
 210
 211 /*
 212  * Send init stream sequence to card
 213  * before sending IDLE command
 214  */
 215 static void send_init_stream(struct mmc_omap_host *host)
 216 {
 217         int reg = 0;
 218         unsigned long timeout;
 219
 220         disable_irq(host->irq);
 221         OMAP_HSMMC_WRITE(host->base, CON,
 222                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 223         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 224
 225         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 226         while ((reg != CC) && time_before(jiffies, timeout))
 227                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 228
 229         OMAP_HSMMC_WRITE(host->base, CON,
 230                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 231         enable_irq(host->irq);
 232 }
 233
 234 static inline
 235 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 236 {
 237         if (host->pdata->slots[host->slot_id].get_cover_state)
 238                 return host->pdata->slots[host->slot_id].get_cover_state(host->dev, host->slot_id);
 239         return 1;
 240 }
 241
 242 static ssize_t
 243 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 244                            char *buf)
 245 {
 246         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 247         struct mmc_omap_host *host = mmc_priv(mmc);
 248
 249         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 250                        "open");
 251 }
 252
 253 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 254
 255 static ssize_t
 256 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 257                         char *buf)
 258 {
 259         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 260         struct mmc_omap_host *host = mmc_priv(mmc);
 261         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 262
 263         return sprintf(buf, "slot:%s\n", slot.name);
 264 }
 265
 266 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 267
 268 /*
 269  * Configure the response type and send the cmd.
 270  */
 271 static void
 272 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 273         struct mmc_data *data)
 274 {
 275         int cmdreg = 0, resptype = 0, cmdtype = 0;
 276
 277         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 278                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 279         host->cmd = cmd;
 280
 281         /*
 282          * Clear status bits and enable interrupts
 283          */
 284         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 285         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 286         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 287
 288         if (cmd->flags & MMC_RSP_PRESENT) {
 289                 if (cmd->flags & MMC_RSP_136)
 290                         resptype = 1;
 291                 else
 292                         resptype = 2;
 293         }
 294
 295         /*
 296          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 297          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 298          * a val of 0x3, rest 0x0.
 299          */
 300         if (cmd == host->mrq->stop)
 301                 cmdtype = 0x3;
 302
 303         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 304
 305         if (data) {
 306                 cmdreg |= DP_SELECT | MSBS | BCE;
 307                 if (data->flags & MMC_DATA_READ)
 308                         cmdreg |= DDIR;
 309                 else
 310                         cmdreg &= ~(DDIR);
 311         }
 312
 313         if (host->use_dma)
 314                 cmdreg |= DMA_EN;
 315
 316         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 317         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 318 }
 319
 320 /*
 321  * Notify the transfer complete to MMC core
 322  */
 323 static void
 324 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 325 {
 326         host->data = NULL;
 327
 328         if (host->use_dma && host->dma_ch != -1)
 329                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 330                         host->dma_dir);
 331
 332         host->datadir = OMAP_MMC_DATADIR_NONE;
 333
 334         if (!data->error)
 335                 data->bytes_xfered += data->blocks * (data->blksz);
 336         else
 337                 data->bytes_xfered = 0;
 338
 339         if (!data->stop) {
 340                 host->mrq = NULL;
 341                 mmc_omap_fclk_lazy_disable(host);
 342                 mmc_request_done(host->mmc, data->mrq);
 343                 return;
 344         }
 345         mmc_omap_start_command(host, data->stop, NULL);
 346 }
 347
 348 /*
 349  * Notify the core about command completion
 350  */
 351 static void
 352 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 353 {
 354         host->cmd = NULL;
 355
 356         if (cmd->flags & MMC_RSP_PRESENT) {
 357                 if (cmd->flags & MMC_RSP_136) {
 358                         /* response type 2 */
 359                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 360                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 361                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 362                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 363                 } else {
 364                         /* response types 1, 1b, 3, 4, 5, 6 */
 365                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 366                 }
 367         }
 368         if (host->data == NULL || cmd->error) {
 369                 host->mrq = NULL;
 370                 mmc_omap_fclk_lazy_disable(host);
 371                 mmc_request_done(host->mmc, cmd->mrq);
 372         }
 373 }
 374
 375 /*
 376  * DMA clean up for command errors
 377  */
 378 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 379 {
 380         host->data->error = -ETIMEDOUT;
 381
 382         if (host->use_dma && host->dma_ch != -1) {
 383                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 384                         host->dma_dir);
 385                 omap_free_dma(host->dma_ch);
 386                 host->dma_ch = -1;
 387                 up(&host->sem);
 388         }
 389         host->data = NULL;
 390         host->datadir = OMAP_MMC_DATADIR_NONE;
 391 }
 392
 393 /*
 394  * Readable error output
 395  */
 396 #ifdef CONFIG_MMC_DEBUG
 397 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 398 {
 399         /* --- means reserved bit without definition at documentation */
 400         static const char *mmc_omap_status_bits[] = {
 401                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 402                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 403                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 404                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 405         };
 406         int i;
 407
 408         dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
 409
 410         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 411                 if (status & (1 << i))
 412                         /*
 413                          * KERN_* facility is not used here because this should
 414                          * print a single line.
 415                          */
 416                         printk(" %s", mmc_omap_status_bits[i]);
 417
 418         printk("\n");
 419
 420 }
 421 #endif  /* CONFIG_MMC_DEBUG */
 422
 423
 424 /*
 425  * MMC controller IRQ handler
 426  */
 427 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 428 {
 429         struct mmc_omap_host *host = dev_id;
 430         struct mmc_data *data;
 431         int end_cmd = 0, end_trans = 0, status;
 432
 433         if (host->cmd == NULL && host->data == NULL) {
 434                 OMAP_HSMMC_WRITE(host->base, STAT,
 435                         OMAP_HSMMC_READ(host->base, STAT));
 436                 return IRQ_HANDLED;
 437         }
 438
 439         data = host->data;
 440         status = OMAP_HSMMC_READ(host->base, STAT);
 441         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 442
 443         if (status & ERR) {
 444 #ifdef CONFIG_MMC_DEBUG
 445                 mmc_omap_report_irq(host, status);
 446 #endif
 447                 if ((status & CMD_TIMEOUT) ||
 448                         (status & CMD_CRC)) {
 449                         if (host->cmd) {
 450                                 if (status & CMD_TIMEOUT) {
 451                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 452                                                 OMAP_HSMMC_READ(host->base,
 453                                                                 SYSCTL) | SRC);
 454                                         while (OMAP_HSMMC_READ(host->base,
 455                                                                 SYSCTL) & SRC) ;
 456                                         host->cmd->error = -ETIMEDOUT;
 457                                 } else {
 458                                         host->cmd->error = -EILSEQ;
 459                                 }
 460                                 end_cmd = 1;
 461                         }
 462                         if (host->data)
 463                                 mmc_dma_cleanup(host);
 464                 }
 465                 if ((status & DATA_TIMEOUT) ||
 466                         (status & DATA_CRC)) {
 467                         if (host->data) {
 468                                 if (status & DATA_TIMEOUT)
 469                                         mmc_dma_cleanup(host);
 470                                 else
 471                                         host->data->error = -EILSEQ;
 472                                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 473                                         OMAP_HSMMC_READ(host->base,
 474                                                         SYSCTL) | SRD);
 475                                 while (OMAP_HSMMC_READ(host->base,
 476                                                         SYSCTL) & SRD) ;
 477                                 end_trans = 1;
 478                         }
 479                 }
 480                 if (status & CARD_ERR) {
 481                         dev_dbg(mmc_dev(host->mmc),
 482                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 483                         if (host->cmd)
 484                                 end_cmd = 1;
 485                         if (host->data)
 486                                 end_trans = 1;
 487                 }
 488         }
 489
 490         OMAP_HSMMC_WRITE(host->base, STAT, status);
 491
 492         if (end_cmd || (status & CC))
 493                 mmc_omap_cmd_done(host, host->cmd);
 494         if (end_trans || (status & TC))
 495                 mmc_omap_xfer_done(host, data);
 496
 497         return IRQ_HANDLED;
 498 }
 499
 500 /*
 501  * Switch MMC operating voltage
 502  */
 503 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 504 {
 505         u32 reg_val = 0;
 506         int ret;
 507
 508         /* Disable the clocks */
 509         mmc_omap_fclk_state(host, OFF);
 510         clk_disable(host->iclk);
 511         clk_disable(host->dbclk);
 512
 513         /* Turn the power off */
 514         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 515         if (ret != 0)
 516                 goto err;
 517
 518         /* Turn the power ON with given VDD 1.8 or 3.0v */
 519         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 520         if (ret != 0)
 521                 goto err;
 522
 523         mmc_omap_fclk_state(host, ON);
 524         clk_enable(host->iclk);
 525         clk_enable(host->dbclk);
 526
 527         OMAP_HSMMC_WRITE(host->base, HCTL,
 528                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 529         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 530         /*
 531          * If a MMC dual voltage card is detected, the set_ios fn calls
 532          * this fn with VDD bit set for 1.8V. Upon card removal from the
 533          * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
 534          *
 535          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 536          * set in HCTL.
 537          */
 538         if (host->id == OMAP_MMC1_DEVID) {
 539                 if (((1 << vdd) == MMC_VDD_32_33) ||
 540                     ((1 << vdd) == MMC_VDD_33_34))
 541                         reg_val |= SDVS30;
 542                 else if ((1 << vdd) == MMC_VDD_165_195)
 543                         reg_val |= SDVS18;
 544         } else
 545                 reg_val |= SDVS18;
 546
 547         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 548
 549         OMAP_HSMMC_WRITE(host->base, HCTL,
 550                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 551
 552         return 0;
 553 err:
 554         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 555         return ret;
 556 }
 557
 558 /*
 559  * Work Item to notify the core about card insertion/removal
 560  */
 561 static void mmc_omap_detect(struct work_struct *work)
 562 {
 563         u16 vdd = 0;
 564         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 565                                                 mmc_carddetect_work);
 566
 567         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 568         mmc_omap_fclk_state(host, ON);
 569         if (host->carddetect) {
 570                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 571         } else {
 572                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 573                         OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
 574                 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
 575                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 576         }
 577         mmc_omap_fclk_lazy_disable(host);
 578 }
 579
 580 /*
 581  * ISR for handling card insertion and removal
 582  */
 583 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 584 {
 585         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 586
 587         host->carddetect = mmc_slot(host).card_detect(irq);
 588         schedule_work(&host->mmc_carddetect_work);
 589
 590         return IRQ_HANDLED;
 591 }
 592
 593 /*
 594  * DMA call back function
 595  */
 596 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 597 {
 598         struct mmc_omap_host *host = data;
 599
 600         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 601                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 602
 603         if (host->dma_ch < 0)
 604                 return;
 605
 606         omap_free_dma(host->dma_ch);
 607         host->dma_ch = -1;
 608         /*
 609          * DMA Callback: run in interrupt context.
 610          * mutex_unlock will through a kernel warning if used.
 611          */
 612         up(&host->sem);
 613 }
 614
 615 /*
 616  * Configure dma src and destination parameters
 617  */
 618 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 619                                 struct mmc_data *data)
 620 {
 621         if (sync_dir == 0) {
 622                 omap_set_dma_dest_params(host->dma_ch, 0,
 623                         OMAP_DMA_AMODE_CONSTANT,
 624                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 625                 omap_set_dma_src_params(host->dma_ch, 0,
 626                         OMAP_DMA_AMODE_POST_INC,
 627                         sg_dma_address(&data->sg[0]), 0, 0);
 628         } else {
 629                 omap_set_dma_src_params(host->dma_ch, 0,
 630                         OMAP_DMA_AMODE_CONSTANT,
 631                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 632                 omap_set_dma_dest_params(host->dma_ch, 0,
 633                         OMAP_DMA_AMODE_POST_INC,
 634                         sg_dma_address(&data->sg[0]), 0, 0);
 635         }
 636         return 0;
 637 }
 638 /*
 639  * Routine to configure and start DMA for the MMC card
 640  */
 641 static int
 642 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 643 {
 644         int sync_dev, sync_dir = 0;
 645         int dma_ch = 0, ret = 0, err = 1;
 646         struct mmc_data *data = req->data;
 647
 648         /*
 649          * If for some reason the DMA transfer is still active,
 650          * we wait for timeout period and free the dma
 651          */
 652         if (host->dma_ch != -1) {
 653                 set_current_state(TASK_UNINTERRUPTIBLE);
 654                 schedule_timeout(100);
 655                 if (down_trylock(&host->sem)) {
 656                         omap_free_dma(host->dma_ch);
 657                         host->dma_ch = -1;
 658                         up(&host->sem);
 659                         return err;
 660                 }
 661         } else {
 662                 if (down_trylock(&host->sem))
 663                         return err;
 664         }
 665
 666         if (!(data->flags & MMC_DATA_WRITE)) {
 667                 host->dma_dir = DMA_FROM_DEVICE;
 668                 if (host->id == OMAP_MMC1_DEVID)
 669                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 670                 else
 671                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 672         } else {
 673                 host->dma_dir = DMA_TO_DEVICE;
 674                 if (host->id == OMAP_MMC1_DEVID)
 675                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 676                 else
 677                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 678         }
 679
 680         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 681                         host, &dma_ch);
 682         if (ret != 0) {
 683                 dev_dbg(mmc_dev(host->mmc),
 684                         "%s: omap_request_dma() failed with %d\n",
 685                         mmc_hostname(host->mmc), ret);
 686                 return ret;
 687         }
 688
 689         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 690                         data->sg_len, host->dma_dir);
 691         host->dma_ch = dma_ch;
 692
 693         if (!(data->flags & MMC_DATA_WRITE))
 694                 mmc_omap_config_dma_param(1, host, data);
 695         else
 696                 mmc_omap_config_dma_param(0, host, data);
 697
 698         if ((data->blksz % 4) == 0)
 699                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 700                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 701                         sync_dev, sync_dir);
 702         else
 703                 /* REVISIT: The MMC buffer increments only when MSB is written.
 704                  * Return error for blksz which is non multiple of four.
 705                  */
 706                 return -EINVAL;
 707
 708         omap_start_dma(dma_ch);
 709         return 0;
 710 }
 711
 712 static void set_data_timeout(struct mmc_omap_host *host,
 713                              struct mmc_request *req)
 714 {
 715         unsigned int timeout, cycle_ns;
 716         uint32_t reg, clkd, dto = 0;
 717
 718         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 719         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 720         if (clkd == 0)
 721                 clkd = 1;
 722
 723         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 724         timeout = req->data->timeout_ns / cycle_ns;
 725         timeout += req->data->timeout_clks;
 726         if (timeout) {
 727                 while ((timeout & 0x80000000) == 0) {
 728                         dto += 1;
 729                         timeout <<= 1;
 730                 }
 731                 dto = 31 - dto;
 732                 timeout <<= 1;
 733                 if (timeout && dto)
 734                         dto += 1;
 735                 if (dto >= 13)
 736                         dto -= 13;
 737                 else
 738                         dto = 0;
 739                 if (dto > 14)
 740                         dto = 14;
 741         }
 742
 743         reg &= ~DTO_MASK;
 744         reg |= dto << DTO_SHIFT;
 745         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 746 }
 747
 748 /*
 749  * Configure block length for MMC/SD cards and initiate the transfer.
 750  */
 751 static int
 752 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 753 {
 754         int ret;
 755         host->data = req->data;
 756
 757         if (req->data == NULL) {
 758                 host->datadir = OMAP_MMC_DATADIR_NONE;
 759                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 760                 return 0;
 761         }
 762
 763         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 764                                         | (req->data->blocks << 16));
 765         set_data_timeout(host, req);
 766
 767         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 768                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 769
 770         if (host->use_dma) {
 771                 ret = mmc_omap_start_dma_transfer(host, req);
 772                 if (ret != 0) {
 773                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 774                         return ret;
 775                 }
 776         }
 777         return 0;
 778 }
 779
 780 /*
 781  * Request function. for read/write operation
 782  */
 783 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 784 {
 785         struct mmc_omap_host *host = mmc_priv(mmc);
 786
 787         WARN_ON(host->mrq != NULL);
 788         host->mrq = req;
 789         mmc_omap_fclk_state(host, ON);
 790         mmc_omap_prepare_data(host, req);
 791         mmc_omap_start_command(host, req->cmd, req->data);
 792 }
 793
 794 /* Routine to configure clock values. Exposed API to core */
 795 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 796 {
 797         struct mmc_omap_host *host = mmc_priv(mmc);
 798         u16 dsor = 0;
 799         unsigned long regval;
 800         unsigned long timeout;
 801
 802         mmc_omap_fclk_state(host, ON);
 803
 804         switch (ios->power_mode) {
 805         case MMC_POWER_OFF:
 806                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 807
 808                 /*
 809                  * Reset bus voltage to 3V if it got set to 1.8V earlier.
 810                  * REVISIT: If we are able to detect cards after unplugging
 811                  * a 1.8V card, this code should not be needed.
 812                  */
 813                 regval = OMAP_HSMMC_READ(host->base, HCTL);
 814                 if (regval & SDVSDET) {
 815                         regval &= ~SDVSDET;
 816                         OMAP_HSMMC_WRITE(host->base, HCTL, regval);
 817                 }
 818                 break;
 819         case MMC_POWER_UP:
 820                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 821                 break;
 822         }
 823
 824         switch (mmc->ios.bus_width) {
 825         case MMC_BUS_WIDTH_4:
 826                 OMAP_HSMMC_WRITE(host->base, HCTL,
 827                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 828                 break;
 829         case MMC_BUS_WIDTH_1:
 830                 OMAP_HSMMC_WRITE(host->base, HCTL,
 831                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 832                 break;
 833         }
 834
 835         if (host->id == OMAP_MMC1_DEVID) {
 836                 /* Only MMC1 can operate at 3V/1.8V */
 837                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 838                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 839                                 /*
 840                                  * The mmc_select_voltage fn of the core does
 841                                  * not seem to set the power_mode to
 842                                  * MMC_POWER_UP upon recalculating the voltage.
 843                                  * vdd 1.8v.
 844                                  */
 845                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 846                                         dev_dbg(mmc_dev(host->mmc),
 847                                                 "Switch operation failed\n");
 848                 }
 849         }
 850
 851         if (ios->clock) {
 852                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 853                 if (dsor < 1)
 854                         dsor = 1;
 855
 856                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 857                         dsor++;
 858
 859                 if (dsor > 250)
 860                         dsor = 250;
 861         }
 862         omap_mmc_stop_clock(host);
 863         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 864         regval = regval & ~(CLKD_MASK);
 865         regval = regval | (dsor << 6) | (DTO << 16);
 866         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 867         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 868                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 869
 870         /* Wait till the ICS bit is set */
 871         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 872         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 873                 && time_before(jiffies, timeout))
 874                 msleep(1);
 875
 876         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 877                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 878
 879         if (ios->power_mode == MMC_POWER_ON)
 880                 send_init_stream(host);
 881
 882         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 883                 OMAP_HSMMC_WRITE(host->base, CON,
 884                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 885
 886         mmc_omap_fclk_lazy_disable(host);
 887 }
 888
 889 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 890 {
 891         struct mmc_omap_host *host = mmc_priv(mmc);
 892         struct omap_mmc_platform_data *pdata = host->pdata;
 893
 894         if (!pdata->slots[0].card_detect)
 895                 return -ENOSYS;
 896         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 897 }
 898
 899 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 900 {
 901         struct mmc_omap_host *host = mmc_priv(mmc);
 902         struct omap_mmc_platform_data *pdata = host->pdata;
 903
 904         if (!pdata->slots[0].get_ro)
 905                 return -ENOSYS;
 906         return pdata->slots[0].get_ro(host->dev, 0);
 907 }
 908
 909 static struct mmc_host_ops mmc_omap_ops = {
 910         .request = omap_mmc_request,
 911         .set_ios = omap_mmc_set_ios,
 912         .get_cd = omap_hsmmc_get_cd,
 913         .get_ro = omap_hsmmc_get_ro,
 914         /* NYET -- enable_sdio_irq */
 915 };
 916
 917 static int __init omap_mmc_probe(struct platform_device *pdev)
 918 {
 919         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 920         struct mmc_host *mmc;
 921         struct mmc_omap_host *host = NULL;
 922         struct resource *res;
 923         int ret = 0, irq, reg;
 924         u32 hctl, capa;
 925
 926         if (pdata == NULL) {
 927                 dev_err(&pdev->dev, "Platform Data is missing\n");
 928                 return -ENXIO;
 929         }
 930
 931         if (pdata->nr_slots == 0) {
 932                 dev_err(&pdev->dev, "No Slots\n");
 933                 return -ENXIO;
 934         }
 935
 936         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 937         irq = platform_get_irq(pdev, 0);
 938         if (res == NULL || irq < 0)
 939                 return -ENXIO;
 940
 941         res = request_mem_region(res->start, res->end - res->start + 1,
 942                                                         pdev->name);
 943         if (res == NULL)
 944                 return -EBUSY;
 945
 946         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 947         if (!mmc) {
 948                 ret = -ENOMEM;
 949                 goto err;
 950         }
 951
 952         host            = mmc_priv(mmc);
 953         host->mmc       = mmc;
 954         host->pdata     = pdata;
 955         host->dev       = &pdev->dev;
 956         host->use_dma   = 1;
 957         host->dev->dma_mask = &pdata->dma_mask;
 958         host->dma_ch    = -1;
 959         host->irq       = irq;
 960         host->id        = pdev->id;
 961         host->slot_id   = 0;
 962         host->mapbase   = res->start;
 963         host->base      = ioremap(host->mapbase, SZ_4K);
 964
 965         platform_set_drvdata(pdev, host);
 966         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 967
 968         mmc->ops        = &mmc_omap_ops;
 969         mmc->f_min      = 400000;
 970         mmc->f_max      = 52000000;
 971
 972         sema_init(&host->sem, 1);
 973
 974         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 975         if (IS_ERR(host->iclk)) {
 976                 ret = PTR_ERR(host->iclk);
 977                 host->iclk = NULL;
 978                 goto err1;
 979         }
 980         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 981         if (IS_ERR(host->fclk)) {
 982                 ret = PTR_ERR(host->fclk);
 983                 host->fclk = NULL;
 984                 clk_put(host->iclk);
 985                 goto err1;
 986         }
 987
 988         spin_lock_init(&host->clk_lock);
 989         setup_timer(&host->idle_timer, mmc_omap_idle_timer,
 990                     (unsigned long) host);
 991
 992         if (mmc_omap_fclk_state(host, ON) != 0) {
 993                 clk_put(host->iclk);
 994                 clk_put(host->fclk);
 995                 goto err1;
 996         }
 997         if (clk_enable(host->iclk) != 0) {
 998                 mmc_omap_fclk_state(host, OFF);
 999                 clk_put(host->iclk);
1000                 clk_put(host->fclk);
1001                 goto err1;
1002         }
1003
1004         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1005         /*
1006          * MMC can still work without debounce clock.
1007          */
1008         if (IS_ERR(host->dbclk))
1009                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1010         else
1011                 if (clk_enable(host->dbclk) != 0)
1012                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1013                                                         " clk failed\n");
1014                 else
1015                         host->dbclk_enabled = 1;
1016
1017 #ifdef CONFIG_MMC_BLOCK_BOUNCE
1018         mmc->max_phys_segs = 1;
1019         mmc->max_hw_segs = 1;
1020 #endif
1021         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1022         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1023         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1024         mmc->max_seg_size = mmc->max_req_size;
1025
1026         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1027         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1028
1029         if (pdata->slots[host->slot_id].wires >= 4)
1030                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1031
1032         /* Only MMC1 supports 3.0V */
1033         if (host->id == OMAP_MMC1_DEVID) {
1034                 hctl = SDVS30;
1035                 capa = VS30 | VS18;
1036         } else {
1037                 hctl = SDVS18;
1038                 capa = VS18;
1039         }
1040
1041         OMAP_HSMMC_WRITE(host->base, HCTL,
1042                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
1043
1044         OMAP_HSMMC_WRITE(host->base, CAPA,
1045                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
1046
1047         /* Set the controller to AUTO IDLE mode */
1048         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
1049                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
1050
1051         /* Set SD bus power bit */
1052         OMAP_HSMMC_WRITE(host->base, HCTL,
1053                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1054
1055         /* Request IRQ for MMC operations */
1056         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1057                         mmc_hostname(mmc), host);
1058         if (ret) {
1059                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1060                 goto err_irq;
1061         }
1062
1063         if (pdata->init != NULL) {
1064                 if (pdata->init(&pdev->dev) != 0) {
1065                         dev_dbg(mmc_dev(host->mmc),
1066                                 "Unable to configure MMC IRQs\n");
1067                         goto err_irq_cd_init;
1068                 }
1069         }
1070
1071         /* Request IRQ for card detect */
1072         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1073                 ret = request_irq(mmc_slot(host).card_detect_irq,
1074                                   omap_mmc_cd_handler,
1075                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1076                                           | IRQF_DISABLED,
1077                                   mmc_hostname(mmc), host);
1078                 if (ret) {
1079                         dev_dbg(mmc_dev(host->mmc),
1080                                 "Unable to grab MMC CD IRQ\n");
1081                         goto err_irq_cd;
1082                 }
1083         }
1084
1085         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1086         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1087
1088         mmc_add_host(mmc);
1089
1090         if (host->pdata->slots[host->slot_id].name != NULL) {
1091                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1092                 if (ret < 0)
1093                         goto err_slot_name;
1094         }
1095         if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1096                         host->pdata->slots[host->slot_id].get_cover_state) {
1097                 ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch);
1098                 if (ret < 0)
1099                         goto err_cover_switch;
1100         }
1101         mmc_omap_fclk_lazy_disable(host);
1102
1103         return 0;
1104
1105 err_cover_switch:
1106         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1107 err_slot_name:
1108         mmc_remove_host(mmc);
1109 err_irq_cd:
1110         free_irq(mmc_slot(host).card_detect_irq, host);
1111 err_irq_cd_init:
1112         free_irq(host->irq, host);
1113 err_irq:
1114         mmc_omap_fclk_state(host, OFF);
1115         clk_disable(host->iclk);
1116         clk_put(host->fclk);
1117         clk_put(host->iclk);
1118         if (host->dbclk_enabled) {
1119                 clk_disable(host->dbclk);
1120                 clk_put(host->dbclk);
1121         }
1122
1123 err1:
1124         iounmap(host->base);
1125 err:
1126         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1127         release_mem_region(res->start, res->end - res->start + 1);
1128         if (host)
1129                 mmc_free_host(mmc);
1130         return ret;
1131 }
1132
1133 static int omap_mmc_remove(struct platform_device *pdev)
1134 {
1135         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1136         struct resource *res;
1137
1138         if (host) {
1139                 mmc_remove_host(host->mmc);
1140                 if (host->pdata->cleanup)
1141                         host->pdata->cleanup(&pdev->dev);
1142                 free_irq(host->irq, host);
1143                 if (mmc_slot(host).card_detect_irq)
1144                         free_irq(mmc_slot(host).card_detect_irq, host);
1145                 flush_scheduled_work();
1146
1147                 mmc_omap_fclk_state(host, OFF);
1148                 clk_disable(host->iclk);
1149                 clk_put(host->fclk);
1150                 clk_put(host->iclk);
1151                 if (host->dbclk_enabled) {
1152                         clk_disable(host->dbclk);
1153                         clk_put(host->dbclk);
1154                 }
1155
1156                 mmc_free_host(host->mmc);
1157                 iounmap(host->base);
1158         }
1159
1160         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1161         if (res)
1162                 release_mem_region(res->start, res->end - res->start + 1);
1163         platform_set_drvdata(pdev, NULL);
1164
1165         return 0;
1166 }
1167
1168 #ifdef CONFIG_PM
1169 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1170 {
1171         int ret = 0;
1172         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1173
1174         if (host && host->suspended)
1175                 return 0;
1176
1177         if (host) {
1178                 ret = mmc_suspend_host(host->mmc, state);
1179                 if (ret == 0) {
1180                         host->suspended = 1;
1181
1182                         mmc_omap_fclk_state(host, ON);
1183                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1184                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1185
1186                         if (host->pdata->suspend) {
1187                                 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1188                                 if (ret)
1189                                         dev_dbg(mmc_dev(host->mmc),
1190                                                 "Unable to handle MMC board"
1191                                                 " level suspend\n");
1192                         }
1193
1194                         OMAP_HSMMC_WRITE(host->base, HCTL,
1195                                          OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1196                         mmc_omap_fclk_state(host, OFF);
1197                         clk_disable(host->iclk);
1198                         clk_disable(host->dbclk);
1199                 }
1200
1201         }
1202         return ret;
1203 }
1204
1205 /* Routine to resume the MMC device */
1206 static int omap_mmc_resume(struct platform_device *pdev)
1207 {
1208         int ret = 0;
1209         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1210
1211         if (host && !host->suspended)
1212                 return 0;
1213
1214         if (host) {
1215                 int i;
1216                 if (mmc_omap_fclk_state(host, ON) != 0)
1217                         goto clk_en_err;
1218
1219                 ret = clk_enable(host->iclk);
1220                 if (ret) {
1221                         mmc_omap_fclk_state(host, OFF);
1222                         clk_put(host->fclk);
1223                         goto clk_en_err;
1224                 }
1225
1226                 if (clk_enable(host->dbclk) != 0)
1227                         dev_dbg(mmc_dev(host->mmc),
1228                                         "Enabling debounce clk failed\n");
1229
1230                 OMAP_HSMMC_WRITE(host->base, HCTL,
1231                                  OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1232
1233                 for (i = 0; i < 100; i++)
1234                         if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1235                                 break;
1236
1237                 if (host->pdata->resume) {
1238                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1239                         if (ret)
1240                                 dev_dbg(mmc_dev(host->mmc),
1241                                         "Unmask interrupt failed\n");
1242                 }
1243
1244                 /* Notify the core to resume the host */
1245                 ret = mmc_resume_host(host->mmc);
1246                 if (ret == 0)
1247                         host->suspended = 0;
1248
1249                 mmc_omap_fclk_lazy_disable(host);
1250         }
1251
1252         return ret;
1253
1254 clk_en_err:
1255         dev_dbg(mmc_dev(host->mmc),
1256                 "Failed to enable MMC clocks during resume\n");
1257         return ret;
1258 }
1259
1260 #else
1261 #define omap_mmc_suspend        NULL
1262 #define omap_mmc_resume         NULL
1263 #endif
1264
1265 static struct platform_driver omap_mmc_driver = {
1266         .probe          = omap_mmc_probe,
1267         .remove         = omap_mmc_remove,
1268         .suspend        = omap_mmc_suspend,
1269         .resume         = omap_mmc_resume,
1270         .driver         = {
1271                 .name = DRIVER_NAME,
1272                 .owner = THIS_MODULE,
1273         },
1274 };
1275
1276 static int __init omap_mmc_init(void)
1277 {
1278         /* Register the MMC driver */
1279         return platform_driver_register(&omap_mmc_driver);
1280 }
1281
1282 static void __exit omap_mmc_cleanup(void)
1283 {
1284         /* Unregister MMC driver */
1285         platform_driver_unregister(&omap_mmc_driver);
1286 }
1287
1288 module_init(omap_mmc_init);
1289 module_exit(omap_mmc_cleanup);
1290
1291 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1292 MODULE_LICENSE("GPL");
1293 MODULE_ALIAS("platform:" DRIVER_NAME);
1294 MODULE_AUTHOR("Texas Instruments Inc");