drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <asm/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1 << 8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1 << 2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define CLKD_SHIFT              6
  68 #define DTO_MASK                0x000F0000
  69 #define DTO_SHIFT               16
  70 #define INT_EN_MASK             0x307F0033
  71 #define INIT_STREAM             (1 << 1)
  72 #define DP_SELECT               (1 << 21)
  73 #define DDIR                    (1 << 4)
  74 #define DMA_EN                  0x1
  75 #define MSBS                    (1 << 5)
  76 #define BCE                     (1 << 1)
  77 #define FOUR_BIT                (1 << 1)
  78 #define CC                      0x1
  79 #define TC                      0x02
  80 #define OD                      0x1
  81 #define ERR                     (1 << 15)
  82 #define CMD_TIMEOUT             (1 << 16)
  83 #define DATA_TIMEOUT            (1 << 20)
  84 #define CMD_CRC                 (1 << 17)
  85 #define DATA_CRC                (1 << 21)
  86 #define CARD_ERR                (1 << 28)
  87 #define STAT_CLEAR              0xFFFFFFFF
  88 #define INIT_STREAM_CMD         0x00000000
  89 #define DUAL_VOLT_OCR_BIT       7
  90 #define SRC                     (1 << 25)
  91 #define SRD                     (1 << 26)
  92
  93 /*
  94  * FIXME: Most likely all the data using these _DEVID defines should come
  95  * from the platform_data, or implemented in controller and slot specific
  96  * functions.
  97  */
  98 #define OMAP_MMC1_DEVID         0
  99 #define OMAP_MMC2_DEVID         1
 100
 101 #define MMC_TIMEOUT_MS          20
 102 #define OMAP_MMC_MASTER_CLOCK   96000000
 103 #define DRIVER_NAME             "mmci-omap"
 104
 105 /*
 106  * One controller can have multiple slots, like on some omap boards using
 107  * omap.c controller driver. Luckily this is not currently done on any known
 108  * omap_hsmmc.c device.
 109  */
 110 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 111
 112 /*
 113  * MMC Host controller read/write API's
 114  */
 115 #define OMAP_HSMMC_READ(base, reg)      \
 116         __raw_readl((base) + OMAP_HSMMC_##reg)
 117
 118 #define OMAP_HSMMC_WRITE(base, reg, val) \
 119         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 120
 121 enum {OFF = 0, ON};
 122 #define IDLE_TIMEOUT (jiffies_to_msecs(10))
 123
 124 struct mmc_omap_host {
 125         struct  device          *dev;
 126         struct  mmc_host        *mmc;
 127         struct  mmc_request     *mrq;
 128         struct  mmc_command     *cmd;
 129         struct  mmc_data        *data;
 130         struct  clk             *fclk;
 131         struct  clk             *iclk;
 132         struct  clk             *dbclk;
 133         struct  semaphore       sem;
 134         struct  work_struct     mmc_carddetect_work;
 135         void    __iomem         *base;
 136         resource_size_t         mapbase;
 137         unsigned int            id;
 138         unsigned int            dma_len;
 139         unsigned int            dma_sg_idx;
 140         unsigned char           bus_mode;
 141         u32                     *buffer;
 142         u32                     bytesleft;
 143         int                     suspended;
 144         int                     irq;
 145         int                     carddetect;
 146         int                     use_dma, dma_ch;
 147         int                     slot_id;
 148         int                     dbclk_enabled;
 149
 150         struct timer_list       idle_timer;
 151         spinlock_t              clk_lock;     /* for changing enabled state */
 152         unsigned int            fclk_enabled:1;
 153
 154         struct  omap_mmc_platform_data  *pdata;
 155 };
 156
 157 static int mmc_omap_fclk_state(struct mmc_omap_host *host, unsigned int state)
 158 {
 159         unsigned long flags;
 160         int ret = 0;
 161
 162         spin_lock_irqsave(&host->clk_lock, flags);
 163         del_timer(&host->idle_timer);
 164         if (host->fclk_enabled != state) {
 165                 if (state == ON) {
 166                         ret = clk_enable(host->fclk);
 167                         if (ret != 0)
 168                                 goto err_out;
 169
 170                         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
 171                 } else {
 172                         clk_disable(host->fclk);
 173                         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
 174                 }
 175                 host->fclk_enabled = state;
 176         }
 177
 178 err_out:
 179         spin_unlock_irqrestore(&host->clk_lock, flags);
 180         return ret;
 181 }
 182
 183 static void mmc_omap_idle_timer(unsigned long data)
 184 {
 185         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 186
 187         mmc_omap_fclk_state(host, OFF);
 188 }
 189
 190 static void mmc_omap_fclk_lazy_disable(struct mmc_omap_host *host)
 191 {
 192         mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
 193 }
 194
 195 /*
 196  * Stop clock to the card
 197  */
 198 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 199 {
 200         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 201                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 202         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 203                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 204 }
 205
 206 /*
 207  * Send init stream sequence to card
 208  * before sending IDLE command
 209  */
 210 static void send_init_stream(struct mmc_omap_host *host)
 211 {
 212         int reg = 0;
 213         unsigned long timeout;
 214
 215         disable_irq(host->irq);
 216         OMAP_HSMMC_WRITE(host->base, CON,
 217                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 218         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 219
 220         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 221         while ((reg != CC) && time_before(jiffies, timeout))
 222                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 223
 224         OMAP_HSMMC_WRITE(host->base, CON,
 225                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 226         enable_irq(host->irq);
 227 }
 228
 229 static inline
 230 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 231 {
 232         if (host->pdata->slots[host->slot_id].get_cover_state)
 233                 return host->pdata->slots[host->slot_id].get_cover_state(host->dev, host->slot_id);
 234         return 1;
 235 }
 236
 237 static ssize_t
 238 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 239                            char *buf)
 240 {
 241         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 242         struct mmc_omap_host *host = mmc_priv(mmc);
 243
 244         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 245                        "open");
 246 }
 247
 248 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 249
 250 static ssize_t
 251 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 252                         char *buf)
 253 {
 254         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 255         struct mmc_omap_host *host = mmc_priv(mmc);
 256         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 257
 258         return sprintf(buf, "slot:%s\n", slot.name);
 259 }
 260
 261 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 262
 263 /*
 264  * Configure the response type and send the cmd.
 265  */
 266 static void
 267 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 268         struct mmc_data *data)
 269 {
 270         int cmdreg = 0, resptype = 0, cmdtype = 0;
 271
 272         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 273                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 274         host->cmd = cmd;
 275
 276         /*
 277          * Clear status bits and enable interrupts
 278          */
 279         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 280         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 281         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 282
 283         if (cmd->flags & MMC_RSP_PRESENT) {
 284                 if (cmd->flags & MMC_RSP_136)
 285                         resptype = 1;
 286                 else
 287                         resptype = 2;
 288         }
 289
 290         /*
 291          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 292          * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
 293          */
 294         if (cmd->opcode == 12)
 295                 cmdtype = 0x3;
 296
 297         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 298
 299         if (data) {
 300                 cmdreg |= DP_SELECT | MSBS | BCE;
 301                 if (data->flags & MMC_DATA_READ)
 302                         cmdreg |= DDIR;
 303                 else
 304                         cmdreg &= ~(DDIR);
 305         }
 306
 307         if (host->use_dma)
 308                 cmdreg |= DMA_EN;
 309
 310         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 311         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 312 }
 313
 314 static int
 315 mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
 316 {
 317         if (data->flags & MMC_DATA_WRITE)
 318                 return DMA_TO_DEVICE;
 319         else
 320                 return DMA_FROM_DEVICE;
 321 }
 322
 323 /*
 324  * Notify the transfer complete to MMC core
 325  */
 326 static void
 327 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 328 {
 329         host->data = NULL;
 330
 331         if (host->use_dma && host->dma_ch != -1)
 332                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 333                         mmc_omap_get_dma_dir(host, data));
 334
 335         if (!data->error)
 336                 data->bytes_xfered += data->blocks * (data->blksz);
 337         else
 338                 data->bytes_xfered = 0;
 339
 340         if (!data->stop) {
 341                 host->mrq = NULL;
 342                 mmc_omap_fclk_lazy_disable(host);
 343                 mmc_request_done(host->mmc, data->mrq);
 344                 return;
 345         }
 346         mmc_omap_start_command(host, data->stop, NULL);
 347 }
 348
 349 /*
 350  * Notify the core about command completion
 351  */
 352 static void
 353 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 354 {
 355         host->cmd = NULL;
 356
 357         if (cmd->flags & MMC_RSP_PRESENT) {
 358                 if (cmd->flags & MMC_RSP_136) {
 359                         /* response type 2 */
 360                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 361                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 362                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 363                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 364                 } else {
 365                         /* response types 1, 1b, 3, 4, 5, 6 */
 366                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 367                 }
 368         }
 369         if (host->data == NULL || cmd->error) {
 370                 host->mrq = NULL;
 371                 mmc_omap_fclk_lazy_disable(host);
 372                 mmc_request_done(host->mmc, cmd->mrq);
 373         }
 374 }
 375
 376 /*
 377  * DMA clean up for command errors
 378  */
 379 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 380 {
 381         host->data->error = -ETIMEDOUT;
 382
 383         if (host->use_dma && host->dma_ch != -1) {
 384                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 385                         mmc_omap_get_dma_dir(host, host->data));
 386                 omap_free_dma(host->dma_ch);
 387                 host->dma_ch = -1;
 388                 up(&host->sem);
 389         }
 390         host->data = NULL;
 391 }
 392
 393 /*
 394  * Readable error output
 395  */
 396 #ifdef CONFIG_MMC_DEBUG
 397 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 398 {
 399         /* --- means reserved bit without definition at documentation */
 400         static const char *mmc_omap_status_bits[] = {
 401                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 402                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 403                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 404                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 405         };
 406         int i;
 407
 408         dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
 409
 410         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 411                 if (status & (1 << i))
 412                         /*
 413                          * KERN_* facility is not used here because this should
 414                          * print a single line.
 415                          */
 416                         printk(" %s", mmc_omap_status_bits[i]);
 417
 418         printk("\n");
 419
 420 }
 421 #endif  /* CONFIG_MMC_DEBUG */
 422
 423
 424 /*
 425  * MMC controller IRQ handler
 426  */
 427 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 428 {
 429         struct mmc_omap_host *host = dev_id;
 430         struct mmc_data *data;
 431         int end_cmd = 0, end_trans = 0, status;
 432
 433         if (host->cmd == NULL && host->data == NULL) {
 434                 OMAP_HSMMC_WRITE(host->base, STAT,
 435                         OMAP_HSMMC_READ(host->base, STAT));
 436                 return IRQ_HANDLED;
 437         }
 438
 439         data = host->data;
 440         status = OMAP_HSMMC_READ(host->base, STAT);
 441         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 442
 443         if (status & ERR) {
 444 #ifdef CONFIG_MMC_DEBUG
 445                 mmc_omap_report_irq(host, status);
 446 #endif
 447                 if ((status & CMD_TIMEOUT) ||
 448                         (status & CMD_CRC)) {
 449                         if (host->cmd) {
 450                                 if (status & CMD_TIMEOUT) {
 451                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 452                                                 OMAP_HSMMC_READ(host->base,
 453                                                                 SYSCTL) | SRC);
 454                                         while (OMAP_HSMMC_READ(host->base,
 455                                                                 SYSCTL) & SRC) ;
 456                                         host->cmd->error = -ETIMEDOUT;
 457                                 } else {
 458                                         host->cmd->error = -EILSEQ;
 459                                 }
 460                                 end_cmd = 1;
 461                         }
 462                         if (host->data)
 463                                 mmc_dma_cleanup(host);
 464                 }
 465                 if ((status & DATA_TIMEOUT) ||
 466                         (status & DATA_CRC)) {
 467                         if (host->data) {
 468                                 if (status & DATA_TIMEOUT)
 469                                         mmc_dma_cleanup(host);
 470                                 else
 471                                         host->data->error = -EILSEQ;
 472                                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 473                                         OMAP_HSMMC_READ(host->base,
 474                                                         SYSCTL) | SRD);
 475                                 while (OMAP_HSMMC_READ(host->base,
 476                                                         SYSCTL) & SRD) ;
 477                                 end_trans = 1;
 478                         }
 479                 }
 480                 if (status & CARD_ERR) {
 481                         dev_dbg(mmc_dev(host->mmc),
 482                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 483                         if (host->cmd)
 484                                 end_cmd = 1;
 485                         if (host->data)
 486                                 end_trans = 1;
 487                 }
 488         }
 489
 490         OMAP_HSMMC_WRITE(host->base, STAT, status);
 491
 492         if (end_cmd || (status & CC))
 493                 mmc_omap_cmd_done(host, host->cmd);
 494         if (end_trans || (status & TC))
 495                 mmc_omap_xfer_done(host, data);
 496
 497         return IRQ_HANDLED;
 498 }
 499
 500 /*
 501  * Switch MMC operating voltage
 502  */
 503 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 504 {
 505         u32 reg_val = 0;
 506         int ret;
 507
 508         /* Disable the clocks */
 509         mmc_omap_fclk_state(host, OFF);
 510         clk_disable(host->iclk);
 511         clk_disable(host->dbclk);
 512
 513         /* Turn the power off */
 514         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 515         if (ret != 0)
 516                 goto err;
 517
 518         /* Turn the power ON with given VDD 1.8 or 3.0v */
 519         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 520         if (ret != 0)
 521                 goto err;
 522
 523         mmc_omap_fclk_state(host, ON);
 524         clk_enable(host->iclk);
 525         clk_enable(host->dbclk);
 526
 527         OMAP_HSMMC_WRITE(host->base, HCTL,
 528                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 529         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 530         /*
 531          * If a MMC dual voltage card is detected, the set_ios fn calls
 532          * this fn with VDD bit set for 1.8V. Upon card removal from the
 533          * slot, mmc_omap_detect fn sets the VDD back to 3V.
 534          *
 535          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 536          * set in HCTL.
 537          */
 538         if (host->id == OMAP_MMC1_DEVID) {
 539                 if (((1 << vdd) == MMC_VDD_32_33) ||
 540                     ((1 << vdd) == MMC_VDD_33_34))
 541                         reg_val |= SDVS30;
 542                 else if ((1 << vdd) == MMC_VDD_165_195)
 543                         reg_val |= SDVS18;
 544         } else
 545                 reg_val |= SDVS18;
 546
 547         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 548
 549         OMAP_HSMMC_WRITE(host->base, HCTL,
 550                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 551
 552         return 0;
 553 err:
 554         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 555         return ret;
 556 }
 557
 558 /*
 559  * Work Item to notify the core about card insertion/removal
 560  */
 561 static void mmc_omap_detect(struct work_struct *work)
 562 {
 563         u16 vdd = 0;
 564         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 565                                                 mmc_carddetect_work);
 566
 567         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 568         mmc_omap_fclk_state(host, ON);
 569         if (host->carddetect) {
 570                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 571                         /*
 572                          * Set the VDD back to 3V when the card is removed
 573                          * before the set_ios fn turns off the power.
 574                          */
 575                         vdd = fls(host->mmc->ocr_avail) - 1;
 576                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 577                                 host->mmc->ios.vdd = vdd;
 578                 }
 579                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 580         } else {
 581                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 582                         OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
 583                 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
 584                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 585         }
 586         mmc_omap_fclk_lazy_disable(host);
 587 }
 588
 589 /*
 590  * ISR for handling card insertion and removal
 591  */
 592 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 593 {
 594         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 595
 596         host->carddetect = mmc_slot(host).card_detect(irq);
 597         schedule_work(&host->mmc_carddetect_work);
 598
 599         return IRQ_HANDLED;
 600 }
 601
 602 static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
 603                                      struct mmc_data *data)
 604 {
 605         int sync_dev;
 606
 607         if (data->flags & MMC_DATA_WRITE) {
 608                 if (host->id == OMAP_MMC1_DEVID)
 609                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 610                 else
 611                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 612         } else {
 613                 if (host->id == OMAP_MMC1_DEVID)
 614                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 615                 else
 616                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 617         }
 618         return sync_dev;
 619 }
 620
 621 static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
 622                                        struct mmc_data *data,
 623                                        struct scatterlist *sgl)
 624 {
 625         int blksz, nblk, dma_ch;
 626
 627         dma_ch = host->dma_ch;
 628         if (data->flags & MMC_DATA_WRITE) {
 629                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 630                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 631                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 632                         sg_dma_address(sgl), 0, 0);
 633         } else {
 634                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 635                                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 636                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 637                         sg_dma_address(sgl), 0, 0);
 638         }
 639
 640         blksz = host->data->blksz;
 641         nblk = sg_dma_len(sgl) / blksz;
 642
 643         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 644                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
 645                         mmc_omap_get_dma_sync_dev(host, data),
 646                         !(data->flags & MMC_DATA_WRITE));
 647
 648         omap_start_dma(dma_ch);
 649 }
 650
 651 /*
 652  * DMA call back function
 653  */
 654 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 655 {
 656         struct mmc_omap_host *host = data;
 657
 658         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 659                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 660
 661         if (host->dma_ch < 0)
 662                 return;
 663
 664         host->dma_sg_idx++;
 665         if (host->dma_sg_idx < host->dma_len) {
 666                 /* Fire up the next transfer. */
 667                 mmc_omap_config_dma_params(host, host->data,
 668                                            host->data->sg + host->dma_sg_idx);
 669                 return;
 670         }
 671
 672         omap_free_dma(host->dma_ch);
 673         host->dma_ch = -1;
 674         /*
 675          * DMA Callback: run in interrupt context.
 676          * mutex_unlock will through a kernel warning if used.
 677          */
 678         up(&host->sem);
 679 }
 680
 681 /*
 682  * Routine to configure and start DMA for the MMC card
 683  */
 684 static int
 685 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 686 {
 687         int dma_ch = 0, ret = 0, err = 1, i;
 688         struct mmc_data *data = req->data;
 689
 690         /* Sanity check: all the SG entries must be aligned by block size. */
 691         for (i = 0; i < host->dma_len; i++) {
 692                 struct scatterlist *sgl;
 693
 694                 sgl = data->sg + i;
 695                 if (sgl->length % data->blksz)
 696                         return -EINVAL;
 697         }
 698         if ((data->blksz % 4) != 0)
 699                 /* REVISIT: The MMC buffer increments only when MSB is written.
 700                  * Return error for blksz which is non multiple of four.
 701                  */
 702                 return -EINVAL;
 703
 704         /*
 705          * If for some reason the DMA transfer is still active,
 706          * we wait for timeout period and free the dma
 707          */
 708         if (host->dma_ch != -1) {
 709                 set_current_state(TASK_UNINTERRUPTIBLE);
 710                 schedule_timeout(100);
 711                 if (down_trylock(&host->sem)) {
 712                         omap_free_dma(host->dma_ch);
 713                         host->dma_ch = -1;
 714                         up(&host->sem);
 715                         return err;
 716                 }
 717         } else {
 718                 if (down_trylock(&host->sem))
 719                         return err;
 720         }
 721
 722         ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
 723                                mmc_omap_dma_cb,host, &dma_ch);
 724         if (ret != 0) {
 725                 dev_err(mmc_dev(host->mmc),
 726                         "%s: omap_request_dma() failed with %d\n",
 727                         mmc_hostname(host->mmc), ret);
 728                 return ret;
 729         }
 730
 731         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 732                         data->sg_len, mmc_omap_get_dma_dir(host, data));
 733         host->dma_ch = dma_ch;
 734         host->dma_sg_idx = 0;
 735
 736         mmc_omap_config_dma_params(host, data, data->sg);
 737
 738         return 0;
 739 }
 740
 741 static void set_data_timeout(struct mmc_omap_host *host,
 742                              struct mmc_request *req)
 743 {
 744         unsigned int timeout, cycle_ns;
 745         uint32_t reg, clkd, dto = 0;
 746
 747         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 748         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 749         if (clkd == 0)
 750                 clkd = 1;
 751
 752         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 753         timeout = req->data->timeout_ns / cycle_ns;
 754         timeout += req->data->timeout_clks;
 755         if (timeout) {
 756                 while ((timeout & 0x80000000) == 0) {
 757                         dto += 1;
 758                         timeout <<= 1;
 759                 }
 760                 dto = 31 - dto;
 761                 timeout <<= 1;
 762                 if (timeout && dto)
 763                         dto += 1;
 764                 if (dto >= 13)
 765                         dto -= 13;
 766                 else
 767                         dto = 0;
 768                 if (dto > 14)
 769                         dto = 14;
 770         }
 771
 772         reg &= ~DTO_MASK;
 773         reg |= dto << DTO_SHIFT;
 774         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 775 }
 776
 777 /*
 778  * Configure block length for MMC/SD cards and initiate the transfer.
 779  */
 780 static int
 781 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 782 {
 783         int ret;
 784         host->data = req->data;
 785
 786         if (req->data == NULL) {
 787                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 788                 return 0;
 789         }
 790
 791         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 792                                         | (req->data->blocks << 16));
 793         set_data_timeout(host, req);
 794
 795         if (host->use_dma) {
 796                 ret = mmc_omap_start_dma_transfer(host, req);
 797                 if (ret != 0) {
 798                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 799                         return ret;
 800                 }
 801         }
 802         return 0;
 803 }
 804
 805 /*
 806  * Request function. for read/write operation
 807  */
 808 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 809 {
 810         struct mmc_omap_host *host = mmc_priv(mmc);
 811
 812         WARN_ON(host->mrq != NULL);
 813         host->mrq = req;
 814         mmc_omap_fclk_state(host, ON);
 815         mmc_omap_prepare_data(host, req);
 816         mmc_omap_start_command(host, req->cmd, req->data);
 817 }
 818
 819 /* Routine to configure clock values. Exposed API to core */
 820 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 821 {
 822         struct mmc_omap_host *host = mmc_priv(mmc);
 823         u16 dsor = 0;
 824         unsigned long regval;
 825         unsigned long timeout;
 826
 827         mmc_omap_fclk_state(host, ON);
 828
 829         switch (ios->power_mode) {
 830         case MMC_POWER_OFF:
 831                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 832                 break;
 833         case MMC_POWER_UP:
 834                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 835                 break;
 836         }
 837
 838         switch (mmc->ios.bus_width) {
 839         case MMC_BUS_WIDTH_4:
 840                 OMAP_HSMMC_WRITE(host->base, HCTL,
 841                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 842                 break;
 843         case MMC_BUS_WIDTH_1:
 844                 OMAP_HSMMC_WRITE(host->base, HCTL,
 845                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 846                 break;
 847         }
 848
 849         if (host->id == OMAP_MMC1_DEVID) {
 850                 /* Only MMC1 can operate at 3V/1.8V */
 851                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 852                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 853                                 /*
 854                                  * The mmc_select_voltage fn of the core does
 855                                  * not seem to set the power_mode to
 856                                  * MMC_POWER_UP upon recalculating the voltage.
 857                                  * vdd 1.8v.
 858                                  */
 859                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 860                                         dev_dbg(mmc_dev(host->mmc),
 861                                                 "Switch operation failed\n");
 862                 }
 863         }
 864
 865         if (ios->clock) {
 866                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 867                 if (dsor < 1)
 868                         dsor = 1;
 869
 870                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 871                         dsor++;
 872
 873                 if (dsor > 250)
 874                         dsor = 250;
 875         }
 876         omap_mmc_stop_clock(host);
 877         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 878         regval = regval & ~(CLKD_MASK);
 879         regval = regval | (dsor << 6) | (DTO << 16);
 880         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 881         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 882                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 883
 884         /* Wait till the ICS bit is set */
 885         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 886         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 887                 && time_before(jiffies, timeout))
 888                 msleep(1);
 889
 890         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 891                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 892
 893         if (ios->power_mode == MMC_POWER_ON)
 894                 send_init_stream(host);
 895
 896         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 897                 OMAP_HSMMC_WRITE(host->base, CON,
 898                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 899
 900         if (ios->power_mode == MMC_POWER_OFF)
 901                 mmc_omap_fclk_state(host, OFF);
 902         else
 903                 mmc_omap_fclk_lazy_disable(host);
 904 }
 905
 906 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 907 {
 908         struct mmc_omap_host *host = mmc_priv(mmc);
 909         struct omap_mmc_platform_data *pdata = host->pdata;
 910
 911         if (!pdata->slots[0].card_detect)
 912                 return -ENOSYS;
 913         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 914 }
 915
 916 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 917 {
 918         struct mmc_omap_host *host = mmc_priv(mmc);
 919         struct omap_mmc_platform_data *pdata = host->pdata;
 920
 921         if (!pdata->slots[0].get_ro)
 922                 return -ENOSYS;
 923         return pdata->slots[0].get_ro(host->dev, 0);
 924 }
 925
 926 static struct mmc_host_ops mmc_omap_ops = {
 927         .request = omap_mmc_request,
 928         .set_ios = omap_mmc_set_ios,
 929         .get_cd = omap_hsmmc_get_cd,
 930         .get_ro = omap_hsmmc_get_ro,
 931         /* NYET -- enable_sdio_irq */
 932 };
 933
 934 static int __init omap_mmc_probe(struct platform_device *pdev)
 935 {
 936         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 937         struct mmc_host *mmc;
 938         struct mmc_omap_host *host = NULL;
 939         struct resource *res;
 940         int ret = 0, irq;
 941         u32 hctl, capa;
 942
 943         if (pdata == NULL) {
 944                 dev_err(&pdev->dev, "Platform Data is missing\n");
 945                 return -ENXIO;
 946         }
 947
 948         if (pdata->nr_slots == 0) {
 949                 dev_err(&pdev->dev, "No Slots\n");
 950                 return -ENXIO;
 951         }
 952
 953         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 954         irq = platform_get_irq(pdev, 0);
 955         if (res == NULL || irq < 0)
 956                 return -ENXIO;
 957
 958         res = request_mem_region(res->start, res->end - res->start + 1,
 959                                                         pdev->name);
 960         if (res == NULL)
 961                 return -EBUSY;
 962
 963         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 964         if (!mmc) {
 965                 ret = -ENOMEM;
 966                 goto err;
 967         }
 968
 969         host            = mmc_priv(mmc);
 970         host->mmc       = mmc;
 971         host->pdata     = pdata;
 972         host->dev       = &pdev->dev;
 973         host->use_dma   = 1;
 974         host->dev->dma_mask = &pdata->dma_mask;
 975         host->dma_ch    = -1;
 976         host->irq       = irq;
 977         host->id        = pdev->id;
 978         host->slot_id   = 0;
 979         host->mapbase   = res->start;
 980         host->base      = ioremap(host->mapbase, SZ_4K);
 981
 982         platform_set_drvdata(pdev, host);
 983         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 984
 985         mmc->ops        = &mmc_omap_ops;
 986         mmc->f_min      = 400000;
 987         mmc->f_max      = 52000000;
 988
 989         sema_init(&host->sem, 1);
 990
 991         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 992         if (IS_ERR(host->iclk)) {
 993                 ret = PTR_ERR(host->iclk);
 994                 host->iclk = NULL;
 995                 goto err1;
 996         }
 997         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 998         if (IS_ERR(host->fclk)) {
 999                 ret = PTR_ERR(host->fclk);
1000                 host->fclk = NULL;
1001                 clk_put(host->iclk);
1002                 goto err1;
1003         }
1004
1005         spin_lock_init(&host->clk_lock);
1006         setup_timer(&host->idle_timer, mmc_omap_idle_timer,
1007                     (unsigned long) host);
1008
1009         if (mmc_omap_fclk_state(host, ON) != 0) {
1010                 clk_put(host->iclk);
1011                 clk_put(host->fclk);
1012                 goto err1;
1013         }
1014         if (clk_enable(host->iclk) != 0) {
1015                 mmc_omap_fclk_state(host, OFF);
1016                 clk_put(host->iclk);
1017                 clk_put(host->fclk);
1018                 goto err1;
1019         }
1020
1021         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1022         /*
1023          * MMC can still work without debounce clock.
1024          */
1025         if (IS_ERR(host->dbclk))
1026                 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1027         else
1028                 if (clk_enable(host->dbclk) != 0)
1029                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1030                                                         " clk failed\n");
1031                 else
1032                         host->dbclk_enabled = 1;
1033
1034         /* Since we do only SG emulation, we can have as many segs
1035          * as we want. */
1036         mmc->max_phys_segs = 1024;
1037         mmc->max_hw_segs = 1024;
1038
1039         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1040         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1041         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1042         mmc->max_seg_size = mmc->max_req_size;
1043
1044         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1045         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1046
1047         if (pdata->slots[host->slot_id].wires >= 4)
1048                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1049
1050         /* Only MMC1 supports 3.0V */
1051         if (host->id == OMAP_MMC1_DEVID) {
1052                 hctl = SDVS30;
1053                 capa = VS30 | VS18;
1054         } else {
1055                 hctl = SDVS18;
1056                 capa = VS18;
1057         }
1058
1059         OMAP_HSMMC_WRITE(host->base, HCTL,
1060                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
1061
1062         OMAP_HSMMC_WRITE(host->base, CAPA,
1063                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
1064
1065         /* Set the controller to AUTO IDLE mode */
1066         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
1067                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
1068
1069         /* Set SD bus power bit */
1070         OMAP_HSMMC_WRITE(host->base, HCTL,
1071                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1072
1073         /* Request IRQ for MMC operations */
1074         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1075                         mmc_hostname(mmc), host);
1076         if (ret) {
1077                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1078                 goto err_irq;
1079         }
1080
1081         if (pdata->init != NULL) {
1082                 if (pdata->init(&pdev->dev) != 0) {
1083                         dev_dbg(mmc_dev(host->mmc),
1084                                 "Unable to configure MMC IRQs\n");
1085                         goto err_irq_cd_init;
1086                 }
1087         }
1088
1089         /* Request IRQ for card detect */
1090         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1091                 ret = request_irq(mmc_slot(host).card_detect_irq,
1092                                   omap_mmc_cd_handler,
1093                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1094                                           | IRQF_DISABLED,
1095                                   mmc_hostname(mmc), host);
1096                 if (ret) {
1097                         dev_dbg(mmc_dev(host->mmc),
1098                                 "Unable to grab MMC CD IRQ\n");
1099                         goto err_irq_cd;
1100                 }
1101         }
1102
1103         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1104         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1105
1106         mmc_add_host(mmc);
1107
1108         if (host->pdata->slots[host->slot_id].name != NULL) {
1109                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1110                 if (ret < 0)
1111                         goto err_slot_name;
1112         }
1113         if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1114                         host->pdata->slots[host->slot_id].get_cover_state) {
1115                 ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch);
1116                 if (ret < 0)
1117                         goto err_cover_switch;
1118         }
1119         mmc_omap_fclk_lazy_disable(host);
1120
1121         return 0;
1122
1123 err_cover_switch:
1124         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1125 err_slot_name:
1126         mmc_remove_host(mmc);
1127 err_irq_cd:
1128         free_irq(mmc_slot(host).card_detect_irq, host);
1129 err_irq_cd_init:
1130         free_irq(host->irq, host);
1131 err_irq:
1132         mmc_omap_fclk_state(host, OFF);
1133         clk_disable(host->iclk);
1134         clk_put(host->fclk);
1135         clk_put(host->iclk);
1136         if (host->dbclk_enabled) {
1137                 clk_disable(host->dbclk);
1138                 clk_put(host->dbclk);
1139         }
1140
1141 err1:
1142         iounmap(host->base);
1143 err:
1144         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1145         release_mem_region(res->start, res->end - res->start + 1);
1146         if (host)
1147                 mmc_free_host(mmc);
1148         return ret;
1149 }
1150
1151 static int omap_mmc_remove(struct platform_device *pdev)
1152 {
1153         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1154         struct resource *res;
1155         u16 vdd = 0;
1156
1157         if (host) {
1158                 mmc_omap_fclk_state(host, ON);
1159                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1160                         /*
1161                          * Set the vdd back to 3V,
1162                          * applicable for dual volt support.
1163                          */
1164                         vdd = fls(host->mmc->ocr_avail) - 1;
1165                         if (omap_mmc_switch_opcond(host, vdd) != 0)
1166                                 host->mmc->ios.vdd = vdd;
1167                 }
1168         }
1169
1170         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1171         if (res)
1172                 release_mem_region(res->start, res->end - res->start + 1);
1173
1174         platform_set_drvdata(pdev, NULL);
1175         if (host) {
1176                 mmc_remove_host(host->mmc);
1177                 if (host->pdata->cleanup)
1178                         host->pdata->cleanup(&pdev->dev);
1179                 free_irq(host->irq, host);
1180                 if (mmc_slot(host).card_detect_irq)
1181                         free_irq(mmc_slot(host).card_detect_irq, host);
1182                 flush_scheduled_work();
1183
1184                 mmc_omap_fclk_state(host, OFF);
1185                 clk_disable(host->iclk);
1186                 clk_put(host->fclk);
1187                 clk_put(host->iclk);
1188                 if (host->dbclk_enabled) {
1189                         clk_disable(host->dbclk);
1190                         clk_put(host->dbclk);
1191                 }
1192
1193                 mmc_free_host(host->mmc);
1194                 iounmap(host->base);
1195         }
1196
1197         return 0;
1198 }
1199
1200 #ifdef CONFIG_PM
1201 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1202 {
1203         int ret = 0;
1204         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1205
1206         if (host && host->suspended)
1207                 return 0;
1208
1209         if (host) {
1210                 mmc_omap_fclk_state(host, ON);
1211
1212                 ret = mmc_suspend_host(host->mmc, state);
1213                 if (ret == 0) {
1214                         host->suspended = 1;
1215
1216                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1217                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1218
1219                         if (host->pdata->suspend) {
1220                                 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1221                                 if (ret)
1222                                         dev_dbg(mmc_dev(host->mmc),
1223                                                 "Unable to handle MMC board"
1224                                                 " level suspend\n");
1225                         }
1226
1227                         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1228                                 u32 hctl = OMAP_HSMMC_READ(host->base, HCTL) &
1229                                         SDVSCLR;
1230
1231                                 if (host->id == OMAP_MMC1_DEVID)
1232                                         hctl |= SDVS30;
1233                                 else
1234                                         hctl |= SDVS18;
1235
1236                                 OMAP_HSMMC_WRITE(host->base, HCTL, hctl);
1237                                 OMAP_HSMMC_WRITE(host->base, HCTL, hctl | SDBP);
1238                         }
1239
1240                         mmc_omap_fclk_state(host, OFF);
1241                         clk_disable(host->iclk);
1242                         clk_disable(host->dbclk);
1243                 }
1244
1245         }
1246         return ret;
1247 }
1248
1249 /* Routine to resume the MMC device */
1250 static int omap_mmc_resume(struct platform_device *pdev)
1251 {
1252         int ret = 0;
1253         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1254
1255         if (host && !host->suspended)
1256                 return 0;
1257
1258         if (host) {
1259                 if (mmc_omap_fclk_state(host, ON) != 0)
1260                         goto clk_en_err;
1261
1262                 ret = clk_enable(host->iclk);
1263                 if (ret) {
1264                         mmc_omap_fclk_state(host, OFF);
1265                         clk_put(host->fclk);
1266                         goto clk_en_err;
1267                 }
1268
1269                 if (clk_enable(host->dbclk) != 0)
1270                         dev_dbg(mmc_dev(host->mmc),
1271                                         "Enabling debounce clk failed\n");
1272
1273                 if (host->pdata->resume) {
1274                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1275                         if (ret)
1276                                 dev_dbg(mmc_dev(host->mmc),
1277                                         "Unmask interrupt failed\n");
1278                 }
1279
1280                 /* Notify the core to resume the host */
1281                 ret = mmc_resume_host(host->mmc);
1282                 if (ret == 0)
1283                         host->suspended = 0;
1284
1285                 mmc_omap_fclk_lazy_disable(host);
1286         }
1287
1288         return ret;
1289
1290 clk_en_err:
1291         dev_dbg(mmc_dev(host->mmc),
1292                 "Failed to enable MMC clocks during resume\n");
1293         return ret;
1294 }
1295
1296 #else
1297 #define omap_mmc_suspend        NULL
1298 #define omap_mmc_resume         NULL
1299 #endif
1300
1301 static struct platform_driver omap_mmc_driver = {
1302         .probe          = omap_mmc_probe,
1303         .remove         = omap_mmc_remove,
1304         .suspend        = omap_mmc_suspend,
1305         .resume         = omap_mmc_resume,
1306         .driver         = {
1307                 .name = DRIVER_NAME,
1308                 .owner = THIS_MODULE,
1309         },
1310 };
1311
1312 static int __init omap_mmc_init(void)
1313 {
1314         /* Register the MMC driver */
1315         return platform_driver_register(&omap_mmc_driver);
1316 }
1317
1318 static void __exit omap_mmc_cleanup(void)
1319 {
1320         /* Unregister MMC driver */
1321         platform_driver_unregister(&omap_mmc_driver);
1322 }
1323
1324 module_init(omap_mmc_init);
1325 module_exit(omap_mmc_cleanup);
1326
1327 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1328 MODULE_LICENSE("GPL");
1329 MODULE_ALIAS("platform:" DRIVER_NAME);
1330 MODULE_AUTHOR("Texas Instruments Inc");