drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <asm/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1 << 8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1 << 2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define CLKD_SHIFT              6
  68 #define DTO_MASK                0x000F0000
  69 #define DTO_SHIFT               16
  70 #define INT_EN_MASK             0x307F0033
  71 #define INIT_STREAM             (1 << 1)
  72 #define DP_SELECT               (1 << 21)
  73 #define DDIR                    (1 << 4)
  74 #define DMA_EN                  0x1
  75 #define MSBS                    (1 << 5)
  76 #define BCE                     (1 << 1)
  77 #define FOUR_BIT                (1 << 1)
  78 #define CC                      0x1
  79 #define TC                      0x02
  80 #define OD                      0x1
  81 #define ERR                     (1 << 15)
  82 #define CMD_TIMEOUT             (1 << 16)
  83 #define DATA_TIMEOUT            (1 << 20)
  84 #define CMD_CRC                 (1 << 17)
  85 #define DATA_CRC                (1 << 21)
  86 #define CARD_ERR                (1 << 28)
  87 #define STAT_CLEAR              0xFFFFFFFF
  88 #define INIT_STREAM_CMD         0x00000000
  89 #define DUAL_VOLT_OCR_BIT       7
  90 #define SRC                     (1 << 25)
  91 #define SRD                     (1 << 26)
  92
  93 /*
  94  * FIXME: Most likely all the data using these _DEVID defines should come
  95  * from the platform_data, or implemented in controller and slot specific
  96  * functions.
  97  */
  98 #define OMAP_MMC1_DEVID         0
  99 #define OMAP_MMC2_DEVID         1
 100
 101 #define OMAP_MMC_DATADIR_NONE   0
 102 #define OMAP_MMC_DATADIR_READ   1
 103 #define OMAP_MMC_DATADIR_WRITE  2
 104 #define MMC_TIMEOUT_MS          20
 105 #define OMAP_MMC_MASTER_CLOCK   96000000
 106 #define DRIVER_NAME             "mmci-omap-hs"
 107
 108 /*
 109  * One controller can have multiple slots, like on some omap boards using
 110  * omap.c controller driver. Luckily this is not currently done on any known
 111  * omap_hsmmc.c device.
 112  */
 113 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 114
 115 /*
 116  * MMC Host controller read/write API's
 117  */
 118 #define OMAP_HSMMC_READ(base, reg)      \
 119         __raw_readl((base) + OMAP_HSMMC_##reg)
 120
 121 #define OMAP_HSMMC_WRITE(base, reg, val) \
 122         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 123
 124 enum {OFF = 0, ON};
 125 #define IDLE_TIMEOUT (jiffies_to_msecs(10))
 126
 127 struct mmc_omap_host {
 128         struct  device          *dev;
 129         struct  mmc_host        *mmc;
 130         struct  mmc_request     *mrq;
 131         struct  mmc_command     *cmd;
 132         struct  mmc_data        *data;
 133         struct  clk             *fclk;
 134         struct  clk             *iclk;
 135         struct  clk             *dbclk;
 136         struct  semaphore       sem;
 137         struct  work_struct     mmc_carddetect_work;
 138         void    __iomem         *base;
 139         resource_size_t         mapbase;
 140         unsigned int            id;
 141         unsigned int            dma_len;
 142         unsigned int            dma_dir;
 143         unsigned char           bus_mode;
 144         unsigned char           datadir;
 145         u32                     *buffer;
 146         u32                     bytesleft;
 147         int                     suspended;
 148         int                     irq;
 149         int                     carddetect;
 150         int                     use_dma, dma_ch;
 151         int                     initstr;
 152         int                     slot_id;
 153         int                     dbclk_enabled;
 154
 155         struct timer_list       idle_timer;
 156         spinlock_t              clk_lock;     /* for changing enabled state */
 157         unsigned int            fclk_enabled:1;
 158
 159         struct  omap_mmc_platform_data  *pdata;
 160 };
 161
 162 static int mmc_omap_fclk_state(struct mmc_omap_host *host, unsigned int state)
 163 {
 164         unsigned long flags;
 165         int ret = 0;
 166
 167         spin_lock_irqsave(&host->clk_lock, flags);
 168         del_timer(&host->idle_timer);
 169         if (host->fclk_enabled != state) {
 170                 if (state == ON) {
 171                         ret = clk_enable(host->fclk);
 172                         if (ret != 0)
 173                                 goto err_out;
 174
 175                         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
 176                 } else {
 177                         clk_disable(host->fclk);
 178                         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
 179                 }
 180                 host->fclk_enabled = state;
 181         }
 182
 183 err_out:
 184         spin_unlock_irqrestore(&host->clk_lock, flags);
 185         return ret;
 186 }
 187
 188 static void mmc_omap_idle_timer(unsigned long data)
 189 {
 190         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 191
 192         mmc_omap_fclk_state(host, OFF);
 193 }
 194
 195 static void mmc_omap_fclk_lazy_disable(struct mmc_omap_host *host)
 196 {
 197         mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
 198 }
 199
 200 /*
 201  * Stop clock to the card
 202  */
 203 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 204 {
 205         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 206                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 207         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 208                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 209 }
 210
 211 /*
 212  * Send init stream sequence to card
 213  * before sending IDLE command
 214  */
 215 static void send_init_stream(struct mmc_omap_host *host)
 216 {
 217         int reg = 0;
 218         unsigned long timeout;
 219
 220         disable_irq(host->irq);
 221         OMAP_HSMMC_WRITE(host->base, CON,
 222                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 223         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 224
 225         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 226         while ((reg != CC) && time_before(jiffies, timeout))
 227                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 228
 229         OMAP_HSMMC_WRITE(host->base, CON,
 230                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 231         enable_irq(host->irq);
 232 }
 233
 234 static inline
 235 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 236 {
 237         if (host->pdata->slots[host->slot_id].get_cover_state)
 238                 return host->pdata->slots[host->slot_id].get_cover_state(host->dev, host->slot_id);
 239         return 1;
 240 }
 241
 242 static ssize_t
 243 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 244                            char *buf)
 245 {
 246         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 247         struct mmc_omap_host *host = mmc_priv(mmc);
 248
 249         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 250                        "open");
 251 }
 252
 253 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 254
 255 static ssize_t
 256 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 257                         char *buf)
 258 {
 259         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 260         struct mmc_omap_host *host = mmc_priv(mmc);
 261         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 262
 263         return sprintf(buf, "slot:%s\n", slot.name);
 264 }
 265
 266 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 267
 268 /*
 269  * Configure the response type and send the cmd.
 270  */
 271 static void
 272 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 273         struct mmc_data *data)
 274 {
 275         int cmdreg = 0, resptype = 0, cmdtype = 0;
 276
 277         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 278                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 279         host->cmd = cmd;
 280
 281         /*
 282          * Clear status bits and enable interrupts
 283          */
 284         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 285         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 286         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 287
 288         if (cmd->flags & MMC_RSP_PRESENT) {
 289                 if (cmd->flags & MMC_RSP_136)
 290                         resptype = 1;
 291                 else
 292                         resptype = 2;
 293         }
 294
 295         /*
 296          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 297          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 298          * a val of 0x3, rest 0x0.
 299          */
 300         if (cmd == host->mrq->stop)
 301                 cmdtype = 0x3;
 302
 303         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 304
 305         if (data) {
 306                 cmdreg |= DP_SELECT | MSBS | BCE;
 307                 if (data->flags & MMC_DATA_READ)
 308                         cmdreg |= DDIR;
 309                 else
 310                         cmdreg &= ~(DDIR);
 311         }
 312
 313         if (host->use_dma)
 314                 cmdreg |= DMA_EN;
 315
 316         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 317         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 318 }
 319
 320 /*
 321  * Notify the transfer complete to MMC core
 322  */
 323 static void
 324 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 325 {
 326         host->data = NULL;
 327
 328         if (host->use_dma && host->dma_ch != -1)
 329                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 330                         host->dma_dir);
 331
 332         host->datadir = OMAP_MMC_DATADIR_NONE;
 333
 334         if (!data->error)
 335                 data->bytes_xfered += data->blocks * (data->blksz);
 336         else
 337                 data->bytes_xfered = 0;
 338
 339         if (!data->stop) {
 340                 host->mrq = NULL;
 341                 mmc_omap_fclk_lazy_disable(host);
 342                 mmc_request_done(host->mmc, data->mrq);
 343                 return;
 344         }
 345         mmc_omap_start_command(host, data->stop, NULL);
 346 }
 347
 348 /*
 349  * Notify the core about command completion
 350  */
 351 static void
 352 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 353 {
 354         host->cmd = NULL;
 355
 356         if (cmd->flags & MMC_RSP_PRESENT) {
 357                 if (cmd->flags & MMC_RSP_136) {
 358                         /* response type 2 */
 359                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 360                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 361                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 362                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 363                 } else {
 364                         /* response types 1, 1b, 3, 4, 5, 6 */
 365                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 366                 }
 367         }
 368         if (host->data == NULL || cmd->error) {
 369                 host->mrq = NULL;
 370                 mmc_omap_fclk_lazy_disable(host);
 371                 mmc_request_done(host->mmc, cmd->mrq);
 372         }
 373 }
 374
 375 /*
 376  * DMA clean up for command errors
 377  */
 378 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 379 {
 380         host->data->error = -ETIMEDOUT;
 381
 382         if (host->use_dma && host->dma_ch != -1) {
 383                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 384                         host->dma_dir);
 385                 omap_free_dma(host->dma_ch);
 386                 host->dma_ch = -1;
 387                 up(&host->sem);
 388         }
 389         host->data = NULL;
 390         host->datadir = OMAP_MMC_DATADIR_NONE;
 391 }
 392
 393 /*
 394  * Readable error output
 395  */
 396 #ifdef CONFIG_MMC_DEBUG
 397 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 398 {
 399         /* --- means reserved bit without definition at documentation */
 400         static const char *mmc_omap_status_bits[] = {
 401                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 402                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 403                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 404                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 405         };
 406         int i;
 407
 408         dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
 409
 410         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 411                 if (status & (1 << i))
 412                         /*
 413                          * KERN_* facility is not used here because this should
 414                          * print a single line.
 415                          */
 416                         printk(" %s", mmc_omap_status_bits[i]);
 417
 418         printk("\n");
 419
 420 }
 421 #endif  /* CONFIG_MMC_DEBUG */
 422
 423
 424 /*
 425  * MMC controller IRQ handler
 426  */
 427 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 428 {
 429         struct mmc_omap_host *host = dev_id;
 430         struct mmc_data *data;
 431         int end_cmd = 0, end_trans = 0, status;
 432
 433         if (host->cmd == NULL && host->data == NULL) {
 434                 OMAP_HSMMC_WRITE(host->base, STAT,
 435                         OMAP_HSMMC_READ(host->base, STAT));
 436                 return IRQ_HANDLED;
 437         }
 438
 439         data = host->data;
 440         status = OMAP_HSMMC_READ(host->base, STAT);
 441         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 442
 443         if (status & ERR) {
 444 #ifdef CONFIG_MMC_DEBUG
 445                 mmc_omap_report_irq(host, status);
 446 #endif
 447                 if ((status & CMD_TIMEOUT) ||
 448                         (status & CMD_CRC)) {
 449                         if (host->cmd) {
 450                                 if (status & CMD_TIMEOUT) {
 451                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 452                                                 OMAP_HSMMC_READ(host->base,
 453                                                                 SYSCTL) | SRC);
 454                                         while (OMAP_HSMMC_READ(host->base,
 455                                                                 SYSCTL) & SRC) ;
 456                                         host->cmd->error = -ETIMEDOUT;
 457                                 } else {
 458                                         host->cmd->error = -EILSEQ;
 459                                 }
 460                                 end_cmd = 1;
 461                         }
 462                         if (host->data)
 463                                 mmc_dma_cleanup(host);
 464                 }
 465                 if ((status & DATA_TIMEOUT) ||
 466                         (status & DATA_CRC)) {
 467                         if (host->data) {
 468                                 if (status & DATA_TIMEOUT)
 469                                         mmc_dma_cleanup(host);
 470                                 else
 471                                         host->data->error = -EILSEQ;
 472                                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 473                                         OMAP_HSMMC_READ(host->base,
 474                                                         SYSCTL) | SRD);
 475                                 while (OMAP_HSMMC_READ(host->base,
 476                                                         SYSCTL) & SRD) ;
 477                                 end_trans = 1;
 478                         }
 479                 }
 480                 if (status & CARD_ERR) {
 481                         dev_dbg(mmc_dev(host->mmc),
 482                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 483                         if (host->cmd)
 484                                 end_cmd = 1;
 485                         if (host->data)
 486                                 end_trans = 1;
 487                 }
 488         }
 489
 490         OMAP_HSMMC_WRITE(host->base, STAT, status);
 491
 492         if (end_cmd || (status & CC))
 493                 mmc_omap_cmd_done(host, host->cmd);
 494         if (end_trans || (status & TC))
 495                 mmc_omap_xfer_done(host, data);
 496
 497         return IRQ_HANDLED;
 498 }
 499
 500 /*
 501  * Switch MMC operating voltage
 502  */
 503 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 504 {
 505         u32 reg_val = 0;
 506         int ret;
 507
 508         /* Disable the clocks */
 509         mmc_omap_fclk_state(host, OFF);
 510         clk_disable(host->iclk);
 511         clk_disable(host->dbclk);
 512
 513         /* Turn the power off */
 514         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 515         if (ret != 0)
 516                 goto err;
 517
 518         /* Turn the power ON with given VDD 1.8 or 3.0v */
 519         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 520         if (ret != 0)
 521                 goto err;
 522
 523         mmc_omap_fclk_state(host, ON);
 524         clk_enable(host->iclk);
 525         clk_enable(host->dbclk);
 526
 527         OMAP_HSMMC_WRITE(host->base, HCTL,
 528                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 529         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 530         /*
 531          * If a MMC dual voltage card is detected, the set_ios fn calls
 532          * this fn with VDD bit set for 1.8V. Upon card removal from the
 533          * slot, mmc_omap_detect fn sets the VDD back to 3V.
 534          *
 535          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 536          * set in HCTL.
 537          */
 538         if (host->id == OMAP_MMC1_DEVID) {
 539                 if (((1 << vdd) == MMC_VDD_32_33) ||
 540                     ((1 << vdd) == MMC_VDD_33_34))
 541                         reg_val |= SDVS30;
 542                 else if ((1 << vdd) == MMC_VDD_165_195)
 543                         reg_val |= SDVS18;
 544         } else
 545                 reg_val |= SDVS18;
 546
 547         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 548
 549         OMAP_HSMMC_WRITE(host->base, HCTL,
 550                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 551
 552         return 0;
 553 err:
 554         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 555         return ret;
 556 }
 557
 558 /*
 559  * Work Item to notify the core about card insertion/removal
 560  */
 561 static void mmc_omap_detect(struct work_struct *work)
 562 {
 563         u16 vdd = 0;
 564         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 565                                                 mmc_carddetect_work);
 566
 567         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 568         mmc_omap_fclk_state(host, ON);
 569         if (host->carddetect) {
 570                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 571                         /*
 572                          * Set the VDD back to 3V when the card is removed
 573                          * before the set_ios fn turns off the power.
 574                          */
 575                         vdd = fls(host->mmc->ocr_avail) - 1;
 576                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 577                                 host->mmc->ios.vdd = vdd;
 578                 }
 579                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 580         } else {
 581                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 582                         OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
 583                 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
 584                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 585         }
 586         mmc_omap_fclk_lazy_disable(host);
 587 }
 588
 589 /*
 590  * ISR for handling card insertion and removal
 591  */
 592 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 593 {
 594         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 595
 596         host->carddetect = mmc_slot(host).card_detect(irq);
 597         schedule_work(&host->mmc_carddetect_work);
 598
 599         return IRQ_HANDLED;
 600 }
 601
 602 /*
 603  * DMA call back function
 604  */
 605 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 606 {
 607         struct mmc_omap_host *host = data;
 608
 609         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 610                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 611
 612         if (host->dma_ch < 0)
 613                 return;
 614
 615         omap_free_dma(host->dma_ch);
 616         host->dma_ch = -1;
 617         /*
 618          * DMA Callback: run in interrupt context.
 619          * mutex_unlock will through a kernel warning if used.
 620          */
 621         up(&host->sem);
 622 }
 623
 624 /*
 625  * Configure dma src and destination parameters
 626  */
 627 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 628                                 struct mmc_data *data)
 629 {
 630         if (sync_dir == 0) {
 631                 omap_set_dma_dest_params(host->dma_ch, 0,
 632                         OMAP_DMA_AMODE_CONSTANT,
 633                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 634                 omap_set_dma_src_params(host->dma_ch, 0,
 635                         OMAP_DMA_AMODE_POST_INC,
 636                         sg_dma_address(&data->sg[0]), 0, 0);
 637         } else {
 638                 omap_set_dma_src_params(host->dma_ch, 0,
 639                         OMAP_DMA_AMODE_CONSTANT,
 640                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 641                 omap_set_dma_dest_params(host->dma_ch, 0,
 642                         OMAP_DMA_AMODE_POST_INC,
 643                         sg_dma_address(&data->sg[0]), 0, 0);
 644         }
 645         return 0;
 646 }
 647 /*
 648  * Routine to configure and start DMA for the MMC card
 649  */
 650 static int
 651 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 652 {
 653         int sync_dev, sync_dir = 0;
 654         int dma_ch = 0, ret = 0, err = 1;
 655         struct mmc_data *data = req->data;
 656
 657         /*
 658          * If for some reason the DMA transfer is still active,
 659          * we wait for timeout period and free the dma
 660          */
 661         if (host->dma_ch != -1) {
 662                 set_current_state(TASK_UNINTERRUPTIBLE);
 663                 schedule_timeout(100);
 664                 if (down_trylock(&host->sem)) {
 665                         omap_free_dma(host->dma_ch);
 666                         host->dma_ch = -1;
 667                         up(&host->sem);
 668                         return err;
 669                 }
 670         } else {
 671                 if (down_trylock(&host->sem))
 672                         return err;
 673         }
 674
 675         if (!(data->flags & MMC_DATA_WRITE)) {
 676                 host->dma_dir = DMA_FROM_DEVICE;
 677                 if (host->id == OMAP_MMC1_DEVID)
 678                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 679                 else
 680                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 681         } else {
 682                 host->dma_dir = DMA_TO_DEVICE;
 683                 if (host->id == OMAP_MMC1_DEVID)
 684                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 685                 else
 686                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 687         }
 688
 689         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 690                         host, &dma_ch);
 691         if (ret != 0) {
 692                 dev_dbg(mmc_dev(host->mmc),
 693                         "%s: omap_request_dma() failed with %d\n",
 694                         mmc_hostname(host->mmc), ret);
 695                 return ret;
 696         }
 697
 698         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 699                         data->sg_len, host->dma_dir);
 700         host->dma_ch = dma_ch;
 701
 702         if (!(data->flags & MMC_DATA_WRITE))
 703                 mmc_omap_config_dma_param(1, host, data);
 704         else
 705                 mmc_omap_config_dma_param(0, host, data);
 706
 707         if ((data->blksz % 4) == 0)
 708                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 709                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 710                         sync_dev, sync_dir);
 711         else
 712                 /* REVISIT: The MMC buffer increments only when MSB is written.
 713                  * Return error for blksz which is non multiple of four.
 714                  */
 715                 return -EINVAL;
 716
 717         omap_start_dma(dma_ch);
 718         return 0;
 719 }
 720
 721 static void set_data_timeout(struct mmc_omap_host *host,
 722                              struct mmc_request *req)
 723 {
 724         unsigned int timeout, cycle_ns;
 725         uint32_t reg, clkd, dto = 0;
 726
 727         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 728         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 729         if (clkd == 0)
 730                 clkd = 1;
 731
 732         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 733         timeout = req->data->timeout_ns / cycle_ns;
 734         timeout += req->data->timeout_clks;
 735         if (timeout) {
 736                 while ((timeout & 0x80000000) == 0) {
 737                         dto += 1;
 738                         timeout <<= 1;
 739                 }
 740                 dto = 31 - dto;
 741                 timeout <<= 1;
 742                 if (timeout && dto)
 743                         dto += 1;
 744                 if (dto >= 13)
 745                         dto -= 13;
 746                 else
 747                         dto = 0;
 748                 if (dto > 14)
 749                         dto = 14;
 750         }
 751
 752         reg &= ~DTO_MASK;
 753         reg |= dto << DTO_SHIFT;
 754         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 755 }
 756
 757 /*
 758  * Configure block length for MMC/SD cards and initiate the transfer.
 759  */
 760 static int
 761 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 762 {
 763         int ret;
 764         host->data = req->data;
 765
 766         if (req->data == NULL) {
 767                 host->datadir = OMAP_MMC_DATADIR_NONE;
 768                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 769                 return 0;
 770         }
 771
 772         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 773                                         | (req->data->blocks << 16));
 774         set_data_timeout(host, req);
 775
 776         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 777                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 778
 779         if (host->use_dma) {
 780                 ret = mmc_omap_start_dma_transfer(host, req);
 781                 if (ret != 0) {
 782                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 783                         return ret;
 784                 }
 785         }
 786         return 0;
 787 }
 788
 789 /*
 790  * Request function. for read/write operation
 791  */
 792 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 793 {
 794         struct mmc_omap_host *host = mmc_priv(mmc);
 795
 796         WARN_ON(host->mrq != NULL);
 797         host->mrq = req;
 798         mmc_omap_fclk_state(host, ON);
 799         mmc_omap_prepare_data(host, req);
 800         mmc_omap_start_command(host, req->cmd, req->data);
 801 }
 802
 803 /* Routine to configure clock values. Exposed API to core */
 804 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 805 {
 806         struct mmc_omap_host *host = mmc_priv(mmc);
 807         u16 dsor = 0;
 808         unsigned long regval;
 809         unsigned long timeout;
 810
 811         mmc_omap_fclk_state(host, ON);
 812
 813         switch (ios->power_mode) {
 814         case MMC_POWER_OFF:
 815                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 816                 break;
 817         case MMC_POWER_UP:
 818                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 819                 break;
 820         }
 821
 822         switch (mmc->ios.bus_width) {
 823         case MMC_BUS_WIDTH_4:
 824                 OMAP_HSMMC_WRITE(host->base, HCTL,
 825                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 826                 break;
 827         case MMC_BUS_WIDTH_1:
 828                 OMAP_HSMMC_WRITE(host->base, HCTL,
 829                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 830                 break;
 831         }
 832
 833         if (host->id == OMAP_MMC1_DEVID) {
 834                 /* Only MMC1 can operate at 3V/1.8V */
 835                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 836                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 837                                 /*
 838                                  * The mmc_select_voltage fn of the core does
 839                                  * not seem to set the power_mode to
 840                                  * MMC_POWER_UP upon recalculating the voltage.
 841                                  * vdd 1.8v.
 842                                  */
 843                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 844                                         dev_dbg(mmc_dev(host->mmc),
 845                                                 "Switch operation failed\n");
 846                 }
 847         }
 848
 849         if (ios->clock) {
 850                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 851                 if (dsor < 1)
 852                         dsor = 1;
 853
 854                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 855                         dsor++;
 856
 857                 if (dsor > 250)
 858                         dsor = 250;
 859         }
 860         omap_mmc_stop_clock(host);
 861         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 862         regval = regval & ~(CLKD_MASK);
 863         regval = regval | (dsor << 6) | (DTO << 16);
 864         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 865         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 866                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 867
 868         /* Wait till the ICS bit is set */
 869         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 870         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 871                 && time_before(jiffies, timeout))
 872                 msleep(1);
 873
 874         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 875                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 876
 877         if (ios->power_mode == MMC_POWER_ON)
 878                 send_init_stream(host);
 879
 880         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 881                 OMAP_HSMMC_WRITE(host->base, CON,
 882                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 883
 884         mmc_omap_fclk_lazy_disable(host);
 885 }
 886
 887 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 888 {
 889         struct mmc_omap_host *host = mmc_priv(mmc);
 890         struct omap_mmc_platform_data *pdata = host->pdata;
 891
 892         if (!pdata->slots[0].card_detect)
 893                 return -ENOSYS;
 894         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 895 }
 896
 897 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 898 {
 899         struct mmc_omap_host *host = mmc_priv(mmc);
 900         struct omap_mmc_platform_data *pdata = host->pdata;
 901
 902         if (!pdata->slots[0].get_ro)
 903                 return -ENOSYS;
 904         return pdata->slots[0].get_ro(host->dev, 0);
 905 }
 906
 907 static struct mmc_host_ops mmc_omap_ops = {
 908         .request = omap_mmc_request,
 909         .set_ios = omap_mmc_set_ios,
 910         .get_cd = omap_hsmmc_get_cd,
 911         .get_ro = omap_hsmmc_get_ro,
 912         /* NYET -- enable_sdio_irq */
 913 };
 914
 915 static int __init omap_mmc_probe(struct platform_device *pdev)
 916 {
 917         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 918         struct mmc_host *mmc;
 919         struct mmc_omap_host *host = NULL;
 920         struct resource *res;
 921         int ret = 0, irq, reg;
 922         u32 hctl, capa;
 923
 924         if (pdata == NULL) {
 925                 dev_err(&pdev->dev, "Platform Data is missing\n");
 926                 return -ENXIO;
 927         }
 928
 929         if (pdata->nr_slots == 0) {
 930                 dev_err(&pdev->dev, "No Slots\n");
 931                 return -ENXIO;
 932         }
 933
 934         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 935         irq = platform_get_irq(pdev, 0);
 936         if (res == NULL || irq < 0)
 937                 return -ENXIO;
 938
 939         res = request_mem_region(res->start, res->end - res->start + 1,
 940                                                         pdev->name);
 941         if (res == NULL)
 942                 return -EBUSY;
 943
 944         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 945         if (!mmc) {
 946                 ret = -ENOMEM;
 947                 goto err;
 948         }
 949
 950         host            = mmc_priv(mmc);
 951         host->mmc       = mmc;
 952         host->pdata     = pdata;
 953         host->dev       = &pdev->dev;
 954         host->use_dma   = 1;
 955         host->dev->dma_mask = &pdata->dma_mask;
 956         host->dma_ch    = -1;
 957         host->irq       = irq;
 958         host->id        = pdev->id;
 959         host->slot_id   = 0;
 960         host->mapbase   = res->start;
 961         host->base      = ioremap(host->mapbase, SZ_4K);
 962
 963         platform_set_drvdata(pdev, host);
 964         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 965
 966         mmc->ops        = &mmc_omap_ops;
 967         mmc->f_min      = 400000;
 968         mmc->f_max      = 52000000;
 969
 970         sema_init(&host->sem, 1);
 971
 972         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 973         if (IS_ERR(host->iclk)) {
 974                 ret = PTR_ERR(host->iclk);
 975                 host->iclk = NULL;
 976                 goto err1;
 977         }
 978         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 979         if (IS_ERR(host->fclk)) {
 980                 ret = PTR_ERR(host->fclk);
 981                 host->fclk = NULL;
 982                 clk_put(host->iclk);
 983                 goto err1;
 984         }
 985
 986         spin_lock_init(&host->clk_lock);
 987         setup_timer(&host->idle_timer, mmc_omap_idle_timer,
 988                     (unsigned long) host);
 989
 990         if (mmc_omap_fclk_state(host, ON) != 0) {
 991                 clk_put(host->iclk);
 992                 clk_put(host->fclk);
 993                 goto err1;
 994         }
 995         if (clk_enable(host->iclk) != 0) {
 996                 mmc_omap_fclk_state(host, OFF);
 997                 clk_put(host->iclk);
 998                 clk_put(host->fclk);
 999                 goto err1;
1000         }
1001
1002         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1003         /*
1004          * MMC can still work without debounce clock.
1005          */
1006         if (IS_ERR(host->dbclk))
1007                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1008         else
1009                 if (clk_enable(host->dbclk) != 0)
1010                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1011                                                         " clk failed\n");
1012                 else
1013                         host->dbclk_enabled = 1;
1014
1015 #ifdef CONFIG_MMC_BLOCK_BOUNCE
1016         mmc->max_phys_segs = 1;
1017         mmc->max_hw_segs = 1;
1018 #endif
1019         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1020         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1021         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1022         mmc->max_seg_size = mmc->max_req_size;
1023
1024         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1025         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1026
1027         if (pdata->slots[host->slot_id].wires >= 4)
1028                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1029
1030         /* Only MMC1 supports 3.0V */
1031         if (host->id == OMAP_MMC1_DEVID) {
1032                 hctl = SDVS30;
1033                 capa = VS30 | VS18;
1034         } else {
1035                 hctl = SDVS18;
1036                 capa = VS18;
1037         }
1038
1039         OMAP_HSMMC_WRITE(host->base, HCTL,
1040                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
1041
1042         OMAP_HSMMC_WRITE(host->base, CAPA,
1043                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
1044
1045         /* Set the controller to AUTO IDLE mode */
1046         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
1047                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
1048
1049         /* Set SD bus power bit */
1050         OMAP_HSMMC_WRITE(host->base, HCTL,
1051                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1052
1053         /* Request IRQ for MMC operations */
1054         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1055                         mmc_hostname(mmc), host);
1056         if (ret) {
1057                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1058                 goto err_irq;
1059         }
1060
1061         if (pdata->init != NULL) {
1062                 if (pdata->init(&pdev->dev) != 0) {
1063                         dev_dbg(mmc_dev(host->mmc),
1064                                 "Unable to configure MMC IRQs\n");
1065                         goto err_irq_cd_init;
1066                 }
1067         }
1068
1069         /* Request IRQ for card detect */
1070         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1071                 ret = request_irq(mmc_slot(host).card_detect_irq,
1072                                   omap_mmc_cd_handler,
1073                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1074                                           | IRQF_DISABLED,
1075                                   mmc_hostname(mmc), host);
1076                 if (ret) {
1077                         dev_dbg(mmc_dev(host->mmc),
1078                                 "Unable to grab MMC CD IRQ\n");
1079                         goto err_irq_cd;
1080                 }
1081         }
1082
1083         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1084         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1085
1086         mmc_add_host(mmc);
1087
1088         if (host->pdata->slots[host->slot_id].name != NULL) {
1089                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1090                 if (ret < 0)
1091                         goto err_slot_name;
1092         }
1093         if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1094                         host->pdata->slots[host->slot_id].get_cover_state) {
1095                 ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch);
1096                 if (ret < 0)
1097                         goto err_cover_switch;
1098         }
1099         mmc_omap_fclk_lazy_disable(host);
1100
1101         return 0;
1102
1103 err_cover_switch:
1104         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1105 err_slot_name:
1106         mmc_remove_host(mmc);
1107 err_irq_cd:
1108         free_irq(mmc_slot(host).card_detect_irq, host);
1109 err_irq_cd_init:
1110         free_irq(host->irq, host);
1111 err_irq:
1112         mmc_omap_fclk_state(host, OFF);
1113         clk_disable(host->iclk);
1114         clk_put(host->fclk);
1115         clk_put(host->iclk);
1116         if (host->dbclk_enabled) {
1117                 clk_disable(host->dbclk);
1118                 clk_put(host->dbclk);
1119         }
1120
1121 err1:
1122         iounmap(host->base);
1123 err:
1124         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1125         release_mem_region(res->start, res->end - res->start + 1);
1126         if (host)
1127                 mmc_free_host(mmc);
1128         return ret;
1129 }
1130
1131 static int omap_mmc_remove(struct platform_device *pdev)
1132 {
1133         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1134         struct resource *res;
1135
1136         if (host) {
1137                 mmc_remove_host(host->mmc);
1138                 if (host->pdata->cleanup)
1139                         host->pdata->cleanup(&pdev->dev);
1140                 free_irq(host->irq, host);
1141                 if (mmc_slot(host).card_detect_irq)
1142                         free_irq(mmc_slot(host).card_detect_irq, host);
1143                 flush_scheduled_work();
1144
1145                 mmc_omap_fclk_state(host, OFF);
1146                 clk_disable(host->iclk);
1147                 clk_put(host->fclk);
1148                 clk_put(host->iclk);
1149                 if (host->dbclk_enabled) {
1150                         clk_disable(host->dbclk);
1151                         clk_put(host->dbclk);
1152                 }
1153
1154                 mmc_free_host(host->mmc);
1155                 iounmap(host->base);
1156         }
1157
1158         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1159         if (res)
1160                 release_mem_region(res->start, res->end - res->start + 1);
1161         platform_set_drvdata(pdev, NULL);
1162
1163         return 0;
1164 }
1165
1166 #ifdef CONFIG_PM
1167 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1168 {
1169         int ret = 0;
1170         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1171
1172         if (host && host->suspended)
1173                 return 0;
1174
1175         if (host) {
1176                 ret = mmc_suspend_host(host->mmc, state);
1177                 if (ret == 0) {
1178                         host->suspended = 1;
1179
1180                         mmc_omap_fclk_state(host, ON);
1181                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1182                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1183
1184                         if (host->pdata->suspend) {
1185                                 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1186                                 if (ret)
1187                                         dev_dbg(mmc_dev(host->mmc),
1188                                                 "Unable to handle MMC board"
1189                                                 " level suspend\n");
1190                         }
1191
1192                         OMAP_HSMMC_WRITE(host->base, HCTL,
1193                                          OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1194                         mmc_omap_fclk_state(host, OFF);
1195                         clk_disable(host->iclk);
1196                         clk_disable(host->dbclk);
1197                 }
1198
1199         }
1200         return ret;
1201 }
1202
1203 /* Routine to resume the MMC device */
1204 static int omap_mmc_resume(struct platform_device *pdev)
1205 {
1206         int ret = 0;
1207         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1208
1209         if (host && !host->suspended)
1210                 return 0;
1211
1212         if (host) {
1213                 int i;
1214                 if (mmc_omap_fclk_state(host, ON) != 0)
1215                         goto clk_en_err;
1216
1217                 ret = clk_enable(host->iclk);
1218                 if (ret) {
1219                         mmc_omap_fclk_state(host, OFF);
1220                         clk_put(host->fclk);
1221                         goto clk_en_err;
1222                 }
1223
1224                 if (clk_enable(host->dbclk) != 0)
1225                         dev_dbg(mmc_dev(host->mmc),
1226                                         "Enabling debounce clk failed\n");
1227
1228                 OMAP_HSMMC_WRITE(host->base, HCTL,
1229                                  OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1230
1231                 for (i = 0; i < 100; i++)
1232                         if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1233                                 break;
1234
1235                 if (host->pdata->resume) {
1236                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1237                         if (ret)
1238                                 dev_dbg(mmc_dev(host->mmc),
1239                                         "Unmask interrupt failed\n");
1240                 }
1241
1242                 /* Notify the core to resume the host */
1243                 ret = mmc_resume_host(host->mmc);
1244                 if (ret == 0)
1245                         host->suspended = 0;
1246
1247                 mmc_omap_fclk_lazy_disable(host);
1248         }
1249
1250         return ret;
1251
1252 clk_en_err:
1253         dev_dbg(mmc_dev(host->mmc),
1254                 "Failed to enable MMC clocks during resume\n");
1255         return ret;
1256 }
1257
1258 #else
1259 #define omap_mmc_suspend        NULL
1260 #define omap_mmc_resume         NULL
1261 #endif
1262
1263 static struct platform_driver omap_mmc_driver = {
1264         .probe          = omap_mmc_probe,
1265         .remove         = omap_mmc_remove,
1266         .suspend        = omap_mmc_suspend,
1267         .resume         = omap_mmc_resume,
1268         .driver         = {
1269                 .name = DRIVER_NAME,
1270                 .owner = THIS_MODULE,
1271         },
1272 };
1273
1274 static int __init omap_mmc_init(void)
1275 {
1276         /* Register the MMC driver */
1277         return platform_driver_register(&omap_mmc_driver);
1278 }
1279
1280 static void __exit omap_mmc_cleanup(void)
1281 {
1282         /* Unregister MMC driver */
1283         platform_driver_unregister(&omap_mmc_driver);
1284 }
1285
1286 module_init(omap_mmc_init);
1287 module_exit(omap_mmc_cleanup);
1288
1289 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1290 MODULE_LICENSE("GPL");
1291 MODULE_ALIAS("platform:" DRIVER_NAME);
1292 MODULE_AUTHOR("Texas Instruments Inc");