2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_device.h>
24 #include <linux/workqueue.h>
25 #include <linux/timer.h>
26 #include <linux/clk.h>
27 #include <linux/mmc/host.h>
29 #include <asm/semaphore.h>
31 #include <asm/hardware.h>
32 #include <asm/arch/board.h>
33 #include <asm/arch/mmc.h>
34 #include <asm/arch/cpu.h>
36 /* OMAP HSMMC Host Controller Registers */
37 #define OMAP_HSMMC_SYSCONFIG 0x0010
38 #define OMAP_HSMMC_CON 0x002C
39 #define OMAP_HSMMC_BLK 0x0104
40 #define OMAP_HSMMC_ARG 0x0108
41 #define OMAP_HSMMC_CMD 0x010C
42 #define OMAP_HSMMC_RSP10 0x0110
43 #define OMAP_HSMMC_RSP32 0x0114
44 #define OMAP_HSMMC_RSP54 0x0118
45 #define OMAP_HSMMC_RSP76 0x011C
46 #define OMAP_HSMMC_DATA 0x0120
47 #define OMAP_HSMMC_HCTL 0x0128
48 #define OMAP_HSMMC_SYSCTL 0x012C
49 #define OMAP_HSMMC_STAT 0x0130
50 #define OMAP_HSMMC_IE 0x0134
51 #define OMAP_HSMMC_ISE 0x0138
52 #define OMAP_HSMMC_CAPA 0x0140
56 #define SDVS18 (0x5<<9)
57 #define SDVS30 (0x6<<9)
58 #define SDVSCLR 0xFFFFF1FF
59 #define SDVSDET 0x00000400
66 #define CLKD_MASK 0x0000FFC0
67 #define INT_EN_MASK 0x307F0033
68 #define INIT_STREAM (1<<1)
69 #define DP_SELECT (1<<21)
74 #define FOUR_BIT 1 << 1
79 #define CMD_TIMEOUT (1 << 16)
80 #define DATA_TIMEOUT (1 << 20)
81 #define CMD_CRC (1 << 17)
82 #define DATA_CRC (1 << 21)
83 #define CARD_ERR (1 << 28)
84 #define STAT_CLEAR 0xFFFFFFFF
85 #define INIT_STREAM_CMD 0x00000000
86 #define DUAL_VOLT_OCR_BIT 7
88 #define OMAP_MMC1_DEVID 1
89 #define OMAP_MMC2_DEVID 2
90 #define OMAP_MMC_DATADIR_NONE 0
91 #define OMAP_MMC_DATADIR_READ 1
92 #define OMAP_MMC_DATADIR_WRITE 2
93 #define MMC_TIMEOUT_MS 20
94 #define OMAP_MMC_MASTER_CLOCK 96000000
95 #define DRIVER_NAME "mmci-omap"
97 * slot_id is device id - 1, device id is a static value
98 * of 1 to represent device 1 etc..
100 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
103 * MMC Host controller read/write API's
105 #define OMAP_HSMMC_READ(base, reg) \
106 __raw_readl((base) + OMAP_HSMMC_##reg)
108 #define OMAP_HSMMC_WRITE(base, reg, val) \
109 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
111 struct mmc_omap_host {
113 struct mmc_host *mmc;
114 struct mmc_request *mrq;
115 struct mmc_command *cmd;
116 struct mmc_data *data;
120 struct semaphore sem;
121 struct work_struct mmc_carddetect_work;
123 resource_size_t mapbase;
125 unsigned int dma_len;
126 unsigned int dma_dir;
127 unsigned char bus_mode;
128 unsigned char datadir;
138 struct omap_mmc_platform_data *pdata;
142 * Stop clock to the card
144 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
146 OMAP_HSMMC_WRITE(host->base, SYSCTL,
147 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
148 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
149 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped");
153 * Send init stream sequence to card
154 * before sending IDLE command
156 static void send_init_stream(struct mmc_omap_host *host)
159 unsigned long timeout;
161 disable_irq(host->irq);
162 OMAP_HSMMC_WRITE(host->base, CON,
163 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
164 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
166 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
167 while ((reg != CC) && time_before(jiffies, timeout))
168 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
170 OMAP_HSMMC_WRITE(host->base, CON,
171 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
172 enable_irq(host->irq);
176 * Configure the response type and send the cmd.
179 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
180 struct mmc_data *data)
182 int cmdreg = 0, resptype = 0, cmdtype = 0;
184 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
185 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
189 * Clear status bits and enable interrupts
191 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
192 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
193 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
195 if (cmd->flags & MMC_RSP_PRESENT) {
196 if (cmd->flags & MMC_RSP_136)
203 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
204 * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
206 if (cmd->opcode == 12)
209 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
212 cmdreg |= DP_SELECT | MSBS | BCE;
213 if (data->flags & MMC_DATA_READ)
222 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
223 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
227 * Notify the transfer complete to MMC core
230 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
234 if (host->use_dma && host->dma_ch != -1)
235 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
238 host->datadir = OMAP_MMC_DATADIR_NONE;
241 data->bytes_xfered += data->blocks * (data->blksz);
243 data->bytes_xfered = 0;
247 mmc_request_done(host->mmc, data->mrq);
250 mmc_omap_start_command(host, data->stop, NULL);
254 * Notify the core about command completion
257 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
261 if (cmd->flags & MMC_RSP_PRESENT) {
262 if (cmd->flags & MMC_RSP_136) {
263 /* response type 2 */
264 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
265 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
266 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
267 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
269 /* response types 1, 1b, 3, 4, 5, 6 */
270 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
273 if (host->data == NULL || cmd->error) {
275 mmc_request_done(host->mmc, cmd->mrq);
280 * DMA clean up for command errors
282 static void mmc_dma_cleanup(struct mmc_omap_host *host)
284 host->data->error = -ETIMEDOUT;
286 if (host->use_dma && host->dma_ch != -1) {
287 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
289 omap_free_dma(host->dma_ch);
294 host->datadir = OMAP_MMC_DATADIR_NONE;
298 * MMC controller IRQ handler
300 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
302 struct mmc_omap_host *host = dev_id;
303 int end_cmd = 0, end_trans = 0, status;
305 if (host->cmd == NULL && host->data == NULL) {
306 OMAP_HSMMC_WRITE(host->base, STAT,
307 OMAP_HSMMC_READ(host->base, STAT));
311 status = OMAP_HSMMC_READ(host->base, STAT);
312 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
315 if ((status & CMD_TIMEOUT) ||
316 (status & CMD_CRC)) {
318 if (status & CMD_TIMEOUT)
319 host->cmd->error = -ETIMEDOUT;
321 host->cmd->error = -EILSEQ;
325 mmc_dma_cleanup(host);
327 if ((status & DATA_TIMEOUT) ||
328 (status & DATA_CRC)) {
330 if (status & DATA_TIMEOUT)
331 mmc_dma_cleanup(host);
333 host->data->error = -EILSEQ;
337 if (status & CARD_ERR) {
338 dev_dbg(mmc_dev(host->mmc),
339 "Ignoring card err CMD%d\n", host->cmd->opcode);
347 OMAP_HSMMC_WRITE(host->base, STAT, status);
349 if (end_cmd || (status & CC))
350 mmc_omap_cmd_done(host, host->cmd);
351 if (end_trans || (status & TC))
352 mmc_omap_xfer_done(host, host->data);
358 * Switch MMC operating voltage
360 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
365 /* Disable the clocks */
366 clk_disable(host->fclk);
367 clk_disable(host->iclk);
368 clk_disable(host->dbclk);
370 /* Turn the power off */
371 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
375 /* Turn the power ON with given VDD 1.8 or 3.0v */
376 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
380 clk_enable(host->fclk);
381 clk_enable(host->iclk);
382 clk_enable(host->dbclk);
384 OMAP_HSMMC_WRITE(host->base, HCTL,
385 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
386 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
388 * If a MMC dual voltage card is detected, the set_ios fn calls
389 * this fn with VDD bit set for 1.8V. Upon card removal from the
390 * slot, mmc_omap_detect fn sets the VDD back to 3V.
392 if (((1 << vdd) == MMC_VDD_32_33) || ((1 << vdd) == MMC_VDD_33_34))
394 if ((1 << vdd) == MMC_VDD_165_195)
397 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
399 OMAP_HSMMC_WRITE(host->base, HCTL,
400 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
404 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage \n");
409 * Work Item to notify the core about card insertion/removal
411 static void mmc_omap_detect(struct work_struct *work)
414 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
415 mmc_carddetect_work);
417 if (host->carddetect) {
418 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
420 * Set the VDD back to 3V when the card is removed
421 * before the set_ios fn turns off the power.
423 vdd = fls(host->mmc->ocr_avail) - 1;
424 if (omap_mmc_switch_opcond(host, vdd) != 0)
425 host->mmc->ios.vdd = vdd;
427 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
429 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
433 * ISR for handling card insertion and removal
435 void omap_mmc_notify_card_detect(struct device *dev, int slot, int detected)
437 struct mmc_omap_host *host = dev_get_drvdata(dev);
438 host->carddetect = detected;
439 schedule_work(&host->mmc_carddetect_work);
443 * DMA call back function
445 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
447 struct mmc_omap_host *host = data;
449 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
450 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
452 if (host->dma_ch < 0)
455 omap_free_dma(host->dma_ch);
458 * DMA Callback: run in interrupt context.
459 * mutex_unlock will through a kernel warning if used.
465 * Configure dma src and destination parameters
467 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
468 struct mmc_data *data)
471 omap_set_dma_dest_params(host->dma_ch, 0,
472 OMAP_DMA_AMODE_CONSTANT,
473 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
474 omap_set_dma_src_params(host->dma_ch, 0,
475 OMAP_DMA_AMODE_POST_INC,
476 sg_dma_address(&data->sg[0]), 0, 0);
478 omap_set_dma_src_params(host->dma_ch, 0,
479 OMAP_DMA_AMODE_CONSTANT,
480 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
481 omap_set_dma_dest_params(host->dma_ch, 0,
482 OMAP_DMA_AMODE_POST_INC,
483 sg_dma_address(&data->sg[0]), 0, 0);
488 * Routine to configure and start DMA for the MMC card
491 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
493 int sync_dev, sync_dir = 0;
494 int dma_ch = 0, ret = 0, err = 1;
495 struct mmc_data *data = req->data;
498 * If for some reason the DMA transfer is still active,
499 * we wait for timeout period and free the dma
501 if (host->dma_ch != -1) {
502 set_current_state(TASK_UNINTERRUPTIBLE);
503 schedule_timeout(100);
504 if (down_trylock(&host->sem)) {
505 omap_free_dma(host->dma_ch);
511 if (down_trylock(&host->sem))
515 if (!(data->flags & MMC_DATA_WRITE)) {
516 host->dma_dir = DMA_FROM_DEVICE;
517 sync_dev = OMAP24XX_DMA_MMC1_RX;
519 host->dma_dir = DMA_TO_DEVICE;
520 sync_dev = OMAP24XX_DMA_MMC1_TX;
523 ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
526 dev_dbg(mmc_dev(host->mmc),
527 "%s: omap_request_dma() failed with %d\n",
528 mmc_hostname(host->mmc), ret);
532 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
533 data->sg_len, host->dma_dir);
534 host->dma_ch = dma_ch;
536 if (!(data->flags & MMC_DATA_WRITE))
537 mmc_omap_config_dma_param(1, host, data);
539 mmc_omap_config_dma_param(0, host, data);
541 if ((data->blksz % 4) == 0)
542 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
543 (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
546 /* REVISIT: The MMC buffer increments only when MSB is written.
547 * Return error for blksz which is non multiple of four.
551 omap_start_dma(dma_ch);
556 * Configure block length for MMC/SD cards and initiate the transfer.
559 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
562 host->data = req->data;
564 if (req->data == NULL) {
565 host->datadir = OMAP_MMC_DATADIR_NONE;
566 OMAP_HSMMC_WRITE(host->base, BLK, 0);
570 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
571 | (req->data->blocks << 16));
573 host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
574 OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
577 ret = mmc_omap_start_dma_transfer(host, req);
579 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
587 * Request function. for read/write operation
589 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
591 struct mmc_omap_host *host = mmc_priv(mmc);
593 WARN_ON(host->mrq != NULL);
595 mmc_omap_prepare_data(host, req);
596 mmc_omap_start_command(host, req->cmd, req->data);
600 /* Routine to configure clock values. Exposed API to core */
601 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
603 struct mmc_omap_host *host = mmc_priv(mmc);
605 unsigned long regval;
606 unsigned long timeout;
608 switch (ios->power_mode) {
610 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
613 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
617 switch (mmc->ios.bus_width) {
618 case MMC_BUS_WIDTH_4:
619 OMAP_HSMMC_WRITE(host->base, HCTL,
620 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
622 case MMC_BUS_WIDTH_1:
623 OMAP_HSMMC_WRITE(host->base, HCTL,
624 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
628 if (host->id == OMAP_MMC1_DEVID) {
629 /* Only MMC1 can operate at 3V/1.8V */
630 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
631 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
633 * The mmc_select_voltage fn of the core does
634 * not seem to set the power_mode to
635 * MMC_POWER_UP upon recalculating the voltage.
638 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
639 dev_dbg(mmc_dev(host->mmc),
640 "Switch operation failed\n");
645 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
649 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
655 omap_mmc_stop_clock(host);
656 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
657 regval = regval & ~(CLKD_MASK);
658 regval = regval | (dsor << 6) | (DTO << 16);
659 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
660 OMAP_HSMMC_WRITE(host->base, SYSCTL,
661 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
663 /* Wait till the ICS bit is set */
664 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
665 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
666 && time_before(jiffies, timeout))
669 OMAP_HSMMC_WRITE(host->base, SYSCTL,
670 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
672 if (ios->power_mode == MMC_POWER_ON)
673 send_init_stream(host);
675 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
676 OMAP_HSMMC_WRITE(host->base, CON,
677 OMAP_HSMMC_READ(host->base, CON) | OD);
679 /* NOTE: Read only switch not supported yet */
680 static struct mmc_host_ops mmc_omap_ops = {
681 .request = omap_mmc_request,
682 .set_ios = omap_mmc_set_ios,
685 static int __init omap_mmc_probe(struct platform_device *pdev)
687 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
688 struct mmc_host *mmc;
689 struct mmc_omap_host *host = NULL;
690 struct resource *res;
694 dev_err(&pdev->dev, "Platform Data is missing\n");
698 if (pdata->nr_slots == 0) {
699 dev_err(&pdev->dev, "No Slots\n");
703 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
704 irq = platform_get_irq(pdev, 0);
705 if (res == NULL || irq < 0)
708 res = request_mem_region(res->start, res->end - res->start + 1,
713 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
719 host = mmc_priv(mmc);
727 host->mapbase = res->start;
728 host->base = ioremap(host->mapbase, SZ_4K);
729 mmc->ops = &mmc_omap_ops;
731 mmc->f_max = 52000000;
733 sema_init(&host->sem, 1);
735 host->iclk = clk_get(&pdev->dev, "mmchs_ick");
736 if (IS_ERR(host->iclk)) {
737 ret = PTR_ERR(host->iclk);
741 host->fclk = clk_get(&pdev->dev, "mmchs_fck");
742 if (IS_ERR(host->fclk)) {
743 ret = PTR_ERR(host->fclk);
749 if (clk_enable(host->fclk) != 0)
752 if (clk_enable(host->iclk) != 0) {
753 clk_disable(host->fclk);
758 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
760 * MMC can still work without debounce clock.
762 if (IS_ERR(host->dbclk))
763 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock \n");
765 if (clk_enable(host->dbclk) != 0)
766 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
769 host->dbclk_enabled = 1;
771 mmc->ocr_avail = mmc_slot(host).ocr_mask;
772 mmc->caps |= MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
773 MMC_CAP_SD_HIGHSPEED;
775 if (pdata->conf.wire4)
776 mmc->caps |= MMC_CAP_4_BIT_DATA;
778 OMAP_HSMMC_WRITE(host->base, HCTL,
779 OMAP_HSMMC_READ(host->base, HCTL) | SDVS30);
781 OMAP_HSMMC_WRITE(host->base, CAPA, OMAP_HSMMC_READ(host->base,
782 CAPA) | VS30 | VS18);
784 /* Set the controller to AUTO IDLE mode */
785 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
786 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
788 /* Set SD bus power bit */
789 OMAP_HSMMC_WRITE(host->base, HCTL,
790 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
792 /* Request IRQ for MMC operations */
793 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED, pdev->name,
796 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ");
800 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
801 if (pdata->init != NULL) {
802 if (pdata->init(&pdev->dev) != 0) {
803 free_irq(host->irq, host);
808 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
809 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
811 platform_set_drvdata(pdev, host);
817 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
823 dev_dbg(mmc_dev(host->mmc), "Unable to configure MMC IRQs");
824 clk_disable(host->fclk);
825 clk_disable(host->iclk);
828 if (host->dbclk_enabled) {
829 clk_disable(host->dbclk);
830 clk_put(host->dbclk);
838 static int omap_mmc_remove(struct platform_device *pdev)
840 struct mmc_omap_host *host = platform_get_drvdata(pdev);
842 platform_set_drvdata(pdev, NULL);
844 host->pdata->cleanup(&pdev->dev);
845 free_irq(host->irq, host);
846 flush_scheduled_work();
848 clk_disable(host->fclk);
849 clk_disable(host->iclk);
852 if (host->dbclk_enabled) {
853 clk_disable(host->dbclk);
854 clk_put(host->dbclk);
857 mmc_free_host(host->mmc);
864 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
867 struct mmc_omap_host *host = platform_get_drvdata(pdev);
869 if (host && host->suspended)
873 ret = mmc_suspend_host(host->mmc, state);
877 OMAP_HSMMC_WRITE(host->base, ISE, 0);
878 OMAP_HSMMC_WRITE(host->base, IE, 0);
880 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
882 dev_dbg(mmc_dev(host->mmc),
883 "Unable to handle MMC board"
886 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
887 OMAP_HSMMC_WRITE(host->base, HCTL,
888 OMAP_HSMMC_READ(host->base, HCTL)
890 OMAP_HSMMC_WRITE(host->base, HCTL,
891 OMAP_HSMMC_READ(host->base, HCTL)
893 OMAP_HSMMC_WRITE(host->base, HCTL,
894 OMAP_HSMMC_READ(host->base, HCTL)
898 clk_disable(host->fclk);
899 clk_disable(host->iclk);
900 clk_disable(host->dbclk);
907 /* Routine to resume the MMC device */
908 static int omap_mmc_resume(struct platform_device *pdev)
911 struct mmc_omap_host *host = platform_get_drvdata(pdev);
913 if (host && !host->suspended)
918 ret = clk_enable(host->fclk);
922 ret = clk_enable(host->iclk);
924 clk_disable(host->fclk);
929 if (clk_enable(host->dbclk) != 0)
930 dev_dbg(mmc_dev(host->mmc),
931 "Enabling debounce clk failed\n");
933 ret = host->pdata->resume(&pdev->dev, host->slot_id);
935 dev_dbg(mmc_dev(host->mmc),
936 "Unmask interrupt failed\n");
938 /* Notify the core to resume the host */
939 ret = mmc_resume_host(host->mmc);
947 dev_dbg(mmc_dev(host->mmc),
948 "Failed to enable MMC clocks during resume\n");
953 #define omap_mmc_suspend NULL
954 #define omap_mmc_resume NULL
957 static struct platform_driver omap_mmc_driver = {
958 .probe = omap_mmc_probe,
959 .remove = omap_mmc_remove,
960 .suspend = omap_mmc_suspend,
961 .resume = omap_mmc_resume,
967 static int __init omap_mmc_init(void)
969 /* Register the MMC driver */
970 return platform_driver_register(&omap_mmc_driver);
973 static void __exit omap_mmc_cleanup(void)
975 /* Unregister MMC driver */
976 platform_driver_unregister(&omap_mmc_driver);
979 module_init(omap_mmc_init);
980 module_exit(omap_mmc_cleanup);
982 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
983 MODULE_LICENSE("GPL");
984 MODULE_ALIAS(DRIVER_NAME);
985 MODULE_AUTHOR("Texas Instruments Inc");