drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/mmc.h>
  25 #include <linux/mmc/host.h>
  26 #include <linux/mmc/card.h>
  27 #include <linux/clk.h>
  28 #include <linux/scatterlist.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/mmc.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/dma.h>
  38 #include <asm/arch/mux.h>
  39 #include <asm/arch/fpga.h>
  40 #include <asm/arch/tps65010.h>
  41 #include <asm/arch/board-sx1.h>
  42
  43 #define OMAP_MMC_REG_CMD        0x00
  44 #define OMAP_MMC_REG_ARGL       0x04
  45 #define OMAP_MMC_REG_ARGH       0x08
  46 #define OMAP_MMC_REG_CON        0x0c
  47 #define OMAP_MMC_REG_STAT       0x10
  48 #define OMAP_MMC_REG_IE         0x14
  49 #define OMAP_MMC_REG_CTO        0x18
  50 #define OMAP_MMC_REG_DTO        0x1c
  51 #define OMAP_MMC_REG_DATA       0x20
  52 #define OMAP_MMC_REG_BLEN       0x24
  53 #define OMAP_MMC_REG_NBLK       0x28
  54 #define OMAP_MMC_REG_BUF        0x2c
  55 #define OMAP_MMC_REG_SDIO       0x34
  56 #define OMAP_MMC_REG_REV        0x3c
  57 #define OMAP_MMC_REG_RSP0       0x40
  58 #define OMAP_MMC_REG_RSP1       0x44
  59 #define OMAP_MMC_REG_RSP2       0x48
  60 #define OMAP_MMC_REG_RSP3       0x4c
  61 #define OMAP_MMC_REG_RSP4       0x50
  62 #define OMAP_MMC_REG_RSP5       0x54
  63 #define OMAP_MMC_REG_RSP6       0x58
  64 #define OMAP_MMC_REG_RSP7       0x5c
  65 #define OMAP_MMC_REG_IOSR       0x60
  66 #define OMAP_MMC_REG_SYSC       0x64
  67 #define OMAP_MMC_REG_SYSS       0x68
  68
  69 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  70 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  71 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  72 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  73 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  74 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  75 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  76 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  77 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  78 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  79 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  80 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  81 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  82
  83 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  84 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  85
  86 /*
  87  * Command types
  88  */
  89 #define OMAP_MMC_CMDTYPE_BC     0
  90 #define OMAP_MMC_CMDTYPE_BCR    1
  91 #define OMAP_MMC_CMDTYPE_AC     2
  92 #define OMAP_MMC_CMDTYPE_ADTC   3
  93
  94
  95 #define DRIVER_NAME "mmci-omap"
  96
  97 /* Specifies how often in millisecs to poll for card status changes
  98  * when the cover switch is open */
  99 #define OMAP_MMC_SWITCH_POLL_DELAY      500
 100
 101 struct mmc_omap_host;
 102
 103 struct mmc_omap_slot {
 104         int                     id;
 105         unsigned int            vdd;
 106         u16                     saved_con;
 107         u16                     bus_mode;
 108         unsigned int            fclk_freq;
 109         unsigned                powered:1;
 110
 111         struct work_struct      switch_work;
 112         struct timer_list       switch_timer;
 113         unsigned                cover_open;
 114
 115         struct mmc_request      *mrq;
 116         struct mmc_omap_host    *host;
 117         struct mmc_host         *mmc;
 118         struct omap_mmc_slot_data *pdata;
 119 };
 120
 121 struct mmc_omap_host {
 122         int                     initialized;
 123         int                     suspended;
 124         struct mmc_request *    mrq;
 125         struct mmc_command *    cmd;
 126         struct mmc_data *       data;
 127         struct mmc_host *       mmc;
 128         struct device *         dev;
 129         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 130         struct clk *            iclk;
 131         struct clk *            fclk;
 132         struct resource         *mem_res;
 133         void __iomem            *virt_base;
 134         unsigned int            phys_base;
 135         int                     irq;
 136         unsigned char           bus_mode;
 137         unsigned char           hw_bus_mode;
 138
 139         unsigned int            sg_len;
 140         int                     sg_idx;
 141         u16 *                   buffer;
 142         u32                     buffer_bytes_left;
 143         u32                     total_bytes_left;
 144
 145         unsigned                use_dma:1;
 146         unsigned                brs_received:1, dma_done:1;
 147         unsigned                dma_is_read:1;
 148         unsigned                dma_in_use:1;
 149         int                     dma_ch;
 150         spinlock_t              dma_lock;
 151         struct timer_list       dma_timer;
 152         unsigned                dma_len;
 153
 154         short                   power_pin;
 155
 156         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 157         struct mmc_omap_slot    *current_slot;
 158         spinlock_t              slot_lock;
 159         wait_queue_head_t       slot_wq;
 160         int                     nr_slots;
 161
 162         struct omap_mmc_platform_data *pdata;
 163 };
 164
 165 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 166 {
 167         struct mmc_omap_host *host = slot->host;
 168         unsigned long flags;
 169
 170         if (claimed)
 171                 goto no_claim;
 172         spin_lock_irqsave(&host->slot_lock, flags);
 173         while (host->mmc != NULL) {
 174                 spin_unlock_irqrestore(&host->slot_lock, flags);
 175                 wait_event(host->slot_wq, host->mmc == NULL);
 176                 spin_lock_irqsave(&host->slot_lock, flags);
 177         }
 178         host->mmc = slot->mmc;
 179         spin_unlock_irqrestore(&host->slot_lock, flags);
 180 no_claim:
 181         clk_enable(host->fclk);
 182         if (host->current_slot != slot) {
 183                 if (host->pdata->switch_slot != NULL)
 184                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 185                 host->current_slot = slot;
 186         }
 187
 188         /* Doing the dummy read here seems to work around some bug
 189          * at least in OMAP24xx silicon where the command would not
 190          * start after writing the CMD register. Sigh. */
 191         OMAP_MMC_READ(host, CON);
 192
 193         OMAP_MMC_WRITE(host, CON, slot->saved_con);
 194 }
 195
 196 static void mmc_omap_start_request(struct mmc_omap_host *host,
 197                                    struct mmc_request *req);
 198
 199 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
 200 {
 201         struct mmc_omap_host *host = slot->host;
 202         unsigned long flags;
 203         int i;
 204
 205         BUG_ON(slot == NULL || host->mmc == NULL);
 206         clk_disable(host->fclk);
 207
 208         spin_lock_irqsave(&host->slot_lock, flags);
 209         /* Check for any pending requests */
 210         for (i = 0; i < host->nr_slots; i++) {
 211                 struct mmc_omap_slot *new_slot;
 212                 struct mmc_request *rq;
 213
 214                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 215                         continue;
 216
 217                 new_slot = host->slots[i];
 218                 /* The current slot should not have a request in queue */
 219                 BUG_ON(new_slot == host->current_slot);
 220
 221                 host->mmc = new_slot->mmc;
 222                 spin_unlock_irqrestore(&host->slot_lock, flags);
 223                 mmc_omap_select_slot(new_slot, 1);
 224                 rq = new_slot->mrq;
 225                 new_slot->mrq = NULL;
 226                 mmc_omap_start_request(host, rq);
 227                 return;
 228         }
 229
 230         host->mmc = NULL;
 231         wake_up(&host->slot_wq);
 232         spin_unlock_irqrestore(&host->slot_lock, flags);
 233 }
 234
 235 static inline
 236 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 237 {
 238         return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
 239 }
 240
 241 static ssize_t
 242 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 243                            char *buf)
 244 {
 245         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 246         struct mmc_omap_slot *slot = mmc_priv(mmc);
 247
 248         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 249                        "closed");
 250 }
 251
 252 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 253
 254 /* Access to the R/O switch is required for production testing
 255  * purposes. */
 256 static ssize_t
 257 mmc_omap_show_ro(struct device *dev, struct device_attribute *attr, char *buf)
 258 {
 259         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 260         struct mmc_omap_slot *slot = mmc_priv(mmc);
 261
 262         return sprintf(buf, "%d\n", slot->pdata->get_ro(mmc_dev(mmc),
 263                                                         slot->id));
 264 }
 265
 266 static DEVICE_ATTR(ro, S_IRUGO, mmc_omap_show_ro, NULL);
 267
 268 static ssize_t
 269 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 270                         char *buf)
 271 {
 272         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 273         struct mmc_omap_slot *slot = mmc_priv(mmc);
 274
 275         return sprintf(buf, "%s\n", slot->pdata->name);
 276 }
 277
 278 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 279
 280 static void
 281 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 282 {
 283         u32 cmdreg;
 284         u32 resptype;
 285         u32 cmdtype;
 286
 287         host->cmd = cmd;
 288
 289         resptype = 0;
 290         cmdtype = 0;
 291
 292         /* Our hardware needs to know exact type */
 293         switch (mmc_resp_type(cmd)) {
 294         case MMC_RSP_NONE:
 295                 break;
 296         case MMC_RSP_R1:
 297         case MMC_RSP_R1B:
 298                 /* resp 1, 1b, 6, 7 */
 299                 resptype = 1;
 300                 break;
 301         case MMC_RSP_R2:
 302                 resptype = 2;
 303                 break;
 304         case MMC_RSP_R3:
 305                 resptype = 3;
 306                 break;
 307         default:
 308                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 309                 break;
 310         }
 311
 312         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 313                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 314         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 315                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 316         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 317                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 318         } else {
 319                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 320         }
 321
 322         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 323
 324         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 325                 cmdreg |= 1 << 6;
 326
 327         if (cmd->flags & MMC_RSP_BUSY)
 328                 cmdreg |= 1 << 11;
 329
 330         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 331                 cmdreg |= 1 << 15;
 332
 333         OMAP_MMC_WRITE(host, CTO, 200);
 334         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 335         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 336         OMAP_MMC_WRITE(host, IE,
 337                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 338                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 339                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 340                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 341                        OMAP_MMC_STAT_END_OF_DATA);
 342         OMAP_MMC_WRITE(host, CMD, cmdreg);
 343 }
 344
 345 static void
 346 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 347 {
 348         if (host->dma_in_use) {
 349                 enum dma_data_direction dma_data_dir;
 350
 351                 BUG_ON(host->dma_ch < 0);
 352                 if (data->error)
 353                         omap_stop_dma(host->dma_ch);
 354                 /* Release DMA channel lazily */
 355                 mod_timer(&host->dma_timer, jiffies + HZ);
 356                 if (data->flags & MMC_DATA_WRITE)
 357                         dma_data_dir = DMA_TO_DEVICE;
 358                 else
 359                         dma_data_dir = DMA_FROM_DEVICE;
 360                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 361                              dma_data_dir);
 362         }
 363         host->data = NULL;
 364         host->sg_len = 0;
 365         clk_disable(host->fclk);
 366
 367         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 368          * dozens of requests until the card finishes writing data.
 369          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 370          */
 371
 372         if (!data->stop) {
 373                 host->mrq = NULL;
 374                 mmc_request_done(host->mmc, data->mrq);
 375                 return;
 376         }
 377
 378         mmc_omap_start_command(host, data->stop);
 379 }
 380
 381 static void
 382 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 383 {
 384         unsigned long flags;
 385         int done;
 386
 387         if (!host->dma_in_use) {
 388                 mmc_omap_xfer_done(host, data);
 389                 return;
 390         }
 391         done = 0;
 392         spin_lock_irqsave(&host->dma_lock, flags);
 393         if (host->dma_done)
 394                 done = 1;
 395         else
 396                 host->brs_received = 1;
 397         spin_unlock_irqrestore(&host->dma_lock, flags);
 398         if (done)
 399                 mmc_omap_xfer_done(host, data);
 400 }
 401
 402 static void
 403 mmc_omap_dma_timer(unsigned long data)
 404 {
 405         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 406
 407         BUG_ON(host->dma_ch < 0);
 408         omap_free_dma(host->dma_ch);
 409         host->dma_ch = -1;
 410 }
 411
 412 static void
 413 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 414 {
 415         unsigned long flags;
 416         int done;
 417
 418         done = 0;
 419         spin_lock_irqsave(&host->dma_lock, flags);
 420         if (host->brs_received)
 421                 done = 1;
 422         else
 423                 host->dma_done = 1;
 424         spin_unlock_irqrestore(&host->dma_lock, flags);
 425         if (done)
 426                 mmc_omap_xfer_done(host, data);
 427 }
 428
 429 static void
 430 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 431 {
 432         host->cmd = NULL;
 433
 434         if (cmd->flags & MMC_RSP_PRESENT) {
 435                 if (cmd->flags & MMC_RSP_136) {
 436                         /* response type 2 */
 437                         cmd->resp[3] =
 438                                 OMAP_MMC_READ(host, RSP0) |
 439                                 (OMAP_MMC_READ(host, RSP1) << 16);
 440                         cmd->resp[2] =
 441                                 OMAP_MMC_READ(host, RSP2) |
 442                                 (OMAP_MMC_READ(host, RSP3) << 16);
 443                         cmd->resp[1] =
 444                                 OMAP_MMC_READ(host, RSP4) |
 445                                 (OMAP_MMC_READ(host, RSP5) << 16);
 446                         cmd->resp[0] =
 447                                 OMAP_MMC_READ(host, RSP6) |
 448                                 (OMAP_MMC_READ(host, RSP7) << 16);
 449                 } else {
 450                         /* response types 1, 1b, 3, 4, 5, 6 */
 451                         cmd->resp[0] =
 452                                 OMAP_MMC_READ(host, RSP6) |
 453                                 (OMAP_MMC_READ(host, RSP7) << 16);
 454                 }
 455         }
 456
 457         if (host->data == NULL || cmd->error) {
 458                 host->mrq = NULL;
 459                 clk_disable(host->fclk);
 460                 mmc_request_done(host->mmc, cmd->mrq);
 461         }
 462 }
 463
 464 /* PIO only */
 465 static void
 466 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 467 {
 468         struct scatterlist *sg;
 469
 470         sg = host->data->sg + host->sg_idx;
 471         host->buffer_bytes_left = sg->length;
 472         host->buffer = sg_virt(sg);
 473         if (host->buffer_bytes_left > host->total_bytes_left)
 474                 host->buffer_bytes_left = host->total_bytes_left;
 475 }
 476
 477 /* PIO only */
 478 static void
 479 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 480 {
 481         int n;
 482
 483         if (host->buffer_bytes_left == 0) {
 484                 host->sg_idx++;
 485                 BUG_ON(host->sg_idx == host->sg_len);
 486                 mmc_omap_sg_to_buf(host);
 487         }
 488         n = 64;
 489         if (n > host->buffer_bytes_left)
 490                 n = host->buffer_bytes_left;
 491         host->buffer_bytes_left -= n;
 492         host->total_bytes_left -= n;
 493         host->data->bytes_xfered += n;
 494
 495         if (write) {
 496                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 497         } else {
 498                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 499         }
 500 }
 501
 502 static inline void mmc_omap_report_irq(u16 status)
 503 {
 504         static const char *mmc_omap_status_bits[] = {
 505                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 506                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 507         };
 508         int i, c = 0;
 509
 510         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 511                 if (status & (1 << i)) {
 512                         if (c)
 513                                 printk(" ");
 514                         printk("%s", mmc_omap_status_bits[i]);
 515                         c++;
 516                 }
 517 }
 518
 519 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 520 {
 521         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 522         u16 status;
 523         int end_command;
 524         int end_transfer;
 525         int transfer_error;
 526
 527         if (host->cmd == NULL && host->data == NULL) {
 528                 status = OMAP_MMC_READ(host, STAT);
 529                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 530                 if (status != 0) {
 531                         OMAP_MMC_WRITE(host, STAT, status);
 532                         OMAP_MMC_WRITE(host, IE, 0);
 533                 }
 534                 return IRQ_HANDLED;
 535         }
 536
 537         end_command = 0;
 538         end_transfer = 0;
 539         transfer_error = 0;
 540
 541         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 542                 OMAP_MMC_WRITE(host, STAT, status);
 543 #ifdef CONFIG_MMC_DEBUG
 544                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 545                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 546                 mmc_omap_report_irq(status);
 547                 printk("\n");
 548 #endif
 549                 if (host->total_bytes_left) {
 550                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 551                             (status & OMAP_MMC_STAT_END_OF_DATA))
 552                                 mmc_omap_xfer_data(host, 0);
 553                         if (status & OMAP_MMC_STAT_A_EMPTY)
 554                                 mmc_omap_xfer_data(host, 1);
 555                 }
 556
 557                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 558                         end_transfer = 1;
 559                 }
 560
 561                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 562                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 563                         if (host->data) {
 564                                 host->data->error = -ETIMEDOUT;
 565                                 transfer_error = 1;
 566                         }
 567                 }
 568
 569                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 570                         if (host->data) {
 571                                 host->data->error = -EILSEQ;
 572                                 dev_dbg(mmc_dev(host->mmc),
 573                                          "data CRC error, bytes left %d\n",
 574                                         host->total_bytes_left);
 575                                 transfer_error = 1;
 576                         } else {
 577                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 578                         }
 579                 }
 580
 581                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 582                         /* Timeouts are routine with some commands */
 583                         if (host->cmd) {
 584                                 struct mmc_omap_slot *slot =
 585                                         host->current_slot;
 586                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 587                                                 host->cmd->opcode !=
 588                                                 MMC_SEND_OP_COND &&
 589                                                 host->cmd->opcode !=
 590                                                 MMC_APP_CMD &&
 591                                                 !mmc_omap_cover_is_open(slot))
 592                                         dev_err(mmc_dev(host->mmc),
 593                                                 "command timeout, CMD %d\n",
 594                                                 host->cmd->opcode);
 595                                 host->cmd->error = -ETIMEDOUT;
 596                                 end_command = 1;
 597                         }
 598                 }
 599
 600                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 601                         if (host->cmd) {
 602                                 dev_err(mmc_dev(host->mmc),
 603                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 604                                         host->cmd->opcode, host->cmd->arg);
 605                                 host->cmd->error = -EILSEQ;
 606                                 end_command = 1;
 607                         } else
 608                                 dev_err(mmc_dev(host->mmc),
 609                                         "command CRC error without cmd?\n");
 610                 }
 611
 612                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 613                         dev_dbg(mmc_dev(host->mmc),
 614                                 "ignoring card status error (CMD%d)\n",
 615                                 host->cmd->opcode);
 616                         end_command = 1;
 617                 }
 618
 619                 /*
 620                  * NOTE: On 1610 the END_OF_CMD may come too early when
 621                  * starting a write
 622                  */
 623                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 624                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 625                         end_command = 1;
 626                 }
 627         }
 628
 629         if (end_command) {
 630                 mmc_omap_cmd_done(host, host->cmd);
 631         }
 632         if (transfer_error)
 633                 mmc_omap_xfer_done(host, host->data);
 634         else if (end_transfer)
 635                 mmc_omap_end_of_data(host, host->data);
 636
 637         return IRQ_HANDLED;
 638 }
 639
 640 void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed)
 641 {
 642         struct mmc_omap_host *host = dev_get_drvdata(dev);
 643
 644         BUG_ON(slot >= host->nr_slots);
 645
 646         /* Other subsystems can call in here before we're initialised. */
 647         if (host->nr_slots == 0 || !host->slots[slot])
 648                 return;
 649
 650         schedule_work(&host->slots[slot]->switch_work);
 651 }
 652
 653 static void mmc_omap_switch_timer(unsigned long arg)
 654 {
 655         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 656
 657         schedule_work(&slot->switch_work);
 658 }
 659
 660 static void mmc_omap_cover_handler(struct work_struct *work)
 661 {
 662         struct mmc_omap_slot *slot = container_of(work, struct mmc_omap_slot,
 663                                                   switch_work);
 664         int cover_open;
 665
 666         cover_open = mmc_omap_cover_is_open(slot);
 667         if (cover_open != slot->cover_open) {
 668                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 669                 slot->cover_open = cover_open;
 670                 dev_info(mmc_dev(slot->mmc), "cover is now %s\n",
 671                          cover_open ? "open" : "closed");
 672         }
 673         mmc_detect_change(slot->mmc, slot->id);
 674 }
 675
 676 /* Prepare to transfer the next segment of a scatterlist */
 677 static void
 678 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 679 {
 680         int dma_ch = host->dma_ch;
 681         unsigned long data_addr;
 682         u16 buf, frame;
 683         u32 count;
 684         struct scatterlist *sg = &data->sg[host->sg_idx];
 685         int src_port = 0;
 686         int dst_port = 0;
 687         int sync_dev = 0;
 688
 689         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 690         frame = data->blksz;
 691         count = sg_dma_len(sg);
 692
 693         if ((data->blocks == 1) && (count > data->blksz))
 694                 count = frame;
 695
 696         host->dma_len = count;
 697
 698         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 699          * Use 16 or 32 word frames when the blocksize is at least that large.
 700          * Blocksize is usually 512 bytes; but not for some SD reads.
 701          */
 702         if (cpu_is_omap15xx() && frame > 32)
 703                 frame = 32;
 704         else if (frame > 64)
 705                 frame = 64;
 706         count /= frame;
 707         frame >>= 1;
 708
 709         if (!(data->flags & MMC_DATA_WRITE)) {
 710                 buf = 0x800f | ((frame - 1) << 8);
 711
 712                 if (cpu_class_is_omap1()) {
 713                         src_port = OMAP_DMA_PORT_TIPB;
 714                         dst_port = OMAP_DMA_PORT_EMIFF;
 715                 }
 716                 if (cpu_is_omap24xx())
 717                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 718
 719                 omap_set_dma_src_params(dma_ch, src_port,
 720                                         OMAP_DMA_AMODE_CONSTANT,
 721                                         data_addr, 0, 0);
 722                 omap_set_dma_dest_params(dma_ch, dst_port,
 723                                          OMAP_DMA_AMODE_POST_INC,
 724                                          sg_dma_address(sg), 0, 0);
 725                 omap_set_dma_dest_data_pack(dma_ch, 1);
 726                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 727         } else {
 728                 buf = 0x0f80 | ((frame - 1) << 0);
 729
 730                 if (cpu_class_is_omap1()) {
 731                         src_port = OMAP_DMA_PORT_EMIFF;
 732                         dst_port = OMAP_DMA_PORT_TIPB;
 733                 }
 734                 if (cpu_is_omap24xx())
 735                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 736
 737                 omap_set_dma_dest_params(dma_ch, dst_port,
 738                                          OMAP_DMA_AMODE_CONSTANT,
 739                                          data_addr, 0, 0);
 740                 omap_set_dma_src_params(dma_ch, src_port,
 741                                         OMAP_DMA_AMODE_POST_INC,
 742                                         sg_dma_address(sg), 0, 0);
 743                 omap_set_dma_src_data_pack(dma_ch, 1);
 744                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 745         }
 746
 747         /* Max limit for DMA frame count is 0xffff */
 748         BUG_ON(count > 0xffff);
 749
 750         OMAP_MMC_WRITE(host, BUF, buf);
 751         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 752                                      frame, count, OMAP_DMA_SYNC_FRAME,
 753                                      sync_dev, 0);
 754 }
 755
 756 /* A scatterlist segment completed */
 757 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 758 {
 759         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 760         struct mmc_data *mmcdat = host->data;
 761
 762         if (unlikely(host->dma_ch < 0)) {
 763                 dev_err(mmc_dev(host->mmc),
 764                         "DMA callback while DMA not enabled\n");
 765                 return;
 766         }
 767         /* FIXME: We really should do something to _handle_ the errors */
 768         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 769                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 770                 return;
 771         }
 772         if (ch_status & OMAP_DMA_DROP_IRQ) {
 773                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 774                 return;
 775         }
 776         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 777                 return;
 778         }
 779         mmcdat->bytes_xfered += host->dma_len;
 780         host->sg_idx++;
 781         if (host->sg_idx < host->sg_len) {
 782                 mmc_omap_prepare_dma(host, host->data);
 783                 omap_start_dma(host->dma_ch);
 784         } else
 785                 mmc_omap_dma_done(host, host->data);
 786 }
 787
 788 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 789 {
 790         const char *dev_name;
 791         int sync_dev, dma_ch, is_read, r;
 792
 793         is_read = !(data->flags & MMC_DATA_WRITE);
 794         del_timer_sync(&host->dma_timer);
 795         if (host->dma_ch >= 0) {
 796                 if (is_read == host->dma_is_read)
 797                         return 0;
 798                 omap_free_dma(host->dma_ch);
 799                 host->dma_ch = -1;
 800         }
 801
 802         if (is_read) {
 803                 if (host->id == 1) {
 804                         sync_dev = OMAP_DMA_MMC_RX;
 805                         dev_name = "MMC1 read";
 806                 } else {
 807                         sync_dev = OMAP_DMA_MMC2_RX;
 808                         dev_name = "MMC2 read";
 809                 }
 810         } else {
 811                 if (host->id == 1) {
 812                         sync_dev = OMAP_DMA_MMC_TX;
 813                         dev_name = "MMC1 write";
 814                 } else {
 815                         sync_dev = OMAP_DMA_MMC2_TX;
 816                         dev_name = "MMC2 write";
 817                 }
 818         }
 819         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 820                              host, &dma_ch);
 821         if (r != 0) {
 822                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 823                 return r;
 824         }
 825         host->dma_ch = dma_ch;
 826         host->dma_is_read = is_read;
 827
 828         return 0;
 829 }
 830
 831 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 832 {
 833         u16 reg;
 834
 835         reg = OMAP_MMC_READ(host, SDIO);
 836         reg &= ~(1 << 5);
 837         OMAP_MMC_WRITE(host, SDIO, reg);
 838         /* Set maximum timeout */
 839         OMAP_MMC_WRITE(host, CTO, 0xff);
 840 }
 841
 842 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 843 {
 844         int timeout;
 845         u16 reg;
 846
 847         /* Convert ns to clock cycles by assuming 20MHz frequency
 848          * 1 cycle at 20MHz = 500 ns
 849          */
 850         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 851
 852         /* Check if we need to use timeout multiplier register */
 853         reg = OMAP_MMC_READ(host, SDIO);
 854         if (timeout > 0xffff) {
 855                 reg |= (1 << 5);
 856                 timeout /= 1024;
 857         } else
 858                 reg &= ~(1 << 5);
 859         OMAP_MMC_WRITE(host, SDIO, reg);
 860         OMAP_MMC_WRITE(host, DTO, timeout);
 861 }
 862
 863 static void
 864 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 865 {
 866         struct mmc_data *data = req->data;
 867         int i, use_dma, block_size;
 868         unsigned sg_len;
 869
 870         host->data = data;
 871         if (data == NULL) {
 872                 OMAP_MMC_WRITE(host, BLEN, 0);
 873                 OMAP_MMC_WRITE(host, NBLK, 0);
 874                 OMAP_MMC_WRITE(host, BUF, 0);
 875                 host->dma_in_use = 0;
 876                 set_cmd_timeout(host, req);
 877                 return;
 878         }
 879
 880         block_size = data->blksz;
 881
 882         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 883         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 884         set_data_timeout(host, req);
 885
 886         /* cope with calling layer confusion; it issues "single
 887          * block" writes using multi-block scatterlists.
 888          */
 889         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 890
 891         /* Only do DMA for entire blocks */
 892         use_dma = host->use_dma;
 893         if (use_dma) {
 894                 for (i = 0; i < sg_len; i++) {
 895                         if ((data->sg[i].length % block_size) != 0) {
 896                                 use_dma = 0;
 897                                 break;
 898                         }
 899                 }
 900         }
 901
 902         host->sg_idx = 0;
 903         if (use_dma) {
 904                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 905                         enum dma_data_direction dma_data_dir;
 906
 907                         if (data->flags & MMC_DATA_WRITE)
 908                                 dma_data_dir = DMA_TO_DEVICE;
 909                         else
 910                                 dma_data_dir = DMA_FROM_DEVICE;
 911
 912                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 913                                                 sg_len, dma_data_dir);
 914                         host->total_bytes_left = 0;
 915                         mmc_omap_prepare_dma(host, req->data);
 916                         host->brs_received = 0;
 917                         host->dma_done = 0;
 918                         host->dma_in_use = 1;
 919                 } else
 920                         use_dma = 0;
 921         }
 922
 923         /* Revert to PIO? */
 924         if (!use_dma) {
 925                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 926                 host->total_bytes_left = data->blocks * block_size;
 927                 host->sg_len = sg_len;
 928                 mmc_omap_sg_to_buf(host);
 929                 host->dma_in_use = 0;
 930         }
 931 }
 932
 933 static void mmc_omap_start_request(struct mmc_omap_host *host,
 934                                    struct mmc_request *req)
 935 {
 936         BUG_ON(host->mrq != NULL);
 937
 938         host->mrq = req;
 939
 940         /* only touch fifo AFTER the controller readies it */
 941         mmc_omap_prepare_data(host, req);
 942         mmc_omap_start_command(host, req->cmd);
 943         if (host->dma_in_use)
 944                 omap_start_dma(host->dma_ch);
 945         BUG_ON(irqs_disabled());
 946 }
 947
 948 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 949 {
 950         struct mmc_omap_slot *slot = mmc_priv(mmc);
 951         struct mmc_omap_host *host = slot->host;
 952         unsigned long flags;
 953
 954         spin_lock_irqsave(&host->slot_lock, flags);
 955         if (host->mmc != NULL) {
 956                 BUG_ON(slot->mrq != NULL);
 957                 slot->mrq = req;
 958                 spin_unlock_irqrestore(&host->slot_lock, flags);
 959                 return;
 960         } else
 961                 host->mmc = mmc;
 962         spin_unlock_irqrestore(&host->slot_lock, flags);
 963         mmc_omap_select_slot(slot, 1);
 964         mmc_omap_start_request(host, req);
 965 }
 966
 967 static void innovator_fpga_socket_power(int on)
 968 {
 969 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 970         if (on) {
 971                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 972                      OMAP1510_FPGA_POWER);
 973         } else {
 974                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 975                      OMAP1510_FPGA_POWER);
 976         }
 977 #endif
 978 }
 979
 980 /*
 981  * Turn the socket power on/off. Innovator uses FPGA, most boards
 982  * probably use GPIO.
 983  */
 984 static void mmc_omap_power(struct mmc_omap_host *host, int on)
 985 {
 986         if (machine_is_sx1())
 987                 sx1_setmmcpower(on);
 988         else if (on) {
 989                 if (machine_is_omap_innovator())
 990                         innovator_fpga_socket_power(1);
 991                 else if (machine_is_omap_h2())
 992                         tps65010_set_gpio_out_value(GPIO3, HIGH);
 993                 else if (machine_is_omap_h3())
 994                         /* GPIO 4 of TPS65010 sends SD_EN signal */
 995                         tps65010_set_gpio_out_value(GPIO4, HIGH);
 996                 else if (cpu_is_omap24xx()) {
 997                         u16 reg = OMAP_MMC_READ(host, CON);
 998                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
 999                 } else
1000                         if (host->power_pin >= 0)
1001                                 omap_set_gpio_dataout(host->power_pin, 1);
1002         } else {
1003                 if (machine_is_omap_innovator())
1004                         innovator_fpga_socket_power(0);
1005                 else if (machine_is_omap_h2())
1006                         tps65010_set_gpio_out_value(GPIO3, LOW);
1007                 else if (machine_is_omap_h3())
1008                         tps65010_set_gpio_out_value(GPIO4, LOW);
1009                 else if (cpu_is_omap24xx()) {
1010                         u16 reg = OMAP_MMC_READ(host, CON);
1011                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
1012                 } else
1013                         if (host->power_pin >= 0)
1014                                 omap_set_gpio_dataout(host->power_pin, 0);
1015         }
1016 }
1017
1018 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1019 {
1020         struct mmc_omap_slot *slot = mmc_priv(mmc);
1021         struct mmc_omap_host *host = slot->host;
1022         int func_clk_rate = clk_get_rate(host->fclk);
1023         int dsor;
1024
1025         if (ios->clock == 0)
1026                 return 0;
1027
1028         dsor = func_clk_rate / ios->clock;
1029         if (dsor < 1)
1030                 dsor = 1;
1031
1032         if (func_clk_rate / dsor > ios->clock)
1033                 dsor++;
1034
1035         if (dsor > 250)
1036                 dsor = 250;
1037
1038         slot->fclk_freq = func_clk_rate / dsor;
1039
1040         if (ios->bus_width == MMC_BUS_WIDTH_4)
1041                 dsor |= 1 << 15;
1042
1043         return dsor;
1044 }
1045
1046 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1047 {
1048         struct mmc_omap_slot *slot = mmc_priv(mmc);
1049         struct mmc_omap_host *host = slot->host;
1050         int i, dsor;
1051
1052         dsor = mmc_omap_calc_divisor(mmc, ios);
1053         host->bus_mode = ios->bus_mode;
1054         host->hw_bus_mode = host->bus_mode;
1055
1056         switch (ios->power_mode) {
1057         case MMC_POWER_OFF:
1058                 mmc_omap_power(host, 0);
1059                 break;
1060         case MMC_POWER_UP:
1061                 /* Cannot touch dsor yet, just power up MMC */
1062                 mmc_omap_power(host, 1);
1063                 return;
1064         case MMC_POWER_ON:
1065                 dsor |= 1 << 11;
1066                 break;
1067         }
1068
1069         clk_enable(host->fclk);
1070
1071         /* On insanely high arm_per frequencies something sometimes
1072          * goes somehow out of sync, and the POW bit is not being set,
1073          * which results in the while loop below getting stuck.
1074          * Writing to the CON register twice seems to do the trick. */
1075         for (i = 0; i < 2; i++)
1076                 OMAP_MMC_WRITE(host, CON, dsor);
1077         if (ios->power_mode == MMC_POWER_ON) {
1078                 /* Send clock cycles, poll completion */
1079                 OMAP_MMC_WRITE(host, IE, 0);
1080                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1081                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1082                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1083                 OMAP_MMC_WRITE(host, STAT, 1);
1084         }
1085         clk_disable(host->fclk);
1086 }
1087
1088 static int mmc_omap_get_ro(struct mmc_host *mmc)
1089 {
1090         struct mmc_omap_slot *slot = mmc_priv(mmc);
1091
1092         if (slot->pdata->get_ro != NULL)
1093                 return slot->pdata->get_ro(mmc_dev(mmc), slot->id);
1094         return 0;
1095 }
1096
1097 static const struct mmc_host_ops mmc_omap_ops = {
1098         .request        = mmc_omap_request,
1099         .set_ios        = mmc_omap_set_ios,
1100         .get_ro         = mmc_omap_get_ro,
1101 };
1102
1103 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1104 {
1105         struct mmc_omap_slot *slot = NULL;
1106         struct mmc_host *mmc;
1107         int r;
1108
1109         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1110         if (mmc == NULL)
1111                 return -ENOMEM;
1112
1113         slot = mmc_priv(mmc);
1114         slot->host = host;
1115         slot->mmc = mmc;
1116         slot->id = id;
1117         slot->pdata = &host->pdata->slots[id];
1118
1119         host->slots[id] = slot;
1120
1121         mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
1122                     MMC_CAP_SD_HIGHSPEED;
1123         if (host->pdata->conf.wire4)
1124                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1125
1126         mmc->ops = &mmc_omap_ops;
1127         mmc->f_min = 400000;
1128
1129         if (cpu_class_is_omap2())
1130                 mmc->f_max = 48000000;
1131         else
1132                 mmc->f_max = 24000000;
1133         if (host->pdata->max_freq)
1134                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1135         mmc->ocr_avail = slot->pdata->ocr_mask;
1136
1137         /* Use scatterlist DMA to reduce per-transfer costs.
1138          * NOTE max_seg_size assumption that small blocks aren't
1139          * normally used (except e.g. for reading SD registers).
1140          */
1141         mmc->max_phys_segs = 32;
1142         mmc->max_hw_segs = 32;
1143         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1144         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1145         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1146         mmc->max_seg_size = mmc->max_req_size;
1147
1148         r = mmc_add_host(mmc);
1149         if (r < 0)
1150                 return r;
1151
1152         if (slot->pdata->name != NULL) {
1153                 r = device_create_file(&mmc->class_dev,
1154                                         &dev_attr_slot_name);
1155                 if (r < 0)
1156                         goto err_remove_host;
1157         }
1158
1159         if (slot->pdata->get_cover_state != NULL) {
1160                 r = device_create_file(&mmc->class_dev,
1161                                         &dev_attr_cover_switch);
1162                 if (r < 0)
1163                         goto err_remove_slot_name;
1164
1165                 INIT_WORK(&slot->switch_work, mmc_omap_cover_handler);
1166                 init_timer(&slot->switch_timer);
1167                 slot->switch_timer.function = mmc_omap_switch_timer;
1168                 slot->switch_timer.data = (unsigned long) slot;
1169                 schedule_work(&slot->switch_work);
1170         }
1171
1172         if (slot->pdata->get_ro != NULL) {
1173                 r = device_create_file(&mmc->class_dev,
1174                                         &dev_attr_ro);
1175                 if (r < 0)
1176                         goto err_remove_cover_attr;
1177         }
1178
1179         return 0;
1180
1181 err_remove_cover_attr:
1182         if (slot->pdata->get_cover_state != NULL)
1183                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1184 err_remove_slot_name:
1185         if (slot->pdata->name != NULL)
1186                 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1187 err_remove_host:
1188         mmc_remove_host(mmc);
1189         return r;
1190 }
1191
1192 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1193 {
1194         struct mmc_host *mmc = slot->mmc;
1195
1196         if (slot->pdata->name != NULL)
1197                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1198         if (slot->pdata->get_cover_state != NULL)
1199                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1200         if (slot->pdata->get_ro != NULL)
1201                 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1202
1203         del_timer_sync(&slot->switch_timer);
1204         flush_scheduled_work();
1205
1206         mmc_remove_host(mmc);
1207         mmc_free_host(mmc);
1208 }
1209
1210 static int __init mmc_omap_probe(struct platform_device *pdev)
1211 {
1212         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1213         struct mmc_omap_host *host = NULL;
1214         struct resource *res;
1215         int i, ret = 0;
1216         int irq;
1217
1218         if (pdata == NULL) {
1219                 dev_err(&pdev->dev, "platform data missing\n");
1220                 return -ENXIO;
1221         }
1222         if (pdata->nr_slots == 0) {
1223                 dev_err(&pdev->dev, "no slots\n");
1224                 return -ENXIO;
1225         }
1226
1227         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1228         irq = platform_get_irq(pdev, 0);
1229         if (res == NULL || irq < 0)
1230                 return -ENXIO;
1231
1232         res = request_mem_region(res->start, res->end - res->start + 1,
1233                                  pdev->name);
1234         if (res == NULL)
1235                 return -EBUSY;
1236
1237         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1238         if (host == NULL) {
1239                 ret = -ENOMEM;
1240                 goto err_free_mem_region;
1241         }
1242
1243         spin_lock_init(&host->dma_lock);
1244         init_timer(&host->dma_timer);
1245         spin_lock_init(&host->slot_lock);
1246         init_waitqueue_head(&host->slot_wq);
1247
1248         host->dma_timer.function = mmc_omap_dma_timer;
1249         host->dma_timer.data = (unsigned long) host;
1250
1251         host->pdata = pdata;
1252         host->dev = &pdev->dev;
1253         platform_set_drvdata(pdev, host);
1254
1255         host->id = pdev->id;
1256         host->mem_res = res;
1257         host->irq = irq;
1258
1259         host->use_dma = 1;
1260         host->dma_ch = -1;
1261
1262         host->irq = irq;
1263         host->phys_base = host->mem_res->start;
1264         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1265
1266         if (cpu_is_omap24xx()) {
1267                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1268                 if (IS_ERR(host->iclk))
1269                         goto err_free_mmc_host;
1270                 clk_enable(host->iclk);
1271         }
1272
1273         if (!cpu_is_omap24xx())
1274                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1275         else
1276                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1277
1278         if (IS_ERR(host->fclk)) {
1279                 ret = PTR_ERR(host->fclk);
1280                 goto err_free_iclk;
1281         }
1282
1283         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1284         if (ret)
1285                 goto err_free_fclk;
1286
1287         if (pdata->init != NULL) {
1288                 ret = pdata->init(&pdev->dev);
1289                 if (ret < 0)
1290                         goto err_free_irq;
1291         }
1292
1293         host->nr_slots = pdata->nr_slots;
1294         for (i = 0; i < pdata->nr_slots; i++) {
1295                 ret = mmc_omap_new_slot(host, i);
1296                 if (ret < 0) {
1297                         while (--i >= 0)
1298                                 mmc_omap_remove_slot(host->slots[i]);
1299
1300                         goto err_plat_cleanup;
1301                 }
1302         }
1303
1304         return 0;
1305
1306 err_plat_cleanup:
1307         if (pdata->cleanup)
1308                 pdata->cleanup(&pdev->dev);
1309 err_free_irq:
1310         free_irq(host->irq, host);
1311 err_free_fclk:
1312         clk_put(host->fclk);
1313 err_free_iclk:
1314         if (host->iclk != NULL) {
1315                 clk_disable(host->iclk);
1316                 clk_put(host->iclk);
1317         }
1318 err_free_mmc_host:
1319         kfree(host);
1320 err_free_mem_region:
1321         release_mem_region(res->start, res->end - res->start + 1);
1322         return ret;
1323 }
1324
1325 static int mmc_omap_remove(struct platform_device *pdev)
1326 {
1327         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1328         int i;
1329
1330         platform_set_drvdata(pdev, NULL);
1331
1332         BUG_ON(host == NULL);
1333
1334         for (i = 0; i < host->nr_slots; i++)
1335                 mmc_omap_remove_slot(host->slots[i]);
1336
1337         if (host->pdata->cleanup)
1338                 host->pdata->cleanup(&pdev->dev);
1339
1340         if (host->iclk && !IS_ERR(host->iclk))
1341                 clk_put(host->iclk);
1342         if (host->fclk && !IS_ERR(host->fclk))
1343                 clk_put(host->fclk);
1344
1345         release_mem_region(pdev->resource[0].start,
1346                            pdev->resource[0].end - pdev->resource[0].start + 1);
1347
1348         kfree(host);
1349
1350         return 0;
1351 }
1352
1353 #ifdef CONFIG_PM
1354 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1355 {
1356         int i, ret = 0;
1357         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1358
1359         if (host == NULL || host->suspended)
1360                 return 0;
1361
1362         for (i = 0; i < host->nr_slots; i++) {
1363                 struct mmc_omap_slot *slot;
1364
1365                 slot = host->slots[i];
1366                 ret = mmc_suspend_host(slot->mmc, mesg);
1367                 if (ret < 0) {
1368                         while (--i >= 0) {
1369                                 slot = host->slots[i];
1370                                 mmc_resume_host(slot->mmc);
1371                         }
1372                         return ret;
1373                 }
1374         }
1375         host->suspended = 1;
1376         return 0;
1377 }
1378
1379 static int mmc_omap_resume(struct platform_device *pdev)
1380 {
1381         int i, ret = 0;
1382         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1383
1384         if (host == NULL || !host->suspended)
1385                 return 0;
1386
1387         for (i = 0; i < host->nr_slots; i++) {
1388                 struct mmc_omap_slot *slot;
1389                 slot = host->slots[i];
1390                 ret = mmc_resume_host(slot->mmc);
1391                 if (ret < 0)
1392                         return ret;
1393
1394                 host->suspended = 0;
1395         }
1396         return 0;
1397 }
1398 #else
1399 #define mmc_omap_suspend        NULL
1400 #define mmc_omap_resume         NULL
1401 #endif
1402
1403 static struct platform_driver mmc_omap_driver = {
1404         .probe          = mmc_omap_probe,
1405         .remove         = mmc_omap_remove,
1406         .suspend        = mmc_omap_suspend,
1407         .resume         = mmc_omap_resume,
1408         .driver         = {
1409                 .name   = DRIVER_NAME,
1410         },
1411 };
1412
1413 static int __init mmc_omap_init(void)
1414 {
1415         return platform_driver_register(&mmc_omap_driver);
1416 }
1417
1418 static void __exit mmc_omap_exit(void)
1419 {
1420         platform_driver_unregister(&mmc_omap_driver);
1421 }
1422
1423 module_init(mmc_omap_init);
1424 module_exit(mmc_omap_exit);
1425
1426 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1427 MODULE_LICENSE("GPL");
1428 MODULE_ALIAS(DRIVER_NAME);
1429 MODULE_AUTHOR("Juha Yrjölä");