2 * linux/drivers/mmc/host/omap.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/timer.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/card.h>
26 #include <linux/clk.h>
27 #include <linux/scatterlist.h>
28 #include <linux/i2c/tps65010.h>
32 #include <asm/mach-types.h>
34 #include <asm/arch/board.h>
35 #include <asm/arch/mmc.h>
36 #include <asm/arch/gpio.h>
37 #include <asm/arch/dma.h>
38 #include <asm/arch/mux.h>
39 #include <asm/arch/fpga.h>
41 #define OMAP_MMC_REG_CMD 0x00
42 #define OMAP_MMC_REG_ARGL 0x04
43 #define OMAP_MMC_REG_ARGH 0x08
44 #define OMAP_MMC_REG_CON 0x0c
45 #define OMAP_MMC_REG_STAT 0x10
46 #define OMAP_MMC_REG_IE 0x14
47 #define OMAP_MMC_REG_CTO 0x18
48 #define OMAP_MMC_REG_DTO 0x1c
49 #define OMAP_MMC_REG_DATA 0x20
50 #define OMAP_MMC_REG_BLEN 0x24
51 #define OMAP_MMC_REG_NBLK 0x28
52 #define OMAP_MMC_REG_BUF 0x2c
53 #define OMAP_MMC_REG_SDIO 0x34
54 #define OMAP_MMC_REG_REV 0x3c
55 #define OMAP_MMC_REG_RSP0 0x40
56 #define OMAP_MMC_REG_RSP1 0x44
57 #define OMAP_MMC_REG_RSP2 0x48
58 #define OMAP_MMC_REG_RSP3 0x4c
59 #define OMAP_MMC_REG_RSP4 0x50
60 #define OMAP_MMC_REG_RSP5 0x54
61 #define OMAP_MMC_REG_RSP6 0x58
62 #define OMAP_MMC_REG_RSP7 0x5c
63 #define OMAP_MMC_REG_IOSR 0x60
64 #define OMAP_MMC_REG_SYSC 0x64
65 #define OMAP_MMC_REG_SYSS 0x68
67 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
68 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
69 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
70 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
71 #define OMAP_MMC_STAT_A_FULL (1 << 10)
72 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
73 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
74 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
75 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
76 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
77 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
78 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
79 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
81 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
82 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
87 #define OMAP_MMC_CMDTYPE_BC 0
88 #define OMAP_MMC_CMDTYPE_BCR 1
89 #define OMAP_MMC_CMDTYPE_AC 2
90 #define OMAP_MMC_CMDTYPE_ADTC 3
93 #define DRIVER_NAME "mmci-omap"
95 /* Specifies how often in millisecs to poll for card status changes
96 * when the cover switch is open */
97 #define OMAP_MMC_SWITCH_POLL_DELAY 500
101 struct mmc_omap_slot {
106 unsigned int fclk_freq;
109 struct work_struct switch_work;
110 struct timer_list switch_timer;
113 struct mmc_request *mrq;
114 struct mmc_omap_host *host;
115 struct mmc_host *mmc;
116 struct omap_mmc_slot_data *pdata;
119 struct mmc_omap_host {
122 struct mmc_request * mrq;
123 struct mmc_command * cmd;
124 struct mmc_data * data;
125 struct mmc_host * mmc;
127 unsigned char id; /* 16xx chips have 2 MMC blocks */
130 struct resource *mem_res;
131 void __iomem *virt_base;
132 unsigned int phys_base;
134 unsigned char bus_mode;
135 unsigned char hw_bus_mode;
140 u32 buffer_bytes_left;
141 u32 total_bytes_left;
144 unsigned brs_received:1, dma_done:1;
145 unsigned dma_is_read:1;
146 unsigned dma_in_use:1;
149 struct timer_list dma_timer;
154 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
155 struct mmc_omap_slot *current_slot;
156 spinlock_t slot_lock;
157 wait_queue_head_t slot_wq;
160 struct omap_mmc_platform_data *pdata;
163 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
165 struct mmc_omap_host *host = slot->host;
170 spin_lock_irqsave(&host->slot_lock, flags);
171 while (host->mmc != NULL) {
172 spin_unlock_irqrestore(&host->slot_lock, flags);
173 wait_event(host->slot_wq, host->mmc == NULL);
174 spin_lock_irqsave(&host->slot_lock, flags);
176 host->mmc = slot->mmc;
177 spin_unlock_irqrestore(&host->slot_lock, flags);
179 clk_enable(host->fclk);
180 if (host->current_slot != slot) {
181 if (host->pdata->switch_slot != NULL)
182 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
183 host->current_slot = slot;
186 /* Doing the dummy read here seems to work around some bug
187 * at least in OMAP24xx silicon where the command would not
188 * start after writing the CMD register. Sigh. */
189 OMAP_MMC_READ(host, CON);
191 OMAP_MMC_WRITE(host, CON, slot->saved_con);
194 static void mmc_omap_start_request(struct mmc_omap_host *host,
195 struct mmc_request *req);
197 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
199 struct mmc_omap_host *host = slot->host;
203 BUG_ON(slot == NULL || host->mmc == NULL);
204 clk_disable(host->fclk);
206 spin_lock_irqsave(&host->slot_lock, flags);
207 /* Check for any pending requests */
208 for (i = 0; i < host->nr_slots; i++) {
209 struct mmc_omap_slot *new_slot;
210 struct mmc_request *rq;
212 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
215 new_slot = host->slots[i];
216 /* The current slot should not have a request in queue */
217 BUG_ON(new_slot == host->current_slot);
219 host->mmc = new_slot->mmc;
220 spin_unlock_irqrestore(&host->slot_lock, flags);
221 mmc_omap_select_slot(new_slot, 1);
223 new_slot->mrq = NULL;
224 mmc_omap_start_request(host, rq);
229 wake_up(&host->slot_wq);
230 spin_unlock_irqrestore(&host->slot_lock, flags);
234 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
236 return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
240 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
243 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
244 struct mmc_omap_slot *slot = mmc_priv(mmc);
246 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
250 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
253 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
256 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
257 struct mmc_omap_slot *slot = mmc_priv(mmc);
259 return sprintf(buf, "%s\n", slot->pdata->name);
262 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
265 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
276 /* Our hardware needs to know exact type */
277 switch (mmc_resp_type(cmd)) {
282 /* resp 1, 1b, 6, 7 */
292 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
296 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
297 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
298 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
299 cmdtype = OMAP_MMC_CMDTYPE_BC;
300 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
301 cmdtype = OMAP_MMC_CMDTYPE_BCR;
303 cmdtype = OMAP_MMC_CMDTYPE_AC;
306 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
308 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
311 if (cmd->flags & MMC_RSP_BUSY)
314 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
317 OMAP_MMC_WRITE(host, CTO, 200);
318 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
319 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
320 OMAP_MMC_WRITE(host, IE,
321 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
322 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
323 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
324 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
325 OMAP_MMC_STAT_END_OF_DATA);
326 OMAP_MMC_WRITE(host, CMD, cmdreg);
330 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
333 enum dma_data_direction dma_data_dir;
335 BUG_ON(host->dma_ch < 0);
337 omap_stop_dma(host->dma_ch);
338 /* Release DMA channel lazily */
339 mod_timer(&host->dma_timer, jiffies + HZ);
340 if (data->flags & MMC_DATA_WRITE)
341 dma_data_dir = DMA_TO_DEVICE;
343 dma_data_dir = DMA_FROM_DEVICE;
344 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
349 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
351 if (host->dma_in_use)
352 mmc_omap_release_dma(host, data, data->error);
357 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
358 * dozens of requests until the card finishes writing data.
359 * It'd be cheaper to just wait till an EOFB interrupt arrives...
363 struct mmc_host *mmc;
367 mmc_omap_release_slot(host->current_slot);
368 mmc_request_done(mmc, data->mrq);
372 mmc_omap_start_command(host, data->stop);
376 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
381 if (host->dma_in_use)
382 mmc_omap_release_dma(host, data, 1);
387 ie = OMAP_MMC_READ(host, IE);
388 OMAP_MMC_WRITE(host, IE, 0);
389 OMAP_MMC_WRITE(host, CMD, 1 << 7);
391 while (!(OMAP_MMC_READ(host, STAT) & OMAP_MMC_STAT_END_OF_CMD)) {
397 OMAP_MMC_WRITE(host, STAT, OMAP_MMC_STAT_END_OF_CMD);
398 OMAP_MMC_WRITE(host, IE, ie);
402 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
407 if (!host->dma_in_use) {
408 mmc_omap_xfer_done(host, data);
412 spin_lock_irqsave(&host->dma_lock, flags);
416 host->brs_received = 1;
417 spin_unlock_irqrestore(&host->dma_lock, flags);
419 mmc_omap_xfer_done(host, data);
423 mmc_omap_dma_timer(unsigned long data)
425 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
427 BUG_ON(host->dma_ch < 0);
428 omap_free_dma(host->dma_ch);
433 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
439 spin_lock_irqsave(&host->dma_lock, flags);
440 if (host->brs_received)
444 spin_unlock_irqrestore(&host->dma_lock, flags);
446 mmc_omap_xfer_done(host, data);
450 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
454 if (cmd->flags & MMC_RSP_PRESENT) {
455 if (cmd->flags & MMC_RSP_136) {
456 /* response type 2 */
458 OMAP_MMC_READ(host, RSP0) |
459 (OMAP_MMC_READ(host, RSP1) << 16);
461 OMAP_MMC_READ(host, RSP2) |
462 (OMAP_MMC_READ(host, RSP3) << 16);
464 OMAP_MMC_READ(host, RSP4) |
465 (OMAP_MMC_READ(host, RSP5) << 16);
467 OMAP_MMC_READ(host, RSP6) |
468 (OMAP_MMC_READ(host, RSP7) << 16);
470 /* response types 1, 1b, 3, 4, 5, 6 */
472 OMAP_MMC_READ(host, RSP6) |
473 (OMAP_MMC_READ(host, RSP7) << 16);
477 if (host->data == NULL || cmd->error) {
478 struct mmc_host *mmc;
480 if (host->data != NULL)
481 mmc_omap_abort_xfer(host, host->data);
484 mmc_omap_release_slot(host->current_slot);
485 mmc_request_done(mmc, cmd->mrq);
491 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
493 struct scatterlist *sg;
495 sg = host->data->sg + host->sg_idx;
496 host->buffer_bytes_left = sg->length;
497 host->buffer = sg_virt(sg);
498 if (host->buffer_bytes_left > host->total_bytes_left)
499 host->buffer_bytes_left = host->total_bytes_left;
504 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
508 if (host->buffer_bytes_left == 0) {
510 BUG_ON(host->sg_idx == host->sg_len);
511 mmc_omap_sg_to_buf(host);
514 if (n > host->buffer_bytes_left)
515 n = host->buffer_bytes_left;
516 host->buffer_bytes_left -= n;
517 host->total_bytes_left -= n;
518 host->data->bytes_xfered += n;
521 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
523 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
527 static inline void mmc_omap_report_irq(u16 status)
529 static const char *mmc_omap_status_bits[] = {
530 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
531 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
535 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
536 if (status & (1 << i)) {
539 printk("%s", mmc_omap_status_bits[i]);
544 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
546 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
552 if (host->cmd == NULL && host->data == NULL) {
553 status = OMAP_MMC_READ(host, STAT);
554 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
556 OMAP_MMC_WRITE(host, STAT, status);
557 OMAP_MMC_WRITE(host, IE, 0);
566 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
567 OMAP_MMC_WRITE(host, STAT, status);
568 #ifdef CONFIG_MMC_DEBUG
569 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
570 status, host->cmd != NULL ? host->cmd->opcode : -1);
571 mmc_omap_report_irq(status);
574 if (host->total_bytes_left) {
575 if ((status & OMAP_MMC_STAT_A_FULL) ||
576 (status & OMAP_MMC_STAT_END_OF_DATA))
577 mmc_omap_xfer_data(host, 0);
578 if (status & OMAP_MMC_STAT_A_EMPTY)
579 mmc_omap_xfer_data(host, 1);
582 if (status & OMAP_MMC_STAT_END_OF_DATA) {
586 if (status & OMAP_MMC_STAT_DATA_TOUT) {
587 dev_dbg(mmc_dev(host->mmc), "data timeout\n");
589 host->data->error = -ETIMEDOUT;
594 if (status & OMAP_MMC_STAT_DATA_CRC) {
596 host->data->error = -EILSEQ;
597 dev_dbg(mmc_dev(host->mmc),
598 "data CRC error, bytes left %d\n",
599 host->total_bytes_left);
602 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
606 if (status & OMAP_MMC_STAT_CMD_TOUT) {
607 /* Timeouts are routine with some commands */
609 struct mmc_omap_slot *slot =
611 if (!mmc_omap_cover_is_open(slot))
612 dev_err(mmc_dev(host->mmc),
613 "command timeout, CMD %d\n",
615 host->cmd->error = -ETIMEDOUT;
620 if (status & OMAP_MMC_STAT_CMD_CRC) {
622 dev_err(mmc_dev(host->mmc),
623 "command CRC error (CMD%d, arg 0x%08x)\n",
624 host->cmd->opcode, host->cmd->arg);
625 host->cmd->error = -EILSEQ;
628 dev_err(mmc_dev(host->mmc),
629 "command CRC error without cmd?\n");
632 if (status & OMAP_MMC_STAT_CARD_ERR) {
633 dev_dbg(mmc_dev(host->mmc),
634 "ignoring card status error (CMD%d)\n",
640 * NOTE: On 1610 the END_OF_CMD may come too early when
643 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
644 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
650 mmc_omap_cmd_done(host, host->cmd);
653 mmc_omap_xfer_done(host, host->data);
654 else if (end_transfer)
655 mmc_omap_end_of_data(host, host->data);
660 void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed)
662 struct mmc_omap_host *host = dev_get_drvdata(dev);
664 BUG_ON(slot >= host->nr_slots);
666 /* Other subsystems can call in here before we're initialised. */
667 if (host->nr_slots == 0 || !host->slots[slot])
670 schedule_work(&host->slots[slot]->switch_work);
673 static void mmc_omap_switch_timer(unsigned long arg)
675 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
677 schedule_work(&slot->switch_work);
680 static void mmc_omap_cover_handler(struct work_struct *work)
682 struct mmc_omap_slot *slot = container_of(work, struct mmc_omap_slot,
686 cover_open = mmc_omap_cover_is_open(slot);
687 if (cover_open != slot->cover_open) {
688 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
689 slot->cover_open = cover_open;
690 dev_info(mmc_dev(slot->mmc), "cover is now %s\n",
691 cover_open ? "open" : "closed");
693 mmc_detect_change(slot->mmc, slot->id);
696 /* Prepare to transfer the next segment of a scatterlist */
698 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
700 int dma_ch = host->dma_ch;
701 unsigned long data_addr;
704 struct scatterlist *sg = &data->sg[host->sg_idx];
709 data_addr = host->phys_base + OMAP_MMC_REG_DATA;
711 count = sg_dma_len(sg);
713 if ((data->blocks == 1) && (count > data->blksz))
716 host->dma_len = count;
718 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
719 * Use 16 or 32 word frames when the blocksize is at least that large.
720 * Blocksize is usually 512 bytes; but not for some SD reads.
722 if (cpu_is_omap15xx() && frame > 32)
729 if (!(data->flags & MMC_DATA_WRITE)) {
730 buf = 0x800f | ((frame - 1) << 8);
732 if (cpu_class_is_omap1()) {
733 src_port = OMAP_DMA_PORT_TIPB;
734 dst_port = OMAP_DMA_PORT_EMIFF;
736 if (cpu_is_omap24xx())
737 sync_dev = OMAP24XX_DMA_MMC1_RX;
739 omap_set_dma_src_params(dma_ch, src_port,
740 OMAP_DMA_AMODE_CONSTANT,
742 omap_set_dma_dest_params(dma_ch, dst_port,
743 OMAP_DMA_AMODE_POST_INC,
744 sg_dma_address(sg), 0, 0);
745 omap_set_dma_dest_data_pack(dma_ch, 1);
746 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
748 buf = 0x0f80 | ((frame - 1) << 0);
750 if (cpu_class_is_omap1()) {
751 src_port = OMAP_DMA_PORT_EMIFF;
752 dst_port = OMAP_DMA_PORT_TIPB;
754 if (cpu_is_omap24xx())
755 sync_dev = OMAP24XX_DMA_MMC1_TX;
757 omap_set_dma_dest_params(dma_ch, dst_port,
758 OMAP_DMA_AMODE_CONSTANT,
760 omap_set_dma_src_params(dma_ch, src_port,
761 OMAP_DMA_AMODE_POST_INC,
762 sg_dma_address(sg), 0, 0);
763 omap_set_dma_src_data_pack(dma_ch, 1);
764 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
767 /* Max limit for DMA frame count is 0xffff */
768 BUG_ON(count > 0xffff);
770 OMAP_MMC_WRITE(host, BUF, buf);
771 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
772 frame, count, OMAP_DMA_SYNC_FRAME,
776 /* A scatterlist segment completed */
777 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
779 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
780 struct mmc_data *mmcdat = host->data;
782 if (unlikely(host->dma_ch < 0)) {
783 dev_err(mmc_dev(host->mmc),
784 "DMA callback while DMA not enabled\n");
787 /* FIXME: We really should do something to _handle_ the errors */
788 if (ch_status & OMAP1_DMA_TOUT_IRQ) {
789 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
792 if (ch_status & OMAP_DMA_DROP_IRQ) {
793 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
796 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
799 mmcdat->bytes_xfered += host->dma_len;
801 if (host->sg_idx < host->sg_len) {
802 mmc_omap_prepare_dma(host, host->data);
803 omap_start_dma(host->dma_ch);
805 mmc_omap_dma_done(host, host->data);
808 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
810 const char *dev_name;
811 int sync_dev, dma_ch, is_read, r;
813 is_read = !(data->flags & MMC_DATA_WRITE);
814 del_timer_sync(&host->dma_timer);
815 if (host->dma_ch >= 0) {
816 if (is_read == host->dma_is_read)
818 omap_free_dma(host->dma_ch);
824 sync_dev = OMAP_DMA_MMC_RX;
825 dev_name = "MMC1 read";
827 sync_dev = OMAP_DMA_MMC2_RX;
828 dev_name = "MMC2 read";
832 sync_dev = OMAP_DMA_MMC_TX;
833 dev_name = "MMC1 write";
835 sync_dev = OMAP_DMA_MMC2_TX;
836 dev_name = "MMC2 write";
839 r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
842 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
845 host->dma_ch = dma_ch;
846 host->dma_is_read = is_read;
851 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
855 reg = OMAP_MMC_READ(host, SDIO);
857 OMAP_MMC_WRITE(host, SDIO, reg);
858 /* Set maximum timeout */
859 OMAP_MMC_WRITE(host, CTO, 0xff);
862 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
864 unsigned int timeout, cycle_ns;
867 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
868 timeout = req->data->timeout_ns / cycle_ns;
869 timeout += req->data->timeout_clks;
871 /* Check if we need to use timeout multiplier register */
872 reg = OMAP_MMC_READ(host, SDIO);
873 if (timeout > 0xffff) {
878 OMAP_MMC_WRITE(host, SDIO, reg);
879 OMAP_MMC_WRITE(host, DTO, timeout);
883 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
885 struct mmc_data *data = req->data;
886 int i, use_dma, block_size;
891 OMAP_MMC_WRITE(host, BLEN, 0);
892 OMAP_MMC_WRITE(host, NBLK, 0);
893 OMAP_MMC_WRITE(host, BUF, 0);
894 host->dma_in_use = 0;
895 set_cmd_timeout(host, req);
899 block_size = data->blksz;
901 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
902 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
903 set_data_timeout(host, req);
905 /* cope with calling layer confusion; it issues "single
906 * block" writes using multi-block scatterlists.
908 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
910 /* Only do DMA for entire blocks */
911 use_dma = host->use_dma;
913 for (i = 0; i < sg_len; i++) {
914 if ((data->sg[i].length % block_size) != 0) {
923 if (mmc_omap_get_dma_channel(host, data) == 0) {
924 enum dma_data_direction dma_data_dir;
926 if (data->flags & MMC_DATA_WRITE)
927 dma_data_dir = DMA_TO_DEVICE;
929 dma_data_dir = DMA_FROM_DEVICE;
931 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
932 sg_len, dma_data_dir);
933 host->total_bytes_left = 0;
934 mmc_omap_prepare_dma(host, req->data);
935 host->brs_received = 0;
937 host->dma_in_use = 1;
944 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
945 host->total_bytes_left = data->blocks * block_size;
946 host->sg_len = sg_len;
947 mmc_omap_sg_to_buf(host);
948 host->dma_in_use = 0;
952 static void mmc_omap_start_request(struct mmc_omap_host *host,
953 struct mmc_request *req)
955 BUG_ON(host->mrq != NULL);
959 /* only touch fifo AFTER the controller readies it */
960 mmc_omap_prepare_data(host, req);
961 mmc_omap_start_command(host, req->cmd);
962 if (host->dma_in_use)
963 omap_start_dma(host->dma_ch);
964 BUG_ON(irqs_disabled());
967 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
969 struct mmc_omap_slot *slot = mmc_priv(mmc);
970 struct mmc_omap_host *host = slot->host;
973 spin_lock_irqsave(&host->slot_lock, flags);
974 if (host->mmc != NULL) {
975 BUG_ON(slot->mrq != NULL);
977 spin_unlock_irqrestore(&host->slot_lock, flags);
981 spin_unlock_irqrestore(&host->slot_lock, flags);
982 mmc_omap_select_slot(slot, 1);
983 mmc_omap_start_request(host, req);
986 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
989 struct mmc_omap_host *host;
993 if (slot->pdata->set_power != NULL)
994 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
997 if (cpu_is_omap24xx()) {
1001 w = OMAP_MMC_READ(host, CON);
1002 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1004 w = OMAP_MMC_READ(host, CON);
1005 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1010 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1012 struct mmc_omap_slot *slot = mmc_priv(mmc);
1013 struct mmc_omap_host *host = slot->host;
1014 int func_clk_rate = clk_get_rate(host->fclk);
1017 if (ios->clock == 0)
1020 dsor = func_clk_rate / ios->clock;
1024 if (func_clk_rate / dsor > ios->clock)
1030 slot->fclk_freq = func_clk_rate / dsor;
1032 if (ios->bus_width == MMC_BUS_WIDTH_4)
1038 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1040 struct mmc_omap_slot *slot = mmc_priv(mmc);
1041 struct mmc_omap_host *host = slot->host;
1044 dsor = mmc_omap_calc_divisor(mmc, ios);
1046 mmc_omap_select_slot(slot, 0);
1048 if (ios->vdd != slot->vdd)
1049 slot->vdd = ios->vdd;
1051 switch (ios->power_mode) {
1053 mmc_omap_set_power(slot, 0, ios->vdd);
1056 /* Cannot touch dsor yet, just power up MMC */
1057 mmc_omap_set_power(slot, 1, ios->vdd);
1064 if (slot->bus_mode != ios->bus_mode) {
1065 if (slot->pdata->set_bus_mode != NULL)
1066 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1068 slot->bus_mode = ios->bus_mode;
1071 /* On insanely high arm_per frequencies something sometimes
1072 * goes somehow out of sync, and the POW bit is not being set,
1073 * which results in the while loop below getting stuck.
1074 * Writing to the CON register twice seems to do the trick. */
1075 for (i = 0; i < 2; i++)
1076 OMAP_MMC_WRITE(host, CON, dsor);
1077 slot->saved_con = dsor;
1078 if (ios->power_mode == MMC_POWER_ON) {
1079 /* Send clock cycles, poll completion */
1080 OMAP_MMC_WRITE(host, IE, 0);
1081 OMAP_MMC_WRITE(host, STAT, 0xffff);
1082 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1083 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1084 OMAP_MMC_WRITE(host, STAT, 1);
1088 mmc_omap_release_slot(slot);
1091 static const struct mmc_host_ops mmc_omap_ops = {
1092 .request = mmc_omap_request,
1093 .set_ios = mmc_omap_set_ios,
1096 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1098 struct mmc_omap_slot *slot = NULL;
1099 struct mmc_host *mmc;
1102 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1106 slot = mmc_priv(mmc);
1110 slot->pdata = &host->pdata->slots[id];
1112 host->slots[id] = slot;
1114 mmc->caps = MMC_CAP_MULTIWRITE;
1115 if (host->pdata->conf.wire4)
1116 mmc->caps |= MMC_CAP_4_BIT_DATA;
1118 mmc->ops = &mmc_omap_ops;
1119 mmc->f_min = 400000;
1121 if (cpu_class_is_omap2())
1122 mmc->f_max = 48000000;
1124 mmc->f_max = 24000000;
1125 if (host->pdata->max_freq)
1126 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1127 mmc->ocr_avail = slot->pdata->ocr_mask;
1129 /* Use scatterlist DMA to reduce per-transfer costs.
1130 * NOTE max_seg_size assumption that small blocks aren't
1131 * normally used (except e.g. for reading SD registers).
1133 mmc->max_phys_segs = 32;
1134 mmc->max_hw_segs = 32;
1135 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1136 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1137 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1138 mmc->max_seg_size = mmc->max_req_size;
1140 r = mmc_add_host(mmc);
1142 goto err_remove_host;
1144 if (slot->pdata->name != NULL) {
1145 r = device_create_file(&mmc->class_dev,
1146 &dev_attr_slot_name);
1148 goto err_remove_host;
1151 if (slot->pdata->get_cover_state != NULL) {
1152 r = device_create_file(&mmc->class_dev,
1153 &dev_attr_cover_switch);
1155 goto err_remove_slot_name;
1157 INIT_WORK(&slot->switch_work, mmc_omap_cover_handler);
1158 init_timer(&slot->switch_timer);
1159 slot->switch_timer.function = mmc_omap_switch_timer;
1160 slot->switch_timer.data = (unsigned long) slot;
1161 schedule_work(&slot->switch_work);
1166 err_remove_slot_name:
1167 if (slot->pdata->name != NULL)
1168 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1170 mmc_remove_host(mmc);
1175 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1177 struct mmc_host *mmc = slot->mmc;
1179 if (slot->pdata->name != NULL)
1180 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1181 if (slot->pdata->get_cover_state != NULL)
1182 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1184 del_timer_sync(&slot->switch_timer);
1185 flush_scheduled_work();
1187 mmc_remove_host(mmc);
1191 static int __init mmc_omap_probe(struct platform_device *pdev)
1193 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1194 struct mmc_omap_host *host = NULL;
1195 struct resource *res;
1199 if (pdata == NULL) {
1200 dev_err(&pdev->dev, "platform data missing\n");
1203 if (pdata->nr_slots == 0) {
1204 dev_err(&pdev->dev, "no slots\n");
1208 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1209 irq = platform_get_irq(pdev, 0);
1210 if (res == NULL || irq < 0)
1213 res = request_mem_region(res->start, res->end - res->start + 1,
1218 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1221 goto err_free_mem_region;
1224 spin_lock_init(&host->dma_lock);
1225 init_timer(&host->dma_timer);
1226 spin_lock_init(&host->slot_lock);
1227 init_waitqueue_head(&host->slot_wq);
1229 host->dma_timer.function = mmc_omap_dma_timer;
1230 host->dma_timer.data = (unsigned long) host;
1232 host->pdata = pdata;
1233 host->dev = &pdev->dev;
1234 platform_set_drvdata(pdev, host);
1236 host->id = pdev->id;
1237 host->mem_res = res;
1244 host->phys_base = host->mem_res->start;
1245 host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1247 if (cpu_is_omap24xx()) {
1248 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1249 if (IS_ERR(host->iclk))
1250 goto err_free_mmc_host;
1251 clk_enable(host->iclk);
1254 if (!cpu_is_omap24xx())
1255 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1257 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1259 if (IS_ERR(host->fclk)) {
1260 ret = PTR_ERR(host->fclk);
1264 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1268 if (pdata->init != NULL) {
1269 ret = pdata->init(&pdev->dev);
1274 host->nr_slots = pdata->nr_slots;
1275 for (i = 0; i < pdata->nr_slots; i++) {
1276 ret = mmc_omap_new_slot(host, i);
1279 mmc_omap_remove_slot(host->slots[i]);
1281 goto err_plat_cleanup;
1289 pdata->cleanup(&pdev->dev);
1291 free_irq(host->irq, host);
1293 clk_put(host->fclk);
1295 if (host->iclk != NULL) {
1296 clk_disable(host->iclk);
1297 clk_put(host->iclk);
1301 err_free_mem_region:
1302 release_mem_region(res->start, res->end - res->start + 1);
1306 static int mmc_omap_remove(struct platform_device *pdev)
1308 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1311 platform_set_drvdata(pdev, NULL);
1313 BUG_ON(host == NULL);
1315 for (i = 0; i < host->nr_slots; i++)
1316 mmc_omap_remove_slot(host->slots[i]);
1318 if (host->pdata->cleanup)
1319 host->pdata->cleanup(&pdev->dev);
1321 if (host->iclk && !IS_ERR(host->iclk))
1322 clk_put(host->iclk);
1323 if (host->fclk && !IS_ERR(host->fclk))
1324 clk_put(host->fclk);
1326 release_mem_region(pdev->resource[0].start,
1327 pdev->resource[0].end - pdev->resource[0].start + 1);
1335 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1338 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1340 if (host == NULL || host->suspended)
1343 for (i = 0; i < host->nr_slots; i++) {
1344 struct mmc_omap_slot *slot;
1346 slot = host->slots[i];
1347 ret = mmc_suspend_host(slot->mmc, mesg);
1350 slot = host->slots[i];
1351 mmc_resume_host(slot->mmc);
1356 host->suspended = 1;
1360 static int mmc_omap_resume(struct platform_device *pdev)
1363 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1365 if (host == NULL || !host->suspended)
1368 for (i = 0; i < host->nr_slots; i++) {
1369 struct mmc_omap_slot *slot;
1370 slot = host->slots[i];
1371 ret = mmc_resume_host(slot->mmc);
1375 host->suspended = 0;
1380 #define mmc_omap_suspend NULL
1381 #define mmc_omap_resume NULL
1384 static struct platform_driver mmc_omap_driver = {
1385 .probe = mmc_omap_probe,
1386 .remove = mmc_omap_remove,
1387 .suspend = mmc_omap_suspend,
1388 .resume = mmc_omap_resume,
1390 .name = DRIVER_NAME,
1391 .owner = THIS_MODULE,
1395 static int __init mmc_omap_init(void)
1397 return platform_driver_register(&mmc_omap_driver);
1400 static void __exit mmc_omap_exit(void)
1402 platform_driver_unregister(&mmc_omap_driver);
1405 module_init(mmc_omap_init);
1406 module_exit(mmc_omap_exit);
1408 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1409 MODULE_LICENSE("GPL");
1410 MODULE_ALIAS("platform:" DRIVER_NAME);
1411 MODULE_AUTHOR("Juha Yrjölä");