drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/mmc.h>
  25 #include <linux/mmc/host.h>
  26 #include <linux/mmc/card.h>
  27 #include <linux/clk.h>
  28 #include <linux/scatterlist.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/gpio.h>
  36 #include <asm/arch/dma.h>
  37 #include <asm/arch/mux.h>
  38 #include <asm/arch/fpga.h>
  39 #include <asm/arch/tps65010.h>
  40 #include <asm/arch/board-sx1.h>
  41
  42 #define OMAP_MMC_REG_CMD        0x00
  43 #define OMAP_MMC_REG_ARGL       0x04
  44 #define OMAP_MMC_REG_ARGH       0x08
  45 #define OMAP_MMC_REG_CON        0x0c
  46 #define OMAP_MMC_REG_STAT       0x10
  47 #define OMAP_MMC_REG_IE         0x14
  48 #define OMAP_MMC_REG_CTO        0x18
  49 #define OMAP_MMC_REG_DTO        0x1c
  50 #define OMAP_MMC_REG_DATA       0x20
  51 #define OMAP_MMC_REG_BLEN       0x24
  52 #define OMAP_MMC_REG_NBLK       0x28
  53 #define OMAP_MMC_REG_BUF        0x2c
  54 #define OMAP_MMC_REG_SDIO       0x34
  55 #define OMAP_MMC_REG_REV        0x3c
  56 #define OMAP_MMC_REG_RSP0       0x40
  57 #define OMAP_MMC_REG_RSP1       0x44
  58 #define OMAP_MMC_REG_RSP2       0x48
  59 #define OMAP_MMC_REG_RSP3       0x4c
  60 #define OMAP_MMC_REG_RSP4       0x50
  61 #define OMAP_MMC_REG_RSP5       0x54
  62 #define OMAP_MMC_REG_RSP6       0x58
  63 #define OMAP_MMC_REG_RSP7       0x5c
  64 #define OMAP_MMC_REG_IOSR       0x60
  65 #define OMAP_MMC_REG_SYSC       0x64
  66 #define OMAP_MMC_REG_SYSS       0x68
  67
  68 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  69 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  70 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  71 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  72 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  73 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  74 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  75 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  76 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  77 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  78 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  79 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  80 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  81
  82 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  83 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  84
  85 /*
  86  * Command types
  87  */
  88 #define OMAP_MMC_CMDTYPE_BC     0
  89 #define OMAP_MMC_CMDTYPE_BCR    1
  90 #define OMAP_MMC_CMDTYPE_AC     2
  91 #define OMAP_MMC_CMDTYPE_ADTC   3
  92
  93
  94 #define DRIVER_NAME "mmci-omap"
  95
  96 /* Specifies how often in millisecs to poll for card status changes
  97  * when the cover switch is open */
  98 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  99
 100 struct mmc_omap_host {
 101         int                     initialized;
 102         int                     suspended;
 103         struct mmc_request *    mrq;
 104         struct mmc_command *    cmd;
 105         struct mmc_data *       data;
 106         struct mmc_host *       mmc;
 107         struct device *         dev;
 108         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 109         struct clk *            iclk;
 110         struct clk *            fclk;
 111         struct resource         *mem_res;
 112         void __iomem            *virt_base;
 113         unsigned int            phys_base;
 114         int                     irq;
 115         unsigned char           bus_mode;
 116         unsigned char           hw_bus_mode;
 117
 118         unsigned int            sg_len;
 119         int                     sg_idx;
 120         u16 *                   buffer;
 121         u32                     buffer_bytes_left;
 122         u32                     total_bytes_left;
 123
 124         unsigned                use_dma:1;
 125         unsigned                brs_received:1, dma_done:1;
 126         unsigned                dma_is_read:1;
 127         unsigned                dma_in_use:1;
 128         int                     dma_ch;
 129         spinlock_t              dma_lock;
 130         struct timer_list       dma_timer;
 131         unsigned                dma_len;
 132
 133         short                   power_pin;
 134         short                   wp_pin;
 135
 136         struct work_struct      switch_work;
 137         struct timer_list       switch_timer;
 138         int                     switch_last_state;
 139 };
 140
 141 static void
 142 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 143 {
 144         u32 cmdreg;
 145         u32 resptype;
 146         u32 cmdtype;
 147
 148         host->cmd = cmd;
 149
 150         resptype = 0;
 151         cmdtype = 0;
 152
 153         /* Our hardware needs to know exact type */
 154         switch (mmc_resp_type(cmd)) {
 155         case MMC_RSP_NONE:
 156                 break;
 157         case MMC_RSP_R1:
 158         case MMC_RSP_R1B:
 159                 /* resp 1, 1b, 6, 7 */
 160                 resptype = 1;
 161                 break;
 162         case MMC_RSP_R2:
 163                 resptype = 2;
 164                 break;
 165         case MMC_RSP_R3:
 166                 resptype = 3;
 167                 break;
 168         default:
 169                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 170                 break;
 171         }
 172
 173         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 174                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 175         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 176                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 177         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 178                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 179         } else {
 180                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 181         }
 182
 183         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 184
 185         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 186                 cmdreg |= 1 << 6;
 187
 188         if (cmd->flags & MMC_RSP_BUSY)
 189                 cmdreg |= 1 << 11;
 190
 191         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 192                 cmdreg |= 1 << 15;
 193
 194         clk_enable(host->fclk);
 195
 196         OMAP_MMC_WRITE(host, CTO, 200);
 197         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 198         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 199         OMAP_MMC_WRITE(host, IE,
 200                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 201                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 202                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 203                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 204                        OMAP_MMC_STAT_END_OF_DATA);
 205         OMAP_MMC_WRITE(host, CMD, cmdreg);
 206 }
 207
 208 static void
 209 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 210 {
 211         if (host->dma_in_use) {
 212                 enum dma_data_direction dma_data_dir;
 213
 214                 BUG_ON(host->dma_ch < 0);
 215                 if (data->error)
 216                         omap_stop_dma(host->dma_ch);
 217                 /* Release DMA channel lazily */
 218                 mod_timer(&host->dma_timer, jiffies + HZ);
 219                 if (data->flags & MMC_DATA_WRITE)
 220                         dma_data_dir = DMA_TO_DEVICE;
 221                 else
 222                         dma_data_dir = DMA_FROM_DEVICE;
 223                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 224                              dma_data_dir);
 225         }
 226         host->data = NULL;
 227         host->sg_len = 0;
 228         clk_disable(host->fclk);
 229
 230         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 231          * dozens of requests until the card finishes writing data.
 232          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 233          */
 234
 235         if (!data->stop) {
 236                 host->mrq = NULL;
 237                 mmc_request_done(host->mmc, data->mrq);
 238                 return;
 239         }
 240
 241         mmc_omap_start_command(host, data->stop);
 242 }
 243
 244 static void
 245 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 246 {
 247         unsigned long flags;
 248         int done;
 249
 250         if (!host->dma_in_use) {
 251                 mmc_omap_xfer_done(host, data);
 252                 return;
 253         }
 254         done = 0;
 255         spin_lock_irqsave(&host->dma_lock, flags);
 256         if (host->dma_done)
 257                 done = 1;
 258         else
 259                 host->brs_received = 1;
 260         spin_unlock_irqrestore(&host->dma_lock, flags);
 261         if (done)
 262                 mmc_omap_xfer_done(host, data);
 263 }
 264
 265 static void
 266 mmc_omap_dma_timer(unsigned long data)
 267 {
 268         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 269
 270         BUG_ON(host->dma_ch < 0);
 271         omap_free_dma(host->dma_ch);
 272         host->dma_ch = -1;
 273 }
 274
 275 static void
 276 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 277 {
 278         unsigned long flags;
 279         int done;
 280
 281         done = 0;
 282         spin_lock_irqsave(&host->dma_lock, flags);
 283         if (host->brs_received)
 284                 done = 1;
 285         else
 286                 host->dma_done = 1;
 287         spin_unlock_irqrestore(&host->dma_lock, flags);
 288         if (done)
 289                 mmc_omap_xfer_done(host, data);
 290 }
 291
 292 static void
 293 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 294 {
 295         host->cmd = NULL;
 296
 297         if (cmd->flags & MMC_RSP_PRESENT) {
 298                 if (cmd->flags & MMC_RSP_136) {
 299                         /* response type 2 */
 300                         cmd->resp[3] =
 301                                 OMAP_MMC_READ(host, RSP0) |
 302                                 (OMAP_MMC_READ(host, RSP1) << 16);
 303                         cmd->resp[2] =
 304                                 OMAP_MMC_READ(host, RSP2) |
 305                                 (OMAP_MMC_READ(host, RSP3) << 16);
 306                         cmd->resp[1] =
 307                                 OMAP_MMC_READ(host, RSP4) |
 308                                 (OMAP_MMC_READ(host, RSP5) << 16);
 309                         cmd->resp[0] =
 310                                 OMAP_MMC_READ(host, RSP6) |
 311                                 (OMAP_MMC_READ(host, RSP7) << 16);
 312                 } else {
 313                         /* response types 1, 1b, 3, 4, 5, 6 */
 314                         cmd->resp[0] =
 315                                 OMAP_MMC_READ(host, RSP6) |
 316                                 (OMAP_MMC_READ(host, RSP7) << 16);
 317                 }
 318         }
 319
 320         if (host->data == NULL || cmd->error) {
 321                 host->mrq = NULL;
 322                 clk_disable(host->fclk);
 323                 mmc_request_done(host->mmc, cmd->mrq);
 324         }
 325 }
 326
 327 /* PIO only */
 328 static void
 329 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 330 {
 331         struct scatterlist *sg;
 332
 333         sg = host->data->sg + host->sg_idx;
 334         host->buffer_bytes_left = sg->length;
 335         host->buffer = sg_virt(sg);
 336         if (host->buffer_bytes_left > host->total_bytes_left)
 337                 host->buffer_bytes_left = host->total_bytes_left;
 338 }
 339
 340 /* PIO only */
 341 static void
 342 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 343 {
 344         int n;
 345
 346         if (host->buffer_bytes_left == 0) {
 347                 host->sg_idx++;
 348                 BUG_ON(host->sg_idx == host->sg_len);
 349                 mmc_omap_sg_to_buf(host);
 350         }
 351         n = 64;
 352         if (n > host->buffer_bytes_left)
 353                 n = host->buffer_bytes_left;
 354         host->buffer_bytes_left -= n;
 355         host->total_bytes_left -= n;
 356         host->data->bytes_xfered += n;
 357
 358         if (write) {
 359                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 360         } else {
 361                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 362         }
 363 }
 364
 365 static inline void mmc_omap_report_irq(u16 status)
 366 {
 367         static const char *mmc_omap_status_bits[] = {
 368                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 369                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 370         };
 371         int i, c = 0;
 372
 373         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 374                 if (status & (1 << i)) {
 375                         if (c)
 376                                 printk(" ");
 377                         printk("%s", mmc_omap_status_bits[i]);
 378                         c++;
 379                 }
 380 }
 381
 382 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 383 {
 384         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 385         u16 status;
 386         int end_command;
 387         int end_transfer;
 388         int transfer_error;
 389
 390         if (host->cmd == NULL && host->data == NULL) {
 391                 status = OMAP_MMC_READ(host, STAT);
 392                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 393                 if (status != 0) {
 394                         OMAP_MMC_WRITE(host, STAT, status);
 395                         OMAP_MMC_WRITE(host, IE, 0);
 396                 }
 397                 return IRQ_HANDLED;
 398         }
 399
 400         end_command = 0;
 401         end_transfer = 0;
 402         transfer_error = 0;
 403
 404         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 405                 OMAP_MMC_WRITE(host, STAT, status);
 406 #ifdef CONFIG_MMC_DEBUG
 407                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 408                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 409                 mmc_omap_report_irq(status);
 410                 printk("\n");
 411 #endif
 412                 if (host->total_bytes_left) {
 413                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 414                             (status & OMAP_MMC_STAT_END_OF_DATA))
 415                                 mmc_omap_xfer_data(host, 0);
 416                         if (status & OMAP_MMC_STAT_A_EMPTY)
 417                                 mmc_omap_xfer_data(host, 1);
 418                 }
 419
 420                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 421                         end_transfer = 1;
 422                 }
 423
 424                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 425                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 426                         if (host->data) {
 427                                 host->data->error = -ETIMEDOUT;
 428                                 transfer_error = 1;
 429                         }
 430                 }
 431
 432                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 433                         if (host->data) {
 434                                 host->data->error = -EILSEQ;
 435                                 dev_dbg(mmc_dev(host->mmc),
 436                                          "data CRC error, bytes left %d\n",
 437                                         host->total_bytes_left);
 438                                 transfer_error = 1;
 439                         } else {
 440                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 441                         }
 442                 }
 443
 444                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 445                         /* Timeouts are routine with some commands */
 446                         if (host->cmd) {
 447                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 448                                                 host->cmd->opcode !=
 449                                                 MMC_SEND_OP_COND &&
 450                                                 host->cmd->opcode !=
 451                                                 MMC_APP_CMD)
 452                                         dev_err(mmc_dev(host->mmc),
 453                                                 "command timeout, CMD %d\n",
 454                                                 host->cmd->opcode);
 455                                 host->cmd->error = -ETIMEDOUT;
 456                                 end_command = 1;
 457                         }
 458                 }
 459
 460                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 461                         if (host->cmd) {
 462                                 dev_err(mmc_dev(host->mmc),
 463                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 464                                         host->cmd->opcode, host->cmd->arg);
 465                                 host->cmd->error = -EILSEQ;
 466                                 end_command = 1;
 467                         } else
 468                                 dev_err(mmc_dev(host->mmc),
 469                                         "command CRC error without cmd?\n");
 470                 }
 471
 472                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 473                         dev_dbg(mmc_dev(host->mmc),
 474                                 "ignoring card status error (CMD%d)\n",
 475                                 host->cmd->opcode);
 476                         end_command = 1;
 477                 }
 478
 479                 /*
 480                  * NOTE: On 1610 the END_OF_CMD may come too early when
 481                  * starting a write
 482                  */
 483                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 484                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 485                         end_command = 1;
 486                 }
 487         }
 488
 489         if (end_command) {
 490                 mmc_omap_cmd_done(host, host->cmd);
 491         }
 492         if (transfer_error)
 493                 mmc_omap_xfer_done(host, host->data);
 494         else if (end_transfer)
 495                 mmc_omap_end_of_data(host, host->data);
 496
 497         return IRQ_HANDLED;
 498 }
 499
 500 /* Prepare to transfer the next segment of a scatterlist */
 501 static void
 502 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 503 {
 504         int dma_ch = host->dma_ch;
 505         unsigned long data_addr;
 506         u16 buf, frame;
 507         u32 count;
 508         struct scatterlist *sg = &data->sg[host->sg_idx];
 509         int src_port = 0;
 510         int dst_port = 0;
 511         int sync_dev = 0;
 512
 513         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 514         frame = data->blksz;
 515         count = sg_dma_len(sg);
 516
 517         if ((data->blocks == 1) && (count > data->blksz))
 518                 count = frame;
 519
 520         host->dma_len = count;
 521
 522         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 523          * Use 16 or 32 word frames when the blocksize is at least that large.
 524          * Blocksize is usually 512 bytes; but not for some SD reads.
 525          */
 526         if (cpu_is_omap15xx() && frame > 32)
 527                 frame = 32;
 528         else if (frame > 64)
 529                 frame = 64;
 530         count /= frame;
 531         frame >>= 1;
 532
 533         if (!(data->flags & MMC_DATA_WRITE)) {
 534                 buf = 0x800f | ((frame - 1) << 8);
 535
 536                 if (cpu_class_is_omap1()) {
 537                         src_port = OMAP_DMA_PORT_TIPB;
 538                         dst_port = OMAP_DMA_PORT_EMIFF;
 539                 }
 540                 if (cpu_is_omap24xx())
 541                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 542
 543                 omap_set_dma_src_params(dma_ch, src_port,
 544                                         OMAP_DMA_AMODE_CONSTANT,
 545                                         data_addr, 0, 0);
 546                 omap_set_dma_dest_params(dma_ch, dst_port,
 547                                          OMAP_DMA_AMODE_POST_INC,
 548                                          sg_dma_address(sg), 0, 0);
 549                 omap_set_dma_dest_data_pack(dma_ch, 1);
 550                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 551         } else {
 552                 buf = 0x0f80 | ((frame - 1) << 0);
 553
 554                 if (cpu_class_is_omap1()) {
 555                         src_port = OMAP_DMA_PORT_EMIFF;
 556                         dst_port = OMAP_DMA_PORT_TIPB;
 557                 }
 558                 if (cpu_is_omap24xx())
 559                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 560
 561                 omap_set_dma_dest_params(dma_ch, dst_port,
 562                                          OMAP_DMA_AMODE_CONSTANT,
 563                                          data_addr, 0, 0);
 564                 omap_set_dma_src_params(dma_ch, src_port,
 565                                         OMAP_DMA_AMODE_POST_INC,
 566                                         sg_dma_address(sg), 0, 0);
 567                 omap_set_dma_src_data_pack(dma_ch, 1);
 568                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 569         }
 570
 571         /* Max limit for DMA frame count is 0xffff */
 572         BUG_ON(count > 0xffff);
 573
 574         OMAP_MMC_WRITE(host, BUF, buf);
 575         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 576                                      frame, count, OMAP_DMA_SYNC_FRAME,
 577                                      sync_dev, 0);
 578 }
 579
 580 /* A scatterlist segment completed */
 581 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 582 {
 583         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 584         struct mmc_data *mmcdat = host->data;
 585
 586         if (unlikely(host->dma_ch < 0)) {
 587                 dev_err(mmc_dev(host->mmc),
 588                         "DMA callback while DMA not enabled\n");
 589                 return;
 590         }
 591         /* FIXME: We really should do something to _handle_ the errors */
 592         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 593                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 594                 return;
 595         }
 596         if (ch_status & OMAP_DMA_DROP_IRQ) {
 597                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 598                 return;
 599         }
 600         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 601                 return;
 602         }
 603         mmcdat->bytes_xfered += host->dma_len;
 604         host->sg_idx++;
 605         if (host->sg_idx < host->sg_len) {
 606                 mmc_omap_prepare_dma(host, host->data);
 607                 omap_start_dma(host->dma_ch);
 608         } else
 609                 mmc_omap_dma_done(host, host->data);
 610 }
 611
 612 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 613 {
 614         const char *dev_name;
 615         int sync_dev, dma_ch, is_read, r;
 616
 617         is_read = !(data->flags & MMC_DATA_WRITE);
 618         del_timer_sync(&host->dma_timer);
 619         if (host->dma_ch >= 0) {
 620                 if (is_read == host->dma_is_read)
 621                         return 0;
 622                 omap_free_dma(host->dma_ch);
 623                 host->dma_ch = -1;
 624         }
 625
 626         if (is_read) {
 627                 if (host->id == 1) {
 628                         sync_dev = OMAP_DMA_MMC_RX;
 629                         dev_name = "MMC1 read";
 630                 } else {
 631                         sync_dev = OMAP_DMA_MMC2_RX;
 632                         dev_name = "MMC2 read";
 633                 }
 634         } else {
 635                 if (host->id == 1) {
 636                         sync_dev = OMAP_DMA_MMC_TX;
 637                         dev_name = "MMC1 write";
 638                 } else {
 639                         sync_dev = OMAP_DMA_MMC2_TX;
 640                         dev_name = "MMC2 write";
 641                 }
 642         }
 643         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 644                              host, &dma_ch);
 645         if (r != 0) {
 646                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 647                 return r;
 648         }
 649         host->dma_ch = dma_ch;
 650         host->dma_is_read = is_read;
 651
 652         return 0;
 653 }
 654
 655 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 656 {
 657         u16 reg;
 658
 659         reg = OMAP_MMC_READ(host, SDIO);
 660         reg &= ~(1 << 5);
 661         OMAP_MMC_WRITE(host, SDIO, reg);
 662         /* Set maximum timeout */
 663         OMAP_MMC_WRITE(host, CTO, 0xff);
 664 }
 665
 666 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 667 {
 668         int timeout;
 669         u16 reg;
 670
 671         /* Convert ns to clock cycles by assuming 20MHz frequency
 672          * 1 cycle at 20MHz = 500 ns
 673          */
 674         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 675
 676         /* Check if we need to use timeout multiplier register */
 677         reg = OMAP_MMC_READ(host, SDIO);
 678         if (timeout > 0xffff) {
 679                 reg |= (1 << 5);
 680                 timeout /= 1024;
 681         } else
 682                 reg &= ~(1 << 5);
 683         OMAP_MMC_WRITE(host, SDIO, reg);
 684         OMAP_MMC_WRITE(host, DTO, timeout);
 685 }
 686
 687 static void
 688 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 689 {
 690         struct mmc_data *data = req->data;
 691         int i, use_dma, block_size;
 692         unsigned sg_len;
 693
 694         host->data = data;
 695         if (data == NULL) {
 696                 OMAP_MMC_WRITE(host, BLEN, 0);
 697                 OMAP_MMC_WRITE(host, NBLK, 0);
 698                 OMAP_MMC_WRITE(host, BUF, 0);
 699                 host->dma_in_use = 0;
 700                 set_cmd_timeout(host, req);
 701                 return;
 702         }
 703
 704         block_size = data->blksz;
 705
 706         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 707         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 708         set_data_timeout(host, req);
 709
 710         /* cope with calling layer confusion; it issues "single
 711          * block" writes using multi-block scatterlists.
 712          */
 713         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 714
 715         /* Only do DMA for entire blocks */
 716         use_dma = host->use_dma;
 717         if (use_dma) {
 718                 for (i = 0; i < sg_len; i++) {
 719                         if ((data->sg[i].length % block_size) != 0) {
 720                                 use_dma = 0;
 721                                 break;
 722                         }
 723                 }
 724         }
 725
 726         host->sg_idx = 0;
 727         if (use_dma) {
 728                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 729                         enum dma_data_direction dma_data_dir;
 730
 731                         if (data->flags & MMC_DATA_WRITE)
 732                                 dma_data_dir = DMA_TO_DEVICE;
 733                         else
 734                                 dma_data_dir = DMA_FROM_DEVICE;
 735
 736                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 737                                                 sg_len, dma_data_dir);
 738                         host->total_bytes_left = 0;
 739                         mmc_omap_prepare_dma(host, req->data);
 740                         host->brs_received = 0;
 741                         host->dma_done = 0;
 742                         host->dma_in_use = 1;
 743                 } else
 744                         use_dma = 0;
 745         }
 746
 747         /* Revert to PIO? */
 748         if (!use_dma) {
 749                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 750                 host->total_bytes_left = data->blocks * block_size;
 751                 host->sg_len = sg_len;
 752                 mmc_omap_sg_to_buf(host);
 753                 host->dma_in_use = 0;
 754         }
 755 }
 756
 757 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 758 {
 759         struct mmc_omap_host *host = mmc_priv(mmc);
 760
 761         WARN_ON(host->mrq != NULL);
 762
 763         host->mrq = req;
 764
 765         /* only touch fifo AFTER the controller readies it */
 766         mmc_omap_prepare_data(host, req);
 767         mmc_omap_start_command(host, req->cmd);
 768         if (host->dma_in_use)
 769                 omap_start_dma(host->dma_ch);
 770 }
 771
 772 static void innovator_fpga_socket_power(int on)
 773 {
 774 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 775         if (on) {
 776                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 777                      OMAP1510_FPGA_POWER);
 778         } else {
 779                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 780                      OMAP1510_FPGA_POWER);
 781         }
 782 #endif
 783 }
 784
 785 /*
 786  * Turn the socket power on/off. Innovator uses FPGA, most boards
 787  * probably use GPIO.
 788  */
 789 static void mmc_omap_power(struct mmc_omap_host *host, int on)
 790 {
 791         if (machine_is_sx1())
 792                 sx1_setmmcpower(on);
 793         else if (on) {
 794                 if (machine_is_omap_innovator())
 795                         innovator_fpga_socket_power(1);
 796                 else if (machine_is_omap_h2())
 797                         tps65010_set_gpio_out_value(GPIO3, HIGH);
 798                 else if (machine_is_omap_h3())
 799                         /* GPIO 4 of TPS65010 sends SD_EN signal */
 800                         tps65010_set_gpio_out_value(GPIO4, HIGH);
 801                 else if (cpu_is_omap24xx()) {
 802                         u16 reg = OMAP_MMC_READ(host, CON);
 803                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
 804                 } else
 805                         if (host->power_pin >= 0)
 806                                 omap_set_gpio_dataout(host->power_pin, 1);
 807         } else {
 808                 if (machine_is_omap_innovator())
 809                         innovator_fpga_socket_power(0);
 810                 else if (machine_is_omap_h2())
 811                         tps65010_set_gpio_out_value(GPIO3, LOW);
 812                 else if (machine_is_omap_h3())
 813                         tps65010_set_gpio_out_value(GPIO4, LOW);
 814                 else if (cpu_is_omap24xx()) {
 815                         u16 reg = OMAP_MMC_READ(host, CON);
 816                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
 817                 } else
 818                         if (host->power_pin >= 0)
 819                                 omap_set_gpio_dataout(host->power_pin, 0);
 820         }
 821 }
 822
 823 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
 824 {
 825         struct mmc_omap_host *host = mmc_priv(mmc);
 826         int func_clk_rate = clk_get_rate(host->fclk);
 827         int dsor;
 828
 829         if (ios->clock == 0)
 830                 return 0;
 831
 832         dsor = func_clk_rate / ios->clock;
 833         if (dsor < 1)
 834                 dsor = 1;
 835
 836         if (func_clk_rate / dsor > ios->clock)
 837                 dsor++;
 838
 839         if (dsor > 250)
 840                 dsor = 250;
 841
 842         if (ios->bus_width == MMC_BUS_WIDTH_4)
 843                 dsor |= 1 << 15;
 844
 845         return dsor;
 846 }
 847
 848 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 849 {
 850         struct mmc_omap_host *host = mmc_priv(mmc);
 851         int dsor;
 852         int i;
 853
 854         dsor = mmc_omap_calc_divisor(mmc, ios);
 855         host->bus_mode = ios->bus_mode;
 856         host->hw_bus_mode = host->bus_mode;
 857
 858         switch (ios->power_mode) {
 859         case MMC_POWER_OFF:
 860                 mmc_omap_power(host, 0);
 861                 break;
 862         case MMC_POWER_UP:
 863                 /* Cannot touch dsor yet, just power up MMC */
 864                 mmc_omap_power(host, 1);
 865                 return;
 866         case MMC_POWER_ON:
 867                 dsor |= 1 << 11;
 868                 break;
 869         }
 870
 871         clk_enable(host->fclk);
 872
 873         /* On insanely high arm_per frequencies something sometimes
 874          * goes somehow out of sync, and the POW bit is not being set,
 875          * which results in the while loop below getting stuck.
 876          * Writing to the CON register twice seems to do the trick. */
 877         for (i = 0; i < 2; i++)
 878                 OMAP_MMC_WRITE(host, CON, dsor);
 879         if (ios->power_mode == MMC_POWER_ON) {
 880                 /* Send clock cycles, poll completion */
 881                 OMAP_MMC_WRITE(host, IE, 0);
 882                 OMAP_MMC_WRITE(host, STAT, 0xffff);
 883                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
 884                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
 885                 OMAP_MMC_WRITE(host, STAT, 1);
 886         }
 887         clk_disable(host->fclk);
 888 }
 889
 890 static int mmc_omap_get_ro(struct mmc_host *mmc)
 891 {
 892         struct mmc_omap_host *host = mmc_priv(mmc);
 893
 894         return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
 895 }
 896
 897 static const struct mmc_host_ops mmc_omap_ops = {
 898         .request        = mmc_omap_request,
 899         .set_ios        = mmc_omap_set_ios,
 900         .get_ro         = mmc_omap_get_ro,
 901 };
 902
 903 static int __init mmc_omap_probe(struct platform_device *pdev)
 904 {
 905         struct omap_mmc_conf *minfo = pdev->dev.platform_data;
 906         struct mmc_host *mmc;
 907         struct mmc_omap_host *host = NULL;
 908         struct resource *res;
 909         int ret = 0;
 910         int irq;
 911
 912         if (minfo == NULL) {
 913                 dev_err(&pdev->dev, "platform data missing\n");
 914                 return -ENXIO;
 915         }
 916
 917         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 918         irq = platform_get_irq(pdev, 0);
 919         if (res == NULL || irq < 0)
 920                 return -ENXIO;
 921
 922         res = request_mem_region(res->start, res->end - res->start + 1,
 923                                  pdev->name);
 924         if (res == NULL)
 925                 return -EBUSY;
 926
 927         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 928         if (mmc == NULL) {
 929                 ret = -ENOMEM;
 930                 goto err_free_mem_region;
 931         }
 932
 933         host = mmc_priv(mmc);
 934         host->mmc = mmc;
 935
 936         spin_lock_init(&host->dma_lock);
 937         init_timer(&host->dma_timer);
 938         host->dma_timer.function = mmc_omap_dma_timer;
 939         host->dma_timer.data = (unsigned long) host;
 940
 941         host->id = pdev->id;
 942         host->mem_res = res;
 943         host->irq = irq;
 944
 945         if (cpu_is_omap24xx()) {
 946                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
 947                 if (IS_ERR(host->iclk))
 948                         goto err_free_mmc_host;
 949                 clk_enable(host->iclk);
 950         }
 951
 952         if (!cpu_is_omap24xx())
 953                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
 954         else
 955                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
 956
 957         if (IS_ERR(host->fclk)) {
 958                 ret = PTR_ERR(host->fclk);
 959                 goto err_free_iclk;
 960         }
 961
 962         /* REVISIT:
 963          * Also, use minfo->cover to decide how to manage
 964          * the card detect sensing.
 965          */
 966         host->power_pin = minfo->power_pin;
 967         host->wp_pin = minfo->wp_pin;
 968         host->use_dma = 1;
 969         host->dma_ch = -1;
 970
 971         host->irq = irq;
 972         host->phys_base = host->mem_res->start;
 973         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
 974
 975         mmc->ops = &mmc_omap_ops;
 976         mmc->f_min = 400000;
 977         mmc->f_max = 24000000;
 978         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 979         mmc->caps = MMC_CAP_MULTIWRITE;
 980
 981         if (minfo->wire4)
 982                  mmc->caps |= MMC_CAP_4_BIT_DATA;
 983
 984         /* Use scatterlist DMA to reduce per-transfer costs.
 985          * NOTE max_seg_size assumption that small blocks aren't
 986          * normally used (except e.g. for reading SD registers).
 987          */
 988         mmc->max_phys_segs = 32;
 989         mmc->max_hw_segs = 32;
 990         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
 991         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
 992         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 993         mmc->max_seg_size = mmc->max_req_size;
 994
 995         if (host->power_pin >= 0) {
 996                 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
 997                         dev_err(mmc_dev(host->mmc),
 998                                 "Unable to get GPIO pin for MMC power\n");
 999                         goto err_free_fclk;
1000                 }
1001                 omap_set_gpio_direction(host->power_pin, 0);
1002         }
1003
1004         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1005         if (ret)
1006                 goto err_free_power_gpio;
1007
1008         host->dev = &pdev->dev;
1009         platform_set_drvdata(pdev, host);
1010
1011         mmc_add_host(mmc);
1012
1013         return 0;
1014
1015         /* FIXME: Free other resources too. */
1016         if (host) {
1017                 if (host->iclk && !IS_ERR(host->iclk))
1018                         clk_put(host->iclk);
1019                 if (host->fclk && !IS_ERR(host->fclk))
1020                         clk_put(host->fclk);
1021                 mmc_free_host(host->mmc);
1022         }
1023 err_free_power_gpio:
1024         if (host->power_pin >= 0)
1025                 omap_free_gpio(host->power_pin);
1026 err_free_fclk:
1027         clk_put(host->fclk);
1028 err_free_iclk:
1029         if (host->iclk != NULL) {
1030                 clk_disable(host->iclk);
1031                 clk_put(host->iclk);
1032         }
1033 err_free_mmc_host:
1034         mmc_free_host(host->mmc);
1035 err_free_mem_region:
1036         release_mem_region(res->start, res->end - res->start + 1);
1037         return ret;
1038 }
1039
1040 static int mmc_omap_remove(struct platform_device *pdev)
1041 {
1042         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1043
1044         platform_set_drvdata(pdev, NULL);
1045
1046         BUG_ON(host == NULL);
1047
1048         mmc_remove_host(host->mmc);
1049         free_irq(host->irq, host);
1050
1051         if (host->power_pin >= 0)
1052                 omap_free_gpio(host->power_pin);
1053         if (host->iclk && !IS_ERR(host->iclk))
1054                 clk_put(host->iclk);
1055         if (host->fclk && !IS_ERR(host->fclk))
1056                 clk_put(host->fclk);
1057
1058         release_mem_region(pdev->resource[0].start,
1059                            pdev->resource[0].end - pdev->resource[0].start + 1);
1060
1061         mmc_free_host(host->mmc);
1062
1063         return 0;
1064 }
1065
1066 #ifdef CONFIG_PM
1067 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1068 {
1069         int ret = 0;
1070         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1071
1072         if (host && host->suspended)
1073                 return 0;
1074
1075         if (host) {
1076                 ret = mmc_suspend_host(host->mmc, mesg);
1077                 if (ret == 0)
1078                         host->suspended = 1;
1079         }
1080         return ret;
1081 }
1082
1083 static int mmc_omap_resume(struct platform_device *pdev)
1084 {
1085         int ret = 0;
1086         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1087
1088         if (host && !host->suspended)
1089                 return 0;
1090
1091         if (host) {
1092                 ret = mmc_resume_host(host->mmc);
1093                 if (ret == 0)
1094                         host->suspended = 0;
1095         }
1096
1097         return ret;
1098 }
1099 #else
1100 #define mmc_omap_suspend        NULL
1101 #define mmc_omap_resume         NULL
1102 #endif
1103
1104 static struct platform_driver mmc_omap_driver = {
1105         .probe          = mmc_omap_probe,
1106         .remove         = mmc_omap_remove,
1107         .suspend        = mmc_omap_suspend,
1108         .resume         = mmc_omap_resume,
1109         .driver         = {
1110                 .name   = DRIVER_NAME,
1111         },
1112 };
1113
1114 static int __init mmc_omap_init(void)
1115 {
1116         return platform_driver_register(&mmc_omap_driver);
1117 }
1118
1119 static void __exit mmc_omap_exit(void)
1120 {
1121         platform_driver_unregister(&mmc_omap_driver);
1122 }
1123
1124 module_init(mmc_omap_init);
1125 module_exit(mmc_omap_exit);
1126
1127 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1128 MODULE_LICENSE("GPL");
1129 MODULE_ALIAS(DRIVER_NAME);
1130 MODULE_AUTHOR("Juha Yrjölä");