drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/clk.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/i2c/tps65010.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/gpio.h>
  36 #include <asm/arch/dma.h>
  37 #include <asm/arch/mux.h>
  38 #include <asm/arch/fpga.h>
  39
  40 #define OMAP_MMC_REG_CMD        0x00
  41 #define OMAP_MMC_REG_ARGL       0x04
  42 #define OMAP_MMC_REG_ARGH       0x08
  43 #define OMAP_MMC_REG_CON        0x0c
  44 #define OMAP_MMC_REG_STAT       0x10
  45 #define OMAP_MMC_REG_IE         0x14
  46 #define OMAP_MMC_REG_CTO        0x18
  47 #define OMAP_MMC_REG_DTO        0x1c
  48 #define OMAP_MMC_REG_DATA       0x20
  49 #define OMAP_MMC_REG_BLEN       0x24
  50 #define OMAP_MMC_REG_NBLK       0x28
  51 #define OMAP_MMC_REG_BUF        0x2c
  52 #define OMAP_MMC_REG_SDIO       0x34
  53 #define OMAP_MMC_REG_REV        0x3c
  54 #define OMAP_MMC_REG_RSP0       0x40
  55 #define OMAP_MMC_REG_RSP1       0x44
  56 #define OMAP_MMC_REG_RSP2       0x48
  57 #define OMAP_MMC_REG_RSP3       0x4c
  58 #define OMAP_MMC_REG_RSP4       0x50
  59 #define OMAP_MMC_REG_RSP5       0x54
  60 #define OMAP_MMC_REG_RSP6       0x58
  61 #define OMAP_MMC_REG_RSP7       0x5c
  62 #define OMAP_MMC_REG_IOSR       0x60
  63 #define OMAP_MMC_REG_SYSC       0x64
  64 #define OMAP_MMC_REG_SYSS       0x68
  65
  66 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  67 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  68 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  69 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  70 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  71 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  72 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  73 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  74 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  75 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  76 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  77 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  78 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  79
  80 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  81 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  82
  83 /*
  84  * Command types
  85  */
  86 #define OMAP_MMC_CMDTYPE_BC     0
  87 #define OMAP_MMC_CMDTYPE_BCR    1
  88 #define OMAP_MMC_CMDTYPE_AC     2
  89 #define OMAP_MMC_CMDTYPE_ADTC   3
  90
  91
  92 #define DRIVER_NAME "mmci-omap"
  93
  94 /* Specifies how often in millisecs to poll for card status changes
  95  * when the cover switch is open */
  96 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  97
  98 struct mmc_omap_host {
  99         int                     initialized;
 100         int                     suspended;
 101         struct mmc_request *    mrq;
 102         struct mmc_command *    cmd;
 103         struct mmc_data *       data;
 104         struct mmc_host *       mmc;
 105         struct device *         dev;
 106         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 107         struct clk *            iclk;
 108         struct clk *            fclk;
 109         struct resource         *mem_res;
 110         void __iomem            *virt_base;
 111         unsigned int            phys_base;
 112         int                     irq;
 113         unsigned char           bus_mode;
 114         unsigned char           hw_bus_mode;
 115
 116         unsigned int            sg_len;
 117         int                     sg_idx;
 118         u16 *                   buffer;
 119         u32                     buffer_bytes_left;
 120         u32                     total_bytes_left;
 121
 122         unsigned                use_dma:1;
 123         unsigned                brs_received:1, dma_done:1;
 124         unsigned                dma_is_read:1;
 125         unsigned                dma_in_use:1;
 126         int                     dma_ch;
 127         spinlock_t              dma_lock;
 128         struct timer_list       dma_timer;
 129         unsigned                dma_len;
 130
 131         short                   power_pin;
 132         short                   wp_pin;
 133
 134         struct work_struct      switch_work;
 135         struct timer_list       switch_timer;
 136         int                     switch_last_state;
 137 };
 138
 139 static void
 140 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 141 {
 142         u32 cmdreg;
 143         u32 resptype;
 144         u32 cmdtype;
 145
 146         host->cmd = cmd;
 147
 148         resptype = 0;
 149         cmdtype = 0;
 150
 151         /* Our hardware needs to know exact type */
 152         switch (mmc_resp_type(cmd)) {
 153         case MMC_RSP_NONE:
 154                 break;
 155         case MMC_RSP_R1:
 156         case MMC_RSP_R1B:
 157                 /* resp 1, 1b, 6, 7 */
 158                 resptype = 1;
 159                 break;
 160         case MMC_RSP_R2:
 161                 resptype = 2;
 162                 break;
 163         case MMC_RSP_R3:
 164                 resptype = 3;
 165                 break;
 166         default:
 167                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 168                 break;
 169         }
 170
 171         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 172                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 173         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 174                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 175         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 176                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 177         } else {
 178                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 179         }
 180
 181         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 182
 183         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 184                 cmdreg |= 1 << 6;
 185
 186         if (cmd->flags & MMC_RSP_BUSY)
 187                 cmdreg |= 1 << 11;
 188
 189         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 190                 cmdreg |= 1 << 15;
 191
 192         clk_enable(host->fclk);
 193
 194         OMAP_MMC_WRITE(host, CTO, 200);
 195         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 196         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 197         OMAP_MMC_WRITE(host, IE,
 198                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 199                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 200                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 201                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 202                        OMAP_MMC_STAT_END_OF_DATA);
 203         OMAP_MMC_WRITE(host, CMD, cmdreg);
 204 }
 205
 206 static void
 207 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 208 {
 209         if (host->dma_in_use) {
 210                 enum dma_data_direction dma_data_dir;
 211
 212                 BUG_ON(host->dma_ch < 0);
 213                 if (data->error)
 214                         omap_stop_dma(host->dma_ch);
 215                 /* Release DMA channel lazily */
 216                 mod_timer(&host->dma_timer, jiffies + HZ);
 217                 if (data->flags & MMC_DATA_WRITE)
 218                         dma_data_dir = DMA_TO_DEVICE;
 219                 else
 220                         dma_data_dir = DMA_FROM_DEVICE;
 221                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 222                              dma_data_dir);
 223         }
 224         host->data = NULL;
 225         host->sg_len = 0;
 226         clk_disable(host->fclk);
 227
 228         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 229          * dozens of requests until the card finishes writing data.
 230          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 231          */
 232
 233         if (!data->stop) {
 234                 host->mrq = NULL;
 235                 mmc_request_done(host->mmc, data->mrq);
 236                 return;
 237         }
 238
 239         mmc_omap_start_command(host, data->stop);
 240 }
 241
 242 static void
 243 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 244 {
 245         unsigned long flags;
 246         int done;
 247
 248         if (!host->dma_in_use) {
 249                 mmc_omap_xfer_done(host, data);
 250                 return;
 251         }
 252         done = 0;
 253         spin_lock_irqsave(&host->dma_lock, flags);
 254         if (host->dma_done)
 255                 done = 1;
 256         else
 257                 host->brs_received = 1;
 258         spin_unlock_irqrestore(&host->dma_lock, flags);
 259         if (done)
 260                 mmc_omap_xfer_done(host, data);
 261 }
 262
 263 static void
 264 mmc_omap_dma_timer(unsigned long data)
 265 {
 266         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 267
 268         BUG_ON(host->dma_ch < 0);
 269         omap_free_dma(host->dma_ch);
 270         host->dma_ch = -1;
 271 }
 272
 273 static void
 274 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 275 {
 276         unsigned long flags;
 277         int done;
 278
 279         done = 0;
 280         spin_lock_irqsave(&host->dma_lock, flags);
 281         if (host->brs_received)
 282                 done = 1;
 283         else
 284                 host->dma_done = 1;
 285         spin_unlock_irqrestore(&host->dma_lock, flags);
 286         if (done)
 287                 mmc_omap_xfer_done(host, data);
 288 }
 289
 290 static void
 291 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 292 {
 293         host->cmd = NULL;
 294
 295         if (cmd->flags & MMC_RSP_PRESENT) {
 296                 if (cmd->flags & MMC_RSP_136) {
 297                         /* response type 2 */
 298                         cmd->resp[3] =
 299                                 OMAP_MMC_READ(host, RSP0) |
 300                                 (OMAP_MMC_READ(host, RSP1) << 16);
 301                         cmd->resp[2] =
 302                                 OMAP_MMC_READ(host, RSP2) |
 303                                 (OMAP_MMC_READ(host, RSP3) << 16);
 304                         cmd->resp[1] =
 305                                 OMAP_MMC_READ(host, RSP4) |
 306                                 (OMAP_MMC_READ(host, RSP5) << 16);
 307                         cmd->resp[0] =
 308                                 OMAP_MMC_READ(host, RSP6) |
 309                                 (OMAP_MMC_READ(host, RSP7) << 16);
 310                 } else {
 311                         /* response types 1, 1b, 3, 4, 5, 6 */
 312                         cmd->resp[0] =
 313                                 OMAP_MMC_READ(host, RSP6) |
 314                                 (OMAP_MMC_READ(host, RSP7) << 16);
 315                 }
 316         }
 317
 318         if (host->data == NULL || cmd->error) {
 319                 host->mrq = NULL;
 320                 clk_disable(host->fclk);
 321                 mmc_request_done(host->mmc, cmd->mrq);
 322         }
 323 }
 324
 325 /* PIO only */
 326 static void
 327 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 328 {
 329         struct scatterlist *sg;
 330
 331         sg = host->data->sg + host->sg_idx;
 332         host->buffer_bytes_left = sg->length;
 333         host->buffer = sg_virt(sg);
 334         if (host->buffer_bytes_left > host->total_bytes_left)
 335                 host->buffer_bytes_left = host->total_bytes_left;
 336 }
 337
 338 /* PIO only */
 339 static void
 340 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 341 {
 342         int n;
 343
 344         if (host->buffer_bytes_left == 0) {
 345                 host->sg_idx++;
 346                 BUG_ON(host->sg_idx == host->sg_len);
 347                 mmc_omap_sg_to_buf(host);
 348         }
 349         n = 64;
 350         if (n > host->buffer_bytes_left)
 351                 n = host->buffer_bytes_left;
 352         host->buffer_bytes_left -= n;
 353         host->total_bytes_left -= n;
 354         host->data->bytes_xfered += n;
 355
 356         if (write) {
 357                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 358         } else {
 359                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 360         }
 361 }
 362
 363 static inline void mmc_omap_report_irq(u16 status)
 364 {
 365         static const char *mmc_omap_status_bits[] = {
 366                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 367                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 368         };
 369         int i, c = 0;
 370
 371         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 372                 if (status & (1 << i)) {
 373                         if (c)
 374                                 printk(" ");
 375                         printk("%s", mmc_omap_status_bits[i]);
 376                         c++;
 377                 }
 378 }
 379
 380 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 381 {
 382         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 383         u16 status;
 384         int end_command;
 385         int end_transfer;
 386         int transfer_error;
 387
 388         if (host->cmd == NULL && host->data == NULL) {
 389                 status = OMAP_MMC_READ(host, STAT);
 390                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 391                 if (status != 0) {
 392                         OMAP_MMC_WRITE(host, STAT, status);
 393                         OMAP_MMC_WRITE(host, IE, 0);
 394                 }
 395                 return IRQ_HANDLED;
 396         }
 397
 398         end_command = 0;
 399         end_transfer = 0;
 400         transfer_error = 0;
 401
 402         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 403                 OMAP_MMC_WRITE(host, STAT, status);
 404 #ifdef CONFIG_MMC_DEBUG
 405                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 406                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 407                 mmc_omap_report_irq(status);
 408                 printk("\n");
 409 #endif
 410                 if (host->total_bytes_left) {
 411                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 412                             (status & OMAP_MMC_STAT_END_OF_DATA))
 413                                 mmc_omap_xfer_data(host, 0);
 414                         if (status & OMAP_MMC_STAT_A_EMPTY)
 415                                 mmc_omap_xfer_data(host, 1);
 416                 }
 417
 418                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 419                         end_transfer = 1;
 420                 }
 421
 422                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 423                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 424                         if (host->data) {
 425                                 host->data->error = -ETIMEDOUT;
 426                                 transfer_error = 1;
 427                         }
 428                 }
 429
 430                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 431                         if (host->data) {
 432                                 host->data->error = -EILSEQ;
 433                                 dev_dbg(mmc_dev(host->mmc),
 434                                          "data CRC error, bytes left %d\n",
 435                                         host->total_bytes_left);
 436                                 transfer_error = 1;
 437                         } else {
 438                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 439                         }
 440                 }
 441
 442                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 443                         /* Timeouts are routine with some commands */
 444                         if (host->cmd) {
 445                                 dev_err(mmc_dev(host->mmc),
 446                                         "command timeout, CMD %d\n",
 447                                         host->cmd->opcode);
 448                                 host->cmd->error = -ETIMEDOUT;
 449                                 end_command = 1;
 450                         }
 451                 }
 452
 453                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 454                         if (host->cmd) {
 455                                 dev_err(mmc_dev(host->mmc),
 456                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 457                                         host->cmd->opcode, host->cmd->arg);
 458                                 host->cmd->error = -EILSEQ;
 459                                 end_command = 1;
 460                         } else
 461                                 dev_err(mmc_dev(host->mmc),
 462                                         "command CRC error without cmd?\n");
 463                 }
 464
 465                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 466                         dev_dbg(mmc_dev(host->mmc),
 467                                 "ignoring card status error (CMD%d)\n",
 468                                 host->cmd->opcode);
 469                         end_command = 1;
 470                 }
 471
 472                 /*
 473                  * NOTE: On 1610 the END_OF_CMD may come too early when
 474                  * starting a write
 475                  */
 476                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 477                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 478                         end_command = 1;
 479                 }
 480         }
 481
 482         if (end_command) {
 483                 mmc_omap_cmd_done(host, host->cmd);
 484         }
 485         if (transfer_error)
 486                 mmc_omap_xfer_done(host, host->data);
 487         else if (end_transfer)
 488                 mmc_omap_end_of_data(host, host->data);
 489
 490         return IRQ_HANDLED;
 491 }
 492
 493 /* Prepare to transfer the next segment of a scatterlist */
 494 static void
 495 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 496 {
 497         int dma_ch = host->dma_ch;
 498         unsigned long data_addr;
 499         u16 buf, frame;
 500         u32 count;
 501         struct scatterlist *sg = &data->sg[host->sg_idx];
 502         int src_port = 0;
 503         int dst_port = 0;
 504         int sync_dev = 0;
 505
 506         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 507         frame = data->blksz;
 508         count = sg_dma_len(sg);
 509
 510         if ((data->blocks == 1) && (count > data->blksz))
 511                 count = frame;
 512
 513         host->dma_len = count;
 514
 515         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 516          * Use 16 or 32 word frames when the blocksize is at least that large.
 517          * Blocksize is usually 512 bytes; but not for some SD reads.
 518          */
 519         if (cpu_is_omap15xx() && frame > 32)
 520                 frame = 32;
 521         else if (frame > 64)
 522                 frame = 64;
 523         count /= frame;
 524         frame >>= 1;
 525
 526         if (!(data->flags & MMC_DATA_WRITE)) {
 527                 buf = 0x800f | ((frame - 1) << 8);
 528
 529                 if (cpu_class_is_omap1()) {
 530                         src_port = OMAP_DMA_PORT_TIPB;
 531                         dst_port = OMAP_DMA_PORT_EMIFF;
 532                 }
 533                 if (cpu_is_omap24xx())
 534                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 535
 536                 omap_set_dma_src_params(dma_ch, src_port,
 537                                         OMAP_DMA_AMODE_CONSTANT,
 538                                         data_addr, 0, 0);
 539                 omap_set_dma_dest_params(dma_ch, dst_port,
 540                                          OMAP_DMA_AMODE_POST_INC,
 541                                          sg_dma_address(sg), 0, 0);
 542                 omap_set_dma_dest_data_pack(dma_ch, 1);
 543                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 544         } else {
 545                 buf = 0x0f80 | ((frame - 1) << 0);
 546
 547                 if (cpu_class_is_omap1()) {
 548                         src_port = OMAP_DMA_PORT_EMIFF;
 549                         dst_port = OMAP_DMA_PORT_TIPB;
 550                 }
 551                 if (cpu_is_omap24xx())
 552                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 553
 554                 omap_set_dma_dest_params(dma_ch, dst_port,
 555                                          OMAP_DMA_AMODE_CONSTANT,
 556                                          data_addr, 0, 0);
 557                 omap_set_dma_src_params(dma_ch, src_port,
 558                                         OMAP_DMA_AMODE_POST_INC,
 559                                         sg_dma_address(sg), 0, 0);
 560                 omap_set_dma_src_data_pack(dma_ch, 1);
 561                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 562         }
 563
 564         /* Max limit for DMA frame count is 0xffff */
 565         BUG_ON(count > 0xffff);
 566
 567         OMAP_MMC_WRITE(host, BUF, buf);
 568         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 569                                      frame, count, OMAP_DMA_SYNC_FRAME,
 570                                      sync_dev, 0);
 571 }
 572
 573 /* A scatterlist segment completed */
 574 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 575 {
 576         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 577         struct mmc_data *mmcdat = host->data;
 578
 579         if (unlikely(host->dma_ch < 0)) {
 580                 dev_err(mmc_dev(host->mmc),
 581                         "DMA callback while DMA not enabled\n");
 582                 return;
 583         }
 584         /* FIXME: We really should do something to _handle_ the errors */
 585         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 586                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 587                 return;
 588         }
 589         if (ch_status & OMAP_DMA_DROP_IRQ) {
 590                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 591                 return;
 592         }
 593         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 594                 return;
 595         }
 596         mmcdat->bytes_xfered += host->dma_len;
 597         host->sg_idx++;
 598         if (host->sg_idx < host->sg_len) {
 599                 mmc_omap_prepare_dma(host, host->data);
 600                 omap_start_dma(host->dma_ch);
 601         } else
 602                 mmc_omap_dma_done(host, host->data);
 603 }
 604
 605 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 606 {
 607         const char *dev_name;
 608         int sync_dev, dma_ch, is_read, r;
 609
 610         is_read = !(data->flags & MMC_DATA_WRITE);
 611         del_timer_sync(&host->dma_timer);
 612         if (host->dma_ch >= 0) {
 613                 if (is_read == host->dma_is_read)
 614                         return 0;
 615                 omap_free_dma(host->dma_ch);
 616                 host->dma_ch = -1;
 617         }
 618
 619         if (is_read) {
 620                 if (host->id == 1) {
 621                         sync_dev = OMAP_DMA_MMC_RX;
 622                         dev_name = "MMC1 read";
 623                 } else {
 624                         sync_dev = OMAP_DMA_MMC2_RX;
 625                         dev_name = "MMC2 read";
 626                 }
 627         } else {
 628                 if (host->id == 1) {
 629                         sync_dev = OMAP_DMA_MMC_TX;
 630                         dev_name = "MMC1 write";
 631                 } else {
 632                         sync_dev = OMAP_DMA_MMC2_TX;
 633                         dev_name = "MMC2 write";
 634                 }
 635         }
 636         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 637                              host, &dma_ch);
 638         if (r != 0) {
 639                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 640                 return r;
 641         }
 642         host->dma_ch = dma_ch;
 643         host->dma_is_read = is_read;
 644
 645         return 0;
 646 }
 647
 648 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 649 {
 650         u16 reg;
 651
 652         reg = OMAP_MMC_READ(host, SDIO);
 653         reg &= ~(1 << 5);
 654         OMAP_MMC_WRITE(host, SDIO, reg);
 655         /* Set maximum timeout */
 656         OMAP_MMC_WRITE(host, CTO, 0xff);
 657 }
 658
 659 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 660 {
 661         int timeout;
 662         u16 reg;
 663
 664         /* Convert ns to clock cycles by assuming 20MHz frequency
 665          * 1 cycle at 20MHz = 500 ns
 666          */
 667         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 668
 669         /* Check if we need to use timeout multiplier register */
 670         reg = OMAP_MMC_READ(host, SDIO);
 671         if (timeout > 0xffff) {
 672                 reg |= (1 << 5);
 673                 timeout /= 1024;
 674         } else
 675                 reg &= ~(1 << 5);
 676         OMAP_MMC_WRITE(host, SDIO, reg);
 677         OMAP_MMC_WRITE(host, DTO, timeout);
 678 }
 679
 680 static void
 681 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 682 {
 683         struct mmc_data *data = req->data;
 684         int i, use_dma, block_size;
 685         unsigned sg_len;
 686
 687         host->data = data;
 688         if (data == NULL) {
 689                 OMAP_MMC_WRITE(host, BLEN, 0);
 690                 OMAP_MMC_WRITE(host, NBLK, 0);
 691                 OMAP_MMC_WRITE(host, BUF, 0);
 692                 host->dma_in_use = 0;
 693                 set_cmd_timeout(host, req);
 694                 return;
 695         }
 696
 697         block_size = data->blksz;
 698
 699         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 700         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 701         set_data_timeout(host, req);
 702
 703         /* cope with calling layer confusion; it issues "single
 704          * block" writes using multi-block scatterlists.
 705          */
 706         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 707
 708         /* Only do DMA for entire blocks */
 709         use_dma = host->use_dma;
 710         if (use_dma) {
 711                 for (i = 0; i < sg_len; i++) {
 712                         if ((data->sg[i].length % block_size) != 0) {
 713                                 use_dma = 0;
 714                                 break;
 715                         }
 716                 }
 717         }
 718
 719         host->sg_idx = 0;
 720         if (use_dma) {
 721                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 722                         enum dma_data_direction dma_data_dir;
 723
 724                         if (data->flags & MMC_DATA_WRITE)
 725                                 dma_data_dir = DMA_TO_DEVICE;
 726                         else
 727                                 dma_data_dir = DMA_FROM_DEVICE;
 728
 729                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 730                                                 sg_len, dma_data_dir);
 731                         host->total_bytes_left = 0;
 732                         mmc_omap_prepare_dma(host, req->data);
 733                         host->brs_received = 0;
 734                         host->dma_done = 0;
 735                         host->dma_in_use = 1;
 736                 } else
 737                         use_dma = 0;
 738         }
 739
 740         /* Revert to PIO? */
 741         if (!use_dma) {
 742                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 743                 host->total_bytes_left = data->blocks * block_size;
 744                 host->sg_len = sg_len;
 745                 mmc_omap_sg_to_buf(host);
 746                 host->dma_in_use = 0;
 747         }
 748 }
 749
 750 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 751 {
 752         struct mmc_omap_host *host = mmc_priv(mmc);
 753
 754         WARN_ON(host->mrq != NULL);
 755
 756         host->mrq = req;
 757
 758         /* only touch fifo AFTER the controller readies it */
 759         mmc_omap_prepare_data(host, req);
 760         mmc_omap_start_command(host, req->cmd);
 761         if (host->dma_in_use)
 762                 omap_start_dma(host->dma_ch);
 763 }
 764
 765 static void innovator_fpga_socket_power(int on)
 766 {
 767 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 768         if (on) {
 769                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 770                      OMAP1510_FPGA_POWER);
 771         } else {
 772                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 773                      OMAP1510_FPGA_POWER);
 774         }
 775 #endif
 776 }
 777
 778 /*
 779  * Turn the socket power on/off. Innovator uses FPGA, most boards
 780  * probably use GPIO.
 781  */
 782 static void mmc_omap_power(struct mmc_omap_host *host, int on)
 783 {
 784         if (on) {
 785                 if (machine_is_omap_innovator())
 786                         innovator_fpga_socket_power(1);
 787                 else if (machine_is_omap_h2())
 788                         tps65010_set_gpio_out_value(GPIO3, HIGH);
 789                 else if (machine_is_omap_h3())
 790                         /* GPIO 4 of TPS65010 sends SD_EN signal */
 791                         tps65010_set_gpio_out_value(GPIO4, HIGH);
 792                 else if (cpu_is_omap24xx()) {
 793                         u16 reg = OMAP_MMC_READ(host, CON);
 794                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
 795                 } else
 796                         if (host->power_pin >= 0)
 797                                 omap_set_gpio_dataout(host->power_pin, 1);
 798         } else {
 799                 if (machine_is_omap_innovator())
 800                         innovator_fpga_socket_power(0);
 801                 else if (machine_is_omap_h2())
 802                         tps65010_set_gpio_out_value(GPIO3, LOW);
 803                 else if (machine_is_omap_h3())
 804                         tps65010_set_gpio_out_value(GPIO4, LOW);
 805                 else if (cpu_is_omap24xx()) {
 806                         u16 reg = OMAP_MMC_READ(host, CON);
 807                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
 808                 } else
 809                         if (host->power_pin >= 0)
 810                                 omap_set_gpio_dataout(host->power_pin, 0);
 811         }
 812 }
 813
 814 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
 815 {
 816         struct mmc_omap_host *host = mmc_priv(mmc);
 817         int func_clk_rate = clk_get_rate(host->fclk);
 818         int dsor;
 819
 820         if (ios->clock == 0)
 821                 return 0;
 822
 823         dsor = func_clk_rate / ios->clock;
 824         if (dsor < 1)
 825                 dsor = 1;
 826
 827         if (func_clk_rate / dsor > ios->clock)
 828                 dsor++;
 829
 830         if (dsor > 250)
 831                 dsor = 250;
 832
 833         if (ios->bus_width == MMC_BUS_WIDTH_4)
 834                 dsor |= 1 << 15;
 835
 836         return dsor;
 837 }
 838
 839 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 840 {
 841         struct mmc_omap_host *host = mmc_priv(mmc);
 842         int dsor;
 843         int i;
 844
 845         dsor = mmc_omap_calc_divisor(mmc, ios);
 846         host->bus_mode = ios->bus_mode;
 847         host->hw_bus_mode = host->bus_mode;
 848
 849         switch (ios->power_mode) {
 850         case MMC_POWER_OFF:
 851                 mmc_omap_power(host, 0);
 852                 break;
 853         case MMC_POWER_UP:
 854                 /* Cannot touch dsor yet, just power up MMC */
 855                 mmc_omap_power(host, 1);
 856                 return;
 857         case MMC_POWER_ON:
 858                 dsor |= 1 << 11;
 859                 break;
 860         }
 861
 862         clk_enable(host->fclk);
 863
 864         /* On insanely high arm_per frequencies something sometimes
 865          * goes somehow out of sync, and the POW bit is not being set,
 866          * which results in the while loop below getting stuck.
 867          * Writing to the CON register twice seems to do the trick. */
 868         for (i = 0; i < 2; i++)
 869                 OMAP_MMC_WRITE(host, CON, dsor);
 870         if (ios->power_mode == MMC_POWER_ON) {
 871                 /* Send clock cycles, poll completion */
 872                 OMAP_MMC_WRITE(host, IE, 0);
 873                 OMAP_MMC_WRITE(host, STAT, 0xffff);
 874                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
 875                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
 876                 OMAP_MMC_WRITE(host, STAT, 1);
 877         }
 878         clk_disable(host->fclk);
 879 }
 880
 881 static int mmc_omap_get_ro(struct mmc_host *mmc)
 882 {
 883         struct mmc_omap_host *host = mmc_priv(mmc);
 884
 885         return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
 886 }
 887
 888 static const struct mmc_host_ops mmc_omap_ops = {
 889         .request        = mmc_omap_request,
 890         .set_ios        = mmc_omap_set_ios,
 891         .get_ro         = mmc_omap_get_ro,
 892 };
 893
 894 static int __init mmc_omap_probe(struct platform_device *pdev)
 895 {
 896         struct omap_mmc_conf *minfo = pdev->dev.platform_data;
 897         struct mmc_host *mmc;
 898         struct mmc_omap_host *host = NULL;
 899         struct resource *res;
 900         int ret = 0;
 901         int irq;
 902
 903         if (minfo == NULL) {
 904                 dev_err(&pdev->dev, "platform data missing\n");
 905                 return -ENXIO;
 906         }
 907
 908         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 909         irq = platform_get_irq(pdev, 0);
 910         if (res == NULL || irq < 0)
 911                 return -ENXIO;
 912
 913         res = request_mem_region(res->start, res->end - res->start + 1,
 914                                  pdev->name);
 915         if (res == NULL)
 916                 return -EBUSY;
 917
 918         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 919         if (mmc == NULL) {
 920                 ret = -ENOMEM;
 921                 goto err_free_mem_region;
 922         }
 923
 924         host = mmc_priv(mmc);
 925         host->mmc = mmc;
 926
 927         spin_lock_init(&host->dma_lock);
 928         init_timer(&host->dma_timer);
 929         host->dma_timer.function = mmc_omap_dma_timer;
 930         host->dma_timer.data = (unsigned long) host;
 931
 932         host->id = pdev->id;
 933         host->mem_res = res;
 934         host->irq = irq;
 935
 936         if (cpu_is_omap24xx()) {
 937                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
 938                 if (IS_ERR(host->iclk))
 939                         goto err_free_mmc_host;
 940                 clk_enable(host->iclk);
 941         }
 942
 943         if (!cpu_is_omap24xx())
 944                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
 945         else
 946                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
 947
 948         if (IS_ERR(host->fclk)) {
 949                 ret = PTR_ERR(host->fclk);
 950                 goto err_free_iclk;
 951         }
 952
 953         /* REVISIT:
 954          * Also, use minfo->cover to decide how to manage
 955          * the card detect sensing.
 956          */
 957         host->power_pin = minfo->power_pin;
 958         host->wp_pin = minfo->wp_pin;
 959         host->use_dma = 1;
 960         host->dma_ch = -1;
 961
 962         host->irq = irq;
 963         host->phys_base = host->mem_res->start;
 964         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
 965
 966         mmc->ops = &mmc_omap_ops;
 967         mmc->f_min = 400000;
 968         mmc->f_max = 24000000;
 969         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 970         mmc->caps = MMC_CAP_MULTIWRITE;
 971
 972         if (minfo->wire4)
 973                  mmc->caps |= MMC_CAP_4_BIT_DATA;
 974
 975         /* Use scatterlist DMA to reduce per-transfer costs.
 976          * NOTE max_seg_size assumption that small blocks aren't
 977          * normally used (except e.g. for reading SD registers).
 978          */
 979         mmc->max_phys_segs = 32;
 980         mmc->max_hw_segs = 32;
 981         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
 982         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
 983         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 984         mmc->max_seg_size = mmc->max_req_size;
 985
 986         if (host->power_pin >= 0) {
 987                 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
 988                         dev_err(mmc_dev(host->mmc),
 989                                 "Unable to get GPIO pin for MMC power\n");
 990                         goto err_free_fclk;
 991                 }
 992                 omap_set_gpio_direction(host->power_pin, 0);
 993         }
 994
 995         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
 996         if (ret)
 997                 goto err_free_power_gpio;
 998
 999         host->dev = &pdev->dev;
1000         platform_set_drvdata(pdev, host);
1001
1002         mmc_add_host(mmc);
1003
1004         return 0;
1005
1006         /* FIXME: Free other resources too. */
1007         if (host) {
1008                 if (host->iclk && !IS_ERR(host->iclk))
1009                         clk_put(host->iclk);
1010                 if (host->fclk && !IS_ERR(host->fclk))
1011                         clk_put(host->fclk);
1012                 mmc_free_host(host->mmc);
1013         }
1014 err_free_power_gpio:
1015         if (host->power_pin >= 0)
1016                 omap_free_gpio(host->power_pin);
1017 err_free_fclk:
1018         clk_put(host->fclk);
1019 err_free_iclk:
1020         if (host->iclk != NULL) {
1021                 clk_disable(host->iclk);
1022                 clk_put(host->iclk);
1023         }
1024 err_free_mmc_host:
1025         mmc_free_host(host->mmc);
1026 err_free_mem_region:
1027         release_mem_region(res->start, res->end - res->start + 1);
1028         return ret;
1029 }
1030
1031 static int mmc_omap_remove(struct platform_device *pdev)
1032 {
1033         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1034
1035         platform_set_drvdata(pdev, NULL);
1036
1037         BUG_ON(host == NULL);
1038
1039         mmc_remove_host(host->mmc);
1040         free_irq(host->irq, host);
1041
1042         if (host->power_pin >= 0)
1043                 omap_free_gpio(host->power_pin);
1044         if (host->iclk && !IS_ERR(host->iclk))
1045                 clk_put(host->iclk);
1046         if (host->fclk && !IS_ERR(host->fclk))
1047                 clk_put(host->fclk);
1048
1049         release_mem_region(pdev->resource[0].start,
1050                            pdev->resource[0].end - pdev->resource[0].start + 1);
1051
1052         mmc_free_host(host->mmc);
1053
1054         return 0;
1055 }
1056
1057 #ifdef CONFIG_PM
1058 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1059 {
1060         int ret = 0;
1061         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1062
1063         if (host && host->suspended)
1064                 return 0;
1065
1066         if (host) {
1067                 ret = mmc_suspend_host(host->mmc, mesg);
1068                 if (ret == 0)
1069                         host->suspended = 1;
1070         }
1071         return ret;
1072 }
1073
1074 static int mmc_omap_resume(struct platform_device *pdev)
1075 {
1076         int ret = 0;
1077         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1078
1079         if (host && !host->suspended)
1080                 return 0;
1081
1082         if (host) {
1083                 ret = mmc_resume_host(host->mmc);
1084                 if (ret == 0)
1085                         host->suspended = 0;
1086         }
1087
1088         return ret;
1089 }
1090 #else
1091 #define mmc_omap_suspend        NULL
1092 #define mmc_omap_resume         NULL
1093 #endif
1094
1095 static struct platform_driver mmc_omap_driver = {
1096         .probe          = mmc_omap_probe,
1097         .remove         = mmc_omap_remove,
1098         .suspend        = mmc_omap_suspend,
1099         .resume         = mmc_omap_resume,
1100         .driver         = {
1101                 .name   = DRIVER_NAME,
1102                 .owner  = THIS_MODULE,
1103         },
1104 };
1105
1106 static int __init mmc_omap_init(void)
1107 {
1108         return platform_driver_register(&mmc_omap_driver);
1109 }
1110
1111 static void __exit mmc_omap_exit(void)
1112 {
1113         platform_driver_unregister(&mmc_omap_driver);
1114 }
1115
1116 module_init(mmc_omap_init);
1117 module_exit(mmc_omap_exit);
1118
1119 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1120 MODULE_LICENSE("GPL");
1121 MODULE_ALIAS("platform:" DRIVER_NAME);
1122 MODULE_AUTHOR("Juha Yrjölä");