drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/clk.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/i2c/tps65010.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/mmc.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/dma.h>
  38 #include <asm/arch/mux.h>
  39 #include <asm/arch/fpga.h>
  40
  41 #define OMAP_MMC_REG_CMD        0x00
  42 #define OMAP_MMC_REG_ARGL       0x04
  43 #define OMAP_MMC_REG_ARGH       0x08
  44 #define OMAP_MMC_REG_CON        0x0c
  45 #define OMAP_MMC_REG_STAT       0x10
  46 #define OMAP_MMC_REG_IE         0x14
  47 #define OMAP_MMC_REG_CTO        0x18
  48 #define OMAP_MMC_REG_DTO        0x1c
  49 #define OMAP_MMC_REG_DATA       0x20
  50 #define OMAP_MMC_REG_BLEN       0x24
  51 #define OMAP_MMC_REG_NBLK       0x28
  52 #define OMAP_MMC_REG_BUF        0x2c
  53 #define OMAP_MMC_REG_SDIO       0x34
  54 #define OMAP_MMC_REG_REV        0x3c
  55 #define OMAP_MMC_REG_RSP0       0x40
  56 #define OMAP_MMC_REG_RSP1       0x44
  57 #define OMAP_MMC_REG_RSP2       0x48
  58 #define OMAP_MMC_REG_RSP3       0x4c
  59 #define OMAP_MMC_REG_RSP4       0x50
  60 #define OMAP_MMC_REG_RSP5       0x54
  61 #define OMAP_MMC_REG_RSP6       0x58
  62 #define OMAP_MMC_REG_RSP7       0x5c
  63 #define OMAP_MMC_REG_IOSR       0x60
  64 #define OMAP_MMC_REG_SYSC       0x64
  65 #define OMAP_MMC_REG_SYSS       0x68
  66
  67 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  68 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  69 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  70 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  71 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  72 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  73 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  74 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  75 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  76 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  77 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  78 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  79 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  80
  81 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  82 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  83
  84 /*
  85  * Command types
  86  */
  87 #define OMAP_MMC_CMDTYPE_BC     0
  88 #define OMAP_MMC_CMDTYPE_BCR    1
  89 #define OMAP_MMC_CMDTYPE_AC     2
  90 #define OMAP_MMC_CMDTYPE_ADTC   3
  91
  92
  93 #define DRIVER_NAME "mmci-omap"
  94
  95 /* Specifies how often in millisecs to poll for card status changes
  96  * when the cover switch is open */
  97 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  98
  99 struct mmc_omap_host;
 100
 101 struct mmc_omap_slot {
 102         int                     id;
 103         unsigned int            vdd;
 104         u16                     saved_con;
 105         u16                     bus_mode;
 106         unsigned int            fclk_freq;
 107         unsigned                powered:1;
 108
 109         struct work_struct      switch_work;
 110         struct timer_list       switch_timer;
 111         unsigned                cover_open;
 112
 113         struct mmc_request      *mrq;
 114         struct mmc_omap_host    *host;
 115         struct mmc_host         *mmc;
 116         struct omap_mmc_slot_data *pdata;
 117 };
 118
 119 struct mmc_omap_host {
 120         int                     initialized;
 121         int                     suspended;
 122         struct mmc_request *    mrq;
 123         struct mmc_command *    cmd;
 124         struct mmc_data *       data;
 125         struct mmc_host *       mmc;
 126         struct device *         dev;
 127         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 128         struct clk *            iclk;
 129         struct clk *            fclk;
 130         struct resource         *mem_res;
 131         void __iomem            *virt_base;
 132         unsigned int            phys_base;
 133         int                     irq;
 134         unsigned char           bus_mode;
 135         unsigned char           hw_bus_mode;
 136
 137         unsigned int            sg_len;
 138         int                     sg_idx;
 139         u16 *                   buffer;
 140         u32                     buffer_bytes_left;
 141         u32                     total_bytes_left;
 142
 143         unsigned                use_dma:1;
 144         unsigned                brs_received:1, dma_done:1;
 145         unsigned                dma_is_read:1;
 146         unsigned                dma_in_use:1;
 147         int                     dma_ch;
 148         spinlock_t              dma_lock;
 149         struct timer_list       dma_timer;
 150         unsigned                dma_len;
 151
 152         short                   power_pin;
 153
 154         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 155         struct mmc_omap_slot    *current_slot;
 156         spinlock_t              slot_lock;
 157         wait_queue_head_t       slot_wq;
 158         int                     nr_slots;
 159
 160         struct omap_mmc_platform_data *pdata;
 161 };
 162
 163 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 164 {
 165         struct mmc_omap_host *host = slot->host;
 166         unsigned long flags;
 167
 168         if (claimed)
 169                 goto no_claim;
 170         spin_lock_irqsave(&host->slot_lock, flags);
 171         while (host->mmc != NULL) {
 172                 spin_unlock_irqrestore(&host->slot_lock, flags);
 173                 wait_event(host->slot_wq, host->mmc == NULL);
 174                 spin_lock_irqsave(&host->slot_lock, flags);
 175         }
 176         host->mmc = slot->mmc;
 177         spin_unlock_irqrestore(&host->slot_lock, flags);
 178 no_claim:
 179         clk_enable(host->fclk);
 180         if (host->current_slot != slot) {
 181                 if (host->pdata->switch_slot != NULL)
 182                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 183                 host->current_slot = slot;
 184         }
 185
 186         /* Doing the dummy read here seems to work around some bug
 187          * at least in OMAP24xx silicon where the command would not
 188          * start after writing the CMD register. Sigh. */
 189         OMAP_MMC_READ(host, CON);
 190
 191         OMAP_MMC_WRITE(host, CON, slot->saved_con);
 192 }
 193
 194 static void mmc_omap_start_request(struct mmc_omap_host *host,
 195                                    struct mmc_request *req);
 196
 197 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
 198 {
 199         struct mmc_omap_host *host = slot->host;
 200         unsigned long flags;
 201         int i;
 202
 203         BUG_ON(slot == NULL || host->mmc == NULL);
 204         clk_disable(host->fclk);
 205
 206         spin_lock_irqsave(&host->slot_lock, flags);
 207         /* Check for any pending requests */
 208         for (i = 0; i < host->nr_slots; i++) {
 209                 struct mmc_omap_slot *new_slot;
 210                 struct mmc_request *rq;
 211
 212                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 213                         continue;
 214
 215                 new_slot = host->slots[i];
 216                 /* The current slot should not have a request in queue */
 217                 BUG_ON(new_slot == host->current_slot);
 218
 219                 host->mmc = new_slot->mmc;
 220                 spin_unlock_irqrestore(&host->slot_lock, flags);
 221                 mmc_omap_select_slot(new_slot, 1);
 222                 rq = new_slot->mrq;
 223                 new_slot->mrq = NULL;
 224                 mmc_omap_start_request(host, rq);
 225                 return;
 226         }
 227
 228         host->mmc = NULL;
 229         wake_up(&host->slot_wq);
 230         spin_unlock_irqrestore(&host->slot_lock, flags);
 231 }
 232
 233 static inline
 234 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 235 {
 236         return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
 237 }
 238
 239 static ssize_t
 240 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 241                            char *buf)
 242 {
 243         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 244         struct mmc_omap_slot *slot = mmc_priv(mmc);
 245
 246         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 247                        "closed");
 248 }
 249
 250 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 251
 252 static ssize_t
 253 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 254                         char *buf)
 255 {
 256         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 257         struct mmc_omap_slot *slot = mmc_priv(mmc);
 258
 259         return sprintf(buf, "%s\n", slot->pdata->name);
 260 }
 261
 262 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 263
 264 static void
 265 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 266 {
 267         u32 cmdreg;
 268         u32 resptype;
 269         u32 cmdtype;
 270
 271         host->cmd = cmd;
 272
 273         resptype = 0;
 274         cmdtype = 0;
 275
 276         /* Our hardware needs to know exact type */
 277         switch (mmc_resp_type(cmd)) {
 278         case MMC_RSP_NONE:
 279                 break;
 280         case MMC_RSP_R1:
 281         case MMC_RSP_R1B:
 282                 /* resp 1, 1b, 6, 7 */
 283                 resptype = 1;
 284                 break;
 285         case MMC_RSP_R2:
 286                 resptype = 2;
 287                 break;
 288         case MMC_RSP_R3:
 289                 resptype = 3;
 290                 break;
 291         default:
 292                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 293                 break;
 294         }
 295
 296         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 297                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 298         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 299                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 300         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 301                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 302         } else {
 303                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 304         }
 305
 306         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 307
 308         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 309                 cmdreg |= 1 << 6;
 310
 311         if (cmd->flags & MMC_RSP_BUSY)
 312                 cmdreg |= 1 << 11;
 313
 314         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 315                 cmdreg |= 1 << 15;
 316
 317         OMAP_MMC_WRITE(host, CTO, 200);
 318         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 319         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 320         OMAP_MMC_WRITE(host, IE,
 321                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 322                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 323                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 324                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 325                        OMAP_MMC_STAT_END_OF_DATA);
 326         OMAP_MMC_WRITE(host, CMD, cmdreg);
 327 }
 328
 329 static void
 330 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 331 {
 332         if (host->dma_in_use) {
 333                 enum dma_data_direction dma_data_dir;
 334
 335                 BUG_ON(host->dma_ch < 0);
 336                 if (data->error)
 337                         omap_stop_dma(host->dma_ch);
 338                 /* Release DMA channel lazily */
 339                 mod_timer(&host->dma_timer, jiffies + HZ);
 340                 if (data->flags & MMC_DATA_WRITE)
 341                         dma_data_dir = DMA_TO_DEVICE;
 342                 else
 343                         dma_data_dir = DMA_FROM_DEVICE;
 344                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 345                              dma_data_dir);
 346         }
 347         host->data = NULL;
 348         host->sg_len = 0;
 349         clk_disable(host->fclk);
 350
 351         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 352          * dozens of requests until the card finishes writing data.
 353          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 354          */
 355
 356         if (!data->stop) {
 357                 host->mrq = NULL;
 358                 mmc_request_done(host->mmc, data->mrq);
 359                 return;
 360         }
 361
 362         mmc_omap_start_command(host, data->stop);
 363 }
 364
 365 static void
 366 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 367 {
 368         unsigned long flags;
 369         int done;
 370
 371         if (!host->dma_in_use) {
 372                 mmc_omap_xfer_done(host, data);
 373                 return;
 374         }
 375         done = 0;
 376         spin_lock_irqsave(&host->dma_lock, flags);
 377         if (host->dma_done)
 378                 done = 1;
 379         else
 380                 host->brs_received = 1;
 381         spin_unlock_irqrestore(&host->dma_lock, flags);
 382         if (done)
 383                 mmc_omap_xfer_done(host, data);
 384 }
 385
 386 static void
 387 mmc_omap_dma_timer(unsigned long data)
 388 {
 389         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 390
 391         BUG_ON(host->dma_ch < 0);
 392         omap_free_dma(host->dma_ch);
 393         host->dma_ch = -1;
 394 }
 395
 396 static void
 397 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 398 {
 399         unsigned long flags;
 400         int done;
 401
 402         done = 0;
 403         spin_lock_irqsave(&host->dma_lock, flags);
 404         if (host->brs_received)
 405                 done = 1;
 406         else
 407                 host->dma_done = 1;
 408         spin_unlock_irqrestore(&host->dma_lock, flags);
 409         if (done)
 410                 mmc_omap_xfer_done(host, data);
 411 }
 412
 413 static void
 414 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 415 {
 416         host->cmd = NULL;
 417
 418         if (cmd->flags & MMC_RSP_PRESENT) {
 419                 if (cmd->flags & MMC_RSP_136) {
 420                         /* response type 2 */
 421                         cmd->resp[3] =
 422                                 OMAP_MMC_READ(host, RSP0) |
 423                                 (OMAP_MMC_READ(host, RSP1) << 16);
 424                         cmd->resp[2] =
 425                                 OMAP_MMC_READ(host, RSP2) |
 426                                 (OMAP_MMC_READ(host, RSP3) << 16);
 427                         cmd->resp[1] =
 428                                 OMAP_MMC_READ(host, RSP4) |
 429                                 (OMAP_MMC_READ(host, RSP5) << 16);
 430                         cmd->resp[0] =
 431                                 OMAP_MMC_READ(host, RSP6) |
 432                                 (OMAP_MMC_READ(host, RSP7) << 16);
 433                 } else {
 434                         /* response types 1, 1b, 3, 4, 5, 6 */
 435                         cmd->resp[0] =
 436                                 OMAP_MMC_READ(host, RSP6) |
 437                                 (OMAP_MMC_READ(host, RSP7) << 16);
 438                 }
 439         }
 440
 441         if (host->data == NULL || cmd->error) {
 442                 host->mrq = NULL;
 443                 clk_disable(host->fclk);
 444                 mmc_request_done(host->mmc, cmd->mrq);
 445         }
 446 }
 447
 448 /* PIO only */
 449 static void
 450 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 451 {
 452         struct scatterlist *sg;
 453
 454         sg = host->data->sg + host->sg_idx;
 455         host->buffer_bytes_left = sg->length;
 456         host->buffer = sg_virt(sg);
 457         if (host->buffer_bytes_left > host->total_bytes_left)
 458                 host->buffer_bytes_left = host->total_bytes_left;
 459 }
 460
 461 /* PIO only */
 462 static void
 463 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 464 {
 465         int n;
 466
 467         if (host->buffer_bytes_left == 0) {
 468                 host->sg_idx++;
 469                 BUG_ON(host->sg_idx == host->sg_len);
 470                 mmc_omap_sg_to_buf(host);
 471         }
 472         n = 64;
 473         if (n > host->buffer_bytes_left)
 474                 n = host->buffer_bytes_left;
 475         host->buffer_bytes_left -= n;
 476         host->total_bytes_left -= n;
 477         host->data->bytes_xfered += n;
 478
 479         if (write) {
 480                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 481         } else {
 482                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 483         }
 484 }
 485
 486 static inline void mmc_omap_report_irq(u16 status)
 487 {
 488         static const char *mmc_omap_status_bits[] = {
 489                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 490                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 491         };
 492         int i, c = 0;
 493
 494         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 495                 if (status & (1 << i)) {
 496                         if (c)
 497                                 printk(" ");
 498                         printk("%s", mmc_omap_status_bits[i]);
 499                         c++;
 500                 }
 501 }
 502
 503 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 504 {
 505         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 506         u16 status;
 507         int end_command;
 508         int end_transfer;
 509         int transfer_error;
 510
 511         if (host->cmd == NULL && host->data == NULL) {
 512                 status = OMAP_MMC_READ(host, STAT);
 513                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 514                 if (status != 0) {
 515                         OMAP_MMC_WRITE(host, STAT, status);
 516                         OMAP_MMC_WRITE(host, IE, 0);
 517                 }
 518                 return IRQ_HANDLED;
 519         }
 520
 521         end_command = 0;
 522         end_transfer = 0;
 523         transfer_error = 0;
 524
 525         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 526                 OMAP_MMC_WRITE(host, STAT, status);
 527 #ifdef CONFIG_MMC_DEBUG
 528                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 529                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 530                 mmc_omap_report_irq(status);
 531                 printk("\n");
 532 #endif
 533                 if (host->total_bytes_left) {
 534                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 535                             (status & OMAP_MMC_STAT_END_OF_DATA))
 536                                 mmc_omap_xfer_data(host, 0);
 537                         if (status & OMAP_MMC_STAT_A_EMPTY)
 538                                 mmc_omap_xfer_data(host, 1);
 539                 }
 540
 541                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 542                         end_transfer = 1;
 543                 }
 544
 545                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 546                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 547                         if (host->data) {
 548                                 host->data->error = -ETIMEDOUT;
 549                                 transfer_error = 1;
 550                         }
 551                 }
 552
 553                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 554                         if (host->data) {
 555                                 host->data->error = -EILSEQ;
 556                                 dev_dbg(mmc_dev(host->mmc),
 557                                          "data CRC error, bytes left %d\n",
 558                                         host->total_bytes_left);
 559                                 transfer_error = 1;
 560                         } else {
 561                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 562                         }
 563                 }
 564
 565                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 566                         /* Timeouts are routine with some commands */
 567                         if (host->cmd) {
 568                                 struct mmc_omap_slot *slot =
 569                                         host->current_slot;
 570                                 if (!mmc_omap_cover_is_open(slot))
 571                                         dev_err(mmc_dev(host->mmc),
 572                                                 "command timeout, CMD %d\n",
 573                                                 host->cmd->opcode);
 574                                 host->cmd->error = -ETIMEDOUT;
 575                                 end_command = 1;
 576                         }
 577                 }
 578
 579                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 580                         if (host->cmd) {
 581                                 dev_err(mmc_dev(host->mmc),
 582                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 583                                         host->cmd->opcode, host->cmd->arg);
 584                                 host->cmd->error = -EILSEQ;
 585                                 end_command = 1;
 586                         } else
 587                                 dev_err(mmc_dev(host->mmc),
 588                                         "command CRC error without cmd?\n");
 589                 }
 590
 591                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 592                         dev_dbg(mmc_dev(host->mmc),
 593                                 "ignoring card status error (CMD%d)\n",
 594                                 host->cmd->opcode);
 595                         end_command = 1;
 596                 }
 597
 598                 /*
 599                  * NOTE: On 1610 the END_OF_CMD may come too early when
 600                  * starting a write
 601                  */
 602                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 603                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 604                         end_command = 1;
 605                 }
 606         }
 607
 608         if (end_command) {
 609                 mmc_omap_cmd_done(host, host->cmd);
 610         }
 611         if (transfer_error)
 612                 mmc_omap_xfer_done(host, host->data);
 613         else if (end_transfer)
 614                 mmc_omap_end_of_data(host, host->data);
 615
 616         return IRQ_HANDLED;
 617 }
 618
 619 void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed)
 620 {
 621         struct mmc_omap_host *host = dev_get_drvdata(dev);
 622
 623         BUG_ON(slot >= host->nr_slots);
 624
 625         /* Other subsystems can call in here before we're initialised. */
 626         if (host->nr_slots == 0 || !host->slots[slot])
 627                 return;
 628
 629         schedule_work(&host->slots[slot]->switch_work);
 630 }
 631
 632 static void mmc_omap_switch_timer(unsigned long arg)
 633 {
 634         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 635
 636         schedule_work(&slot->switch_work);
 637 }
 638
 639 static void mmc_omap_cover_handler(struct work_struct *work)
 640 {
 641         struct mmc_omap_slot *slot = container_of(work, struct mmc_omap_slot,
 642                                                   switch_work);
 643         int cover_open;
 644
 645         cover_open = mmc_omap_cover_is_open(slot);
 646         if (cover_open != slot->cover_open) {
 647                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 648                 slot->cover_open = cover_open;
 649                 dev_info(mmc_dev(slot->mmc), "cover is now %s\n",
 650                          cover_open ? "open" : "closed");
 651         }
 652         mmc_detect_change(slot->mmc, slot->id);
 653 }
 654
 655 /* Prepare to transfer the next segment of a scatterlist */
 656 static void
 657 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 658 {
 659         int dma_ch = host->dma_ch;
 660         unsigned long data_addr;
 661         u16 buf, frame;
 662         u32 count;
 663         struct scatterlist *sg = &data->sg[host->sg_idx];
 664         int src_port = 0;
 665         int dst_port = 0;
 666         int sync_dev = 0;
 667
 668         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 669         frame = data->blksz;
 670         count = sg_dma_len(sg);
 671
 672         if ((data->blocks == 1) && (count > data->blksz))
 673                 count = frame;
 674
 675         host->dma_len = count;
 676
 677         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 678          * Use 16 or 32 word frames when the blocksize is at least that large.
 679          * Blocksize is usually 512 bytes; but not for some SD reads.
 680          */
 681         if (cpu_is_omap15xx() && frame > 32)
 682                 frame = 32;
 683         else if (frame > 64)
 684                 frame = 64;
 685         count /= frame;
 686         frame >>= 1;
 687
 688         if (!(data->flags & MMC_DATA_WRITE)) {
 689                 buf = 0x800f | ((frame - 1) << 8);
 690
 691                 if (cpu_class_is_omap1()) {
 692                         src_port = OMAP_DMA_PORT_TIPB;
 693                         dst_port = OMAP_DMA_PORT_EMIFF;
 694                 }
 695                 if (cpu_is_omap24xx())
 696                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 697
 698                 omap_set_dma_src_params(dma_ch, src_port,
 699                                         OMAP_DMA_AMODE_CONSTANT,
 700                                         data_addr, 0, 0);
 701                 omap_set_dma_dest_params(dma_ch, dst_port,
 702                                          OMAP_DMA_AMODE_POST_INC,
 703                                          sg_dma_address(sg), 0, 0);
 704                 omap_set_dma_dest_data_pack(dma_ch, 1);
 705                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 706         } else {
 707                 buf = 0x0f80 | ((frame - 1) << 0);
 708
 709                 if (cpu_class_is_omap1()) {
 710                         src_port = OMAP_DMA_PORT_EMIFF;
 711                         dst_port = OMAP_DMA_PORT_TIPB;
 712                 }
 713                 if (cpu_is_omap24xx())
 714                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 715
 716                 omap_set_dma_dest_params(dma_ch, dst_port,
 717                                          OMAP_DMA_AMODE_CONSTANT,
 718                                          data_addr, 0, 0);
 719                 omap_set_dma_src_params(dma_ch, src_port,
 720                                         OMAP_DMA_AMODE_POST_INC,
 721                                         sg_dma_address(sg), 0, 0);
 722                 omap_set_dma_src_data_pack(dma_ch, 1);
 723                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 724         }
 725
 726         /* Max limit for DMA frame count is 0xffff */
 727         BUG_ON(count > 0xffff);
 728
 729         OMAP_MMC_WRITE(host, BUF, buf);
 730         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 731                                      frame, count, OMAP_DMA_SYNC_FRAME,
 732                                      sync_dev, 0);
 733 }
 734
 735 /* A scatterlist segment completed */
 736 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 737 {
 738         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 739         struct mmc_data *mmcdat = host->data;
 740
 741         if (unlikely(host->dma_ch < 0)) {
 742                 dev_err(mmc_dev(host->mmc),
 743                         "DMA callback while DMA not enabled\n");
 744                 return;
 745         }
 746         /* FIXME: We really should do something to _handle_ the errors */
 747         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 748                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 749                 return;
 750         }
 751         if (ch_status & OMAP_DMA_DROP_IRQ) {
 752                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 753                 return;
 754         }
 755         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 756                 return;
 757         }
 758         mmcdat->bytes_xfered += host->dma_len;
 759         host->sg_idx++;
 760         if (host->sg_idx < host->sg_len) {
 761                 mmc_omap_prepare_dma(host, host->data);
 762                 omap_start_dma(host->dma_ch);
 763         } else
 764                 mmc_omap_dma_done(host, host->data);
 765 }
 766
 767 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 768 {
 769         const char *dev_name;
 770         int sync_dev, dma_ch, is_read, r;
 771
 772         is_read = !(data->flags & MMC_DATA_WRITE);
 773         del_timer_sync(&host->dma_timer);
 774         if (host->dma_ch >= 0) {
 775                 if (is_read == host->dma_is_read)
 776                         return 0;
 777                 omap_free_dma(host->dma_ch);
 778                 host->dma_ch = -1;
 779         }
 780
 781         if (is_read) {
 782                 if (host->id == 1) {
 783                         sync_dev = OMAP_DMA_MMC_RX;
 784                         dev_name = "MMC1 read";
 785                 } else {
 786                         sync_dev = OMAP_DMA_MMC2_RX;
 787                         dev_name = "MMC2 read";
 788                 }
 789         } else {
 790                 if (host->id == 1) {
 791                         sync_dev = OMAP_DMA_MMC_TX;
 792                         dev_name = "MMC1 write";
 793                 } else {
 794                         sync_dev = OMAP_DMA_MMC2_TX;
 795                         dev_name = "MMC2 write";
 796                 }
 797         }
 798         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 799                              host, &dma_ch);
 800         if (r != 0) {
 801                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 802                 return r;
 803         }
 804         host->dma_ch = dma_ch;
 805         host->dma_is_read = is_read;
 806
 807         return 0;
 808 }
 809
 810 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 811 {
 812         u16 reg;
 813
 814         reg = OMAP_MMC_READ(host, SDIO);
 815         reg &= ~(1 << 5);
 816         OMAP_MMC_WRITE(host, SDIO, reg);
 817         /* Set maximum timeout */
 818         OMAP_MMC_WRITE(host, CTO, 0xff);
 819 }
 820
 821 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 822 {
 823         int timeout;
 824         u16 reg;
 825
 826         /* Convert ns to clock cycles by assuming 20MHz frequency
 827          * 1 cycle at 20MHz = 500 ns
 828          */
 829         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 830
 831         /* Check if we need to use timeout multiplier register */
 832         reg = OMAP_MMC_READ(host, SDIO);
 833         if (timeout > 0xffff) {
 834                 reg |= (1 << 5);
 835                 timeout /= 1024;
 836         } else
 837                 reg &= ~(1 << 5);
 838         OMAP_MMC_WRITE(host, SDIO, reg);
 839         OMAP_MMC_WRITE(host, DTO, timeout);
 840 }
 841
 842 static void
 843 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 844 {
 845         struct mmc_data *data = req->data;
 846         int i, use_dma, block_size;
 847         unsigned sg_len;
 848
 849         host->data = data;
 850         if (data == NULL) {
 851                 OMAP_MMC_WRITE(host, BLEN, 0);
 852                 OMAP_MMC_WRITE(host, NBLK, 0);
 853                 OMAP_MMC_WRITE(host, BUF, 0);
 854                 host->dma_in_use = 0;
 855                 set_cmd_timeout(host, req);
 856                 return;
 857         }
 858
 859         block_size = data->blksz;
 860
 861         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 862         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 863         set_data_timeout(host, req);
 864
 865         /* cope with calling layer confusion; it issues "single
 866          * block" writes using multi-block scatterlists.
 867          */
 868         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 869
 870         /* Only do DMA for entire blocks */
 871         use_dma = host->use_dma;
 872         if (use_dma) {
 873                 for (i = 0; i < sg_len; i++) {
 874                         if ((data->sg[i].length % block_size) != 0) {
 875                                 use_dma = 0;
 876                                 break;
 877                         }
 878                 }
 879         }
 880
 881         host->sg_idx = 0;
 882         if (use_dma) {
 883                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 884                         enum dma_data_direction dma_data_dir;
 885
 886                         if (data->flags & MMC_DATA_WRITE)
 887                                 dma_data_dir = DMA_TO_DEVICE;
 888                         else
 889                                 dma_data_dir = DMA_FROM_DEVICE;
 890
 891                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 892                                                 sg_len, dma_data_dir);
 893                         host->total_bytes_left = 0;
 894                         mmc_omap_prepare_dma(host, req->data);
 895                         host->brs_received = 0;
 896                         host->dma_done = 0;
 897                         host->dma_in_use = 1;
 898                 } else
 899                         use_dma = 0;
 900         }
 901
 902         /* Revert to PIO? */
 903         if (!use_dma) {
 904                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 905                 host->total_bytes_left = data->blocks * block_size;
 906                 host->sg_len = sg_len;
 907                 mmc_omap_sg_to_buf(host);
 908                 host->dma_in_use = 0;
 909         }
 910 }
 911
 912 static void mmc_omap_start_request(struct mmc_omap_host *host,
 913                                    struct mmc_request *req)
 914 {
 915         BUG_ON(host->mrq != NULL);
 916
 917         host->mrq = req;
 918
 919         /* only touch fifo AFTER the controller readies it */
 920         mmc_omap_prepare_data(host, req);
 921         mmc_omap_start_command(host, req->cmd);
 922         if (host->dma_in_use)
 923                 omap_start_dma(host->dma_ch);
 924         BUG_ON(irqs_disabled());
 925 }
 926
 927 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 928 {
 929         struct mmc_omap_slot *slot = mmc_priv(mmc);
 930         struct mmc_omap_host *host = slot->host;
 931         unsigned long flags;
 932
 933         spin_lock_irqsave(&host->slot_lock, flags);
 934         if (host->mmc != NULL) {
 935                 BUG_ON(slot->mrq != NULL);
 936                 slot->mrq = req;
 937                 spin_unlock_irqrestore(&host->slot_lock, flags);
 938                 return;
 939         } else
 940                 host->mmc = mmc;
 941         spin_unlock_irqrestore(&host->slot_lock, flags);
 942         mmc_omap_select_slot(slot, 1);
 943         mmc_omap_start_request(host, req);
 944 }
 945
 946 static void innovator_fpga_socket_power(int on)
 947 {
 948 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 949         if (on) {
 950                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 951                      OMAP1510_FPGA_POWER);
 952         } else {
 953                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 954                      OMAP1510_FPGA_POWER);
 955         }
 956 #endif
 957 }
 958
 959 /*
 960  * Turn the socket power on/off. Innovator uses FPGA, most boards
 961  * probably use GPIO.
 962  */
 963 static void mmc_omap_power(struct mmc_omap_host *host, int on)
 964 {
 965         if (on) {
 966                 if (machine_is_omap_innovator())
 967                         innovator_fpga_socket_power(1);
 968                 else if (machine_is_omap_h2())
 969                         tps65010_set_gpio_out_value(GPIO3, HIGH);
 970                 else if (machine_is_omap_h3())
 971                         /* GPIO 4 of TPS65010 sends SD_EN signal */
 972                         tps65010_set_gpio_out_value(GPIO4, HIGH);
 973                 else if (cpu_is_omap24xx()) {
 974                         u16 reg = OMAP_MMC_READ(host, CON);
 975                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
 976                 } else
 977                         if (host->power_pin >= 0)
 978                                 omap_set_gpio_dataout(host->power_pin, 1);
 979         } else {
 980                 if (machine_is_omap_innovator())
 981                         innovator_fpga_socket_power(0);
 982                 else if (machine_is_omap_h2())
 983                         tps65010_set_gpio_out_value(GPIO3, LOW);
 984                 else if (machine_is_omap_h3())
 985                         tps65010_set_gpio_out_value(GPIO4, LOW);
 986                 else if (cpu_is_omap24xx()) {
 987                         u16 reg = OMAP_MMC_READ(host, CON);
 988                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
 989                 } else
 990                         if (host->power_pin >= 0)
 991                                 omap_set_gpio_dataout(host->power_pin, 0);
 992         }
 993 }
 994
 995 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
 996 {
 997         struct mmc_omap_slot *slot = mmc_priv(mmc);
 998         struct mmc_omap_host *host = slot->host;
 999         int func_clk_rate = clk_get_rate(host->fclk);
1000         int dsor;
1001
1002         if (ios->clock == 0)
1003                 return 0;
1004
1005         dsor = func_clk_rate / ios->clock;
1006         if (dsor < 1)
1007                 dsor = 1;
1008
1009         if (func_clk_rate / dsor > ios->clock)
1010                 dsor++;
1011
1012         if (dsor > 250)
1013                 dsor = 250;
1014
1015         slot->fclk_freq = func_clk_rate / dsor;
1016
1017         if (ios->bus_width == MMC_BUS_WIDTH_4)
1018                 dsor |= 1 << 15;
1019
1020         return dsor;
1021 }
1022
1023 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1024 {
1025         struct mmc_omap_slot *slot = mmc_priv(mmc);
1026         struct mmc_omap_host *host = slot->host;
1027         int i, dsor;
1028
1029         dsor = mmc_omap_calc_divisor(mmc, ios);
1030         host->bus_mode = ios->bus_mode;
1031         host->hw_bus_mode = host->bus_mode;
1032
1033         switch (ios->power_mode) {
1034         case MMC_POWER_OFF:
1035                 mmc_omap_power(host, 0);
1036                 break;
1037         case MMC_POWER_UP:
1038                 /* Cannot touch dsor yet, just power up MMC */
1039                 mmc_omap_power(host, 1);
1040                 return;
1041         case MMC_POWER_ON:
1042                 dsor |= 1 << 11;
1043                 break;
1044         }
1045
1046         clk_enable(host->fclk);
1047
1048         /* On insanely high arm_per frequencies something sometimes
1049          * goes somehow out of sync, and the POW bit is not being set,
1050          * which results in the while loop below getting stuck.
1051          * Writing to the CON register twice seems to do the trick. */
1052         for (i = 0; i < 2; i++)
1053                 OMAP_MMC_WRITE(host, CON, dsor);
1054         if (ios->power_mode == MMC_POWER_ON) {
1055                 /* Send clock cycles, poll completion */
1056                 OMAP_MMC_WRITE(host, IE, 0);
1057                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1058                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1059                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1060                 OMAP_MMC_WRITE(host, STAT, 1);
1061         }
1062         clk_disable(host->fclk);
1063 }
1064
1065 static const struct mmc_host_ops mmc_omap_ops = {
1066         .request        = mmc_omap_request,
1067         .set_ios        = mmc_omap_set_ios,
1068 };
1069
1070 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1071 {
1072         struct mmc_omap_slot *slot = NULL;
1073         struct mmc_host *mmc;
1074         int r;
1075
1076         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1077         if (mmc == NULL)
1078                 return -ENOMEM;
1079
1080         slot = mmc_priv(mmc);
1081         slot->host = host;
1082         slot->mmc = mmc;
1083         slot->id = id;
1084         slot->pdata = &host->pdata->slots[id];
1085
1086         host->slots[id] = slot;
1087
1088         mmc->caps = MMC_CAP_MULTIWRITE;
1089         if (host->pdata->conf.wire4)
1090                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1091
1092         mmc->ops = &mmc_omap_ops;
1093         mmc->f_min = 400000;
1094
1095         if (cpu_class_is_omap2())
1096                 mmc->f_max = 48000000;
1097         else
1098                 mmc->f_max = 24000000;
1099         if (host->pdata->max_freq)
1100                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1101         mmc->ocr_avail = slot->pdata->ocr_mask;
1102
1103         /* Use scatterlist DMA to reduce per-transfer costs.
1104          * NOTE max_seg_size assumption that small blocks aren't
1105          * normally used (except e.g. for reading SD registers).
1106          */
1107         mmc->max_phys_segs = 32;
1108         mmc->max_hw_segs = 32;
1109         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1110         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1111         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1112         mmc->max_seg_size = mmc->max_req_size;
1113
1114         r = mmc_add_host(mmc);
1115         if (r < 0)
1116                 goto err_remove_host;
1117
1118         if (slot->pdata->name != NULL) {
1119                 r = device_create_file(&mmc->class_dev,
1120                                         &dev_attr_slot_name);
1121                 if (r < 0)
1122                         goto err_remove_host;
1123         }
1124
1125         if (slot->pdata->get_cover_state != NULL) {
1126                 r = device_create_file(&mmc->class_dev,
1127                                         &dev_attr_cover_switch);
1128                 if (r < 0)
1129                         goto err_remove_slot_name;
1130
1131                 INIT_WORK(&slot->switch_work, mmc_omap_cover_handler);
1132                 init_timer(&slot->switch_timer);
1133                 slot->switch_timer.function = mmc_omap_switch_timer;
1134                 slot->switch_timer.data = (unsigned long) slot;
1135                 schedule_work(&slot->switch_work);
1136         }
1137
1138         return 0;
1139
1140 err_remove_slot_name:
1141         if (slot->pdata->name != NULL)
1142                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1143 err_remove_host:
1144         mmc_remove_host(mmc);
1145         mmc_free_host(mmc);
1146         return r;
1147 }
1148
1149 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1150 {
1151         struct mmc_host *mmc = slot->mmc;
1152
1153         if (slot->pdata->name != NULL)
1154                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1155         if (slot->pdata->get_cover_state != NULL)
1156                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1157
1158         del_timer_sync(&slot->switch_timer);
1159         flush_scheduled_work();
1160
1161         mmc_remove_host(mmc);
1162         mmc_free_host(mmc);
1163 }
1164
1165 static int __init mmc_omap_probe(struct platform_device *pdev)
1166 {
1167         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1168         struct mmc_omap_host *host = NULL;
1169         struct resource *res;
1170         int i, ret = 0;
1171         int irq;
1172
1173         if (pdata == NULL) {
1174                 dev_err(&pdev->dev, "platform data missing\n");
1175                 return -ENXIO;
1176         }
1177         if (pdata->nr_slots == 0) {
1178                 dev_err(&pdev->dev, "no slots\n");
1179                 return -ENXIO;
1180         }
1181
1182         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1183         irq = platform_get_irq(pdev, 0);
1184         if (res == NULL || irq < 0)
1185                 return -ENXIO;
1186
1187         res = request_mem_region(res->start, res->end - res->start + 1,
1188                                  pdev->name);
1189         if (res == NULL)
1190                 return -EBUSY;
1191
1192         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1193         if (host == NULL) {
1194                 ret = -ENOMEM;
1195                 goto err_free_mem_region;
1196         }
1197
1198         spin_lock_init(&host->dma_lock);
1199         init_timer(&host->dma_timer);
1200         spin_lock_init(&host->slot_lock);
1201         init_waitqueue_head(&host->slot_wq);
1202
1203         host->dma_timer.function = mmc_omap_dma_timer;
1204         host->dma_timer.data = (unsigned long) host;
1205
1206         host->pdata = pdata;
1207         host->dev = &pdev->dev;
1208         platform_set_drvdata(pdev, host);
1209
1210         host->id = pdev->id;
1211         host->mem_res = res;
1212         host->irq = irq;
1213
1214         host->use_dma = 1;
1215         host->dma_ch = -1;
1216
1217         host->irq = irq;
1218         host->phys_base = host->mem_res->start;
1219         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1220
1221         if (cpu_is_omap24xx()) {
1222                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1223                 if (IS_ERR(host->iclk))
1224                         goto err_free_mmc_host;
1225                 clk_enable(host->iclk);
1226         }
1227
1228         if (!cpu_is_omap24xx())
1229                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1230         else
1231                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1232
1233         if (IS_ERR(host->fclk)) {
1234                 ret = PTR_ERR(host->fclk);
1235                 goto err_free_iclk;
1236         }
1237
1238         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1239         if (ret)
1240                 goto err_free_fclk;
1241
1242         if (pdata->init != NULL) {
1243                 ret = pdata->init(&pdev->dev);
1244                 if (ret < 0)
1245                         goto err_free_irq;
1246         }
1247
1248         host->nr_slots = pdata->nr_slots;
1249         for (i = 0; i < pdata->nr_slots; i++) {
1250                 ret = mmc_omap_new_slot(host, i);
1251                 if (ret < 0) {
1252                         while (--i >= 0)
1253                                 mmc_omap_remove_slot(host->slots[i]);
1254
1255                         goto err_plat_cleanup;
1256                 }
1257         }
1258
1259         return 0;
1260
1261 err_plat_cleanup:
1262         if (pdata->cleanup)
1263                 pdata->cleanup(&pdev->dev);
1264 err_free_irq:
1265         free_irq(host->irq, host);
1266 err_free_fclk:
1267         clk_put(host->fclk);
1268 err_free_iclk:
1269         if (host->iclk != NULL) {
1270                 clk_disable(host->iclk);
1271                 clk_put(host->iclk);
1272         }
1273 err_free_mmc_host:
1274         kfree(host);
1275 err_free_mem_region:
1276         release_mem_region(res->start, res->end - res->start + 1);
1277         return ret;
1278 }
1279
1280 static int mmc_omap_remove(struct platform_device *pdev)
1281 {
1282         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1283         int i;
1284
1285         platform_set_drvdata(pdev, NULL);
1286
1287         BUG_ON(host == NULL);
1288
1289         for (i = 0; i < host->nr_slots; i++)
1290                 mmc_omap_remove_slot(host->slots[i]);
1291
1292         if (host->pdata->cleanup)
1293                 host->pdata->cleanup(&pdev->dev);
1294
1295         if (host->iclk && !IS_ERR(host->iclk))
1296                 clk_put(host->iclk);
1297         if (host->fclk && !IS_ERR(host->fclk))
1298                 clk_put(host->fclk);
1299
1300         release_mem_region(pdev->resource[0].start,
1301                            pdev->resource[0].end - pdev->resource[0].start + 1);
1302
1303         kfree(host);
1304
1305         return 0;
1306 }
1307
1308 #ifdef CONFIG_PM
1309 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1310 {
1311         int i, ret = 0;
1312         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1313
1314         if (host == NULL || host->suspended)
1315                 return 0;
1316
1317         for (i = 0; i < host->nr_slots; i++) {
1318                 struct mmc_omap_slot *slot;
1319
1320                 slot = host->slots[i];
1321                 ret = mmc_suspend_host(slot->mmc, mesg);
1322                 if (ret < 0) {
1323                         while (--i >= 0) {
1324                                 slot = host->slots[i];
1325                                 mmc_resume_host(slot->mmc);
1326                         }
1327                         return ret;
1328                 }
1329         }
1330         host->suspended = 1;
1331         return 0;
1332 }
1333
1334 static int mmc_omap_resume(struct platform_device *pdev)
1335 {
1336         int i, ret = 0;
1337         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1338
1339         if (host == NULL || !host->suspended)
1340                 return 0;
1341
1342         for (i = 0; i < host->nr_slots; i++) {
1343                 struct mmc_omap_slot *slot;
1344                 slot = host->slots[i];
1345                 ret = mmc_resume_host(slot->mmc);
1346                 if (ret < 0)
1347                         return ret;
1348
1349                 host->suspended = 0;
1350         }
1351         return 0;
1352 }
1353 #else
1354 #define mmc_omap_suspend        NULL
1355 #define mmc_omap_resume         NULL
1356 #endif
1357
1358 static struct platform_driver mmc_omap_driver = {
1359         .probe          = mmc_omap_probe,
1360         .remove         = mmc_omap_remove,
1361         .suspend        = mmc_omap_suspend,
1362         .resume         = mmc_omap_resume,
1363         .driver         = {
1364                 .name   = DRIVER_NAME,
1365                 .owner  = THIS_MODULE,
1366         },
1367 };
1368
1369 static int __init mmc_omap_init(void)
1370 {
1371         return platform_driver_register(&mmc_omap_driver);
1372 }
1373
1374 static void __exit mmc_omap_exit(void)
1375 {
1376         platform_driver_unregister(&mmc_omap_driver);
1377 }
1378
1379 module_init(mmc_omap_init);
1380 module_exit(mmc_omap_exit);
1381
1382 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1383 MODULE_LICENSE("GPL");
1384 MODULE_ALIAS("platform:" DRIVER_NAME);
1385 MODULE_AUTHOR("Juha Yrjölä");