drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/mmc.h>
  25 #include <linux/mmc/host.h>
  26 #include <linux/mmc/card.h>
  27 #include <linux/clk.h>
  28 #include <linux/scatterlist.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/mmc.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/dma.h>
  38 #include <asm/arch/mux.h>
  39 #include <asm/arch/fpga.h>
  40 #include <asm/arch/tps65010.h>
  41 #include <asm/arch/board-sx1.h>
  42
  43 #define OMAP_MMC_REG_CMD        0x00
  44 #define OMAP_MMC_REG_ARGL       0x04
  45 #define OMAP_MMC_REG_ARGH       0x08
  46 #define OMAP_MMC_REG_CON        0x0c
  47 #define OMAP_MMC_REG_STAT       0x10
  48 #define OMAP_MMC_REG_IE         0x14
  49 #define OMAP_MMC_REG_CTO        0x18
  50 #define OMAP_MMC_REG_DTO        0x1c
  51 #define OMAP_MMC_REG_DATA       0x20
  52 #define OMAP_MMC_REG_BLEN       0x24
  53 #define OMAP_MMC_REG_NBLK       0x28
  54 #define OMAP_MMC_REG_BUF        0x2c
  55 #define OMAP_MMC_REG_SDIO       0x34
  56 #define OMAP_MMC_REG_REV        0x3c
  57 #define OMAP_MMC_REG_RSP0       0x40
  58 #define OMAP_MMC_REG_RSP1       0x44
  59 #define OMAP_MMC_REG_RSP2       0x48
  60 #define OMAP_MMC_REG_RSP3       0x4c
  61 #define OMAP_MMC_REG_RSP4       0x50
  62 #define OMAP_MMC_REG_RSP5       0x54
  63 #define OMAP_MMC_REG_RSP6       0x58
  64 #define OMAP_MMC_REG_RSP7       0x5c
  65 #define OMAP_MMC_REG_IOSR       0x60
  66 #define OMAP_MMC_REG_SYSC       0x64
  67 #define OMAP_MMC_REG_SYSS       0x68
  68
  69 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  70 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  71 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  72 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  73 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  74 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  75 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  76 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  77 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  78 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  79 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  80 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  81 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  82
  83 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  84 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  85
  86 /*
  87  * Command types
  88  */
  89 #define OMAP_MMC_CMDTYPE_BC     0
  90 #define OMAP_MMC_CMDTYPE_BCR    1
  91 #define OMAP_MMC_CMDTYPE_AC     2
  92 #define OMAP_MMC_CMDTYPE_ADTC   3
  93
  94
  95 #define DRIVER_NAME "mmci-omap"
  96
  97 /* Specifies how often in millisecs to poll for card status changes
  98  * when the cover switch is open */
  99 #define OMAP_MMC_SWITCH_POLL_DELAY      500
 100
 101 struct mmc_omap_host;
 102
 103 struct mmc_omap_slot {
 104         int                     id;
 105         unsigned int            vdd;
 106         u16                     saved_con;
 107         u16                     bus_mode;
 108         unsigned int            fclk_freq;
 109         unsigned                powered:1;
 110
 111         struct work_struct      switch_work;
 112         struct timer_list       switch_timer;
 113         unsigned                cover_open;
 114
 115         struct mmc_request      *mrq;
 116         struct mmc_omap_host    *host;
 117         struct mmc_host         *mmc;
 118         struct omap_mmc_slot_data *pdata;
 119 };
 120
 121 struct mmc_omap_host {
 122         int                     initialized;
 123         int                     suspended;
 124         struct mmc_request *    mrq;
 125         struct mmc_command *    cmd;
 126         struct mmc_data *       data;
 127         struct mmc_host *       mmc;
 128         struct device *         dev;
 129         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 130         struct clk *            iclk;
 131         struct clk *            fclk;
 132         struct resource         *mem_res;
 133         void __iomem            *virt_base;
 134         unsigned int            phys_base;
 135         int                     irq;
 136         unsigned char           bus_mode;
 137         unsigned char           hw_bus_mode;
 138
 139         unsigned int            sg_len;
 140         int                     sg_idx;
 141         u16 *                   buffer;
 142         u32                     buffer_bytes_left;
 143         u32                     total_bytes_left;
 144
 145         unsigned                use_dma:1;
 146         unsigned                brs_received:1, dma_done:1;
 147         unsigned                dma_is_read:1;
 148         unsigned                dma_in_use:1;
 149         int                     dma_ch;
 150         spinlock_t              dma_lock;
 151         struct timer_list       dma_timer;
 152         unsigned                dma_len;
 153
 154         short                   power_pin;
 155
 156         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 157         struct mmc_omap_slot    *current_slot;
 158         spinlock_t              slot_lock;
 159         wait_queue_head_t       slot_wq;
 160         int                     nr_slots;
 161
 162         struct omap_mmc_platform_data *pdata;
 163 };
 164
 165 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 166 {
 167         struct mmc_omap_host *host = slot->host;
 168         unsigned long flags;
 169
 170         if (claimed)
 171                 goto no_claim;
 172         spin_lock_irqsave(&host->slot_lock, flags);
 173         while (host->mmc != NULL) {
 174                 spin_unlock_irqrestore(&host->slot_lock, flags);
 175                 wait_event(host->slot_wq, host->mmc == NULL);
 176                 spin_lock_irqsave(&host->slot_lock, flags);
 177         }
 178         host->mmc = slot->mmc;
 179         spin_unlock_irqrestore(&host->slot_lock, flags);
 180 no_claim:
 181         clk_enable(host->fclk);
 182         if (host->current_slot != slot) {
 183                 if (host->pdata->switch_slot != NULL)
 184                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 185                 host->current_slot = slot;
 186         }
 187
 188         /* Doing the dummy read here seems to work around some bug
 189          * at least in OMAP24xx silicon where the command would not
 190          * start after writing the CMD register. Sigh. */
 191         OMAP_MMC_READ(host, CON);
 192
 193         OMAP_MMC_WRITE(host, CON, slot->saved_con);
 194 }
 195
 196 static void mmc_omap_start_request(struct mmc_omap_host *host,
 197                                    struct mmc_request *req);
 198
 199 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
 200 {
 201         struct mmc_omap_host *host = slot->host;
 202         unsigned long flags;
 203         int i;
 204
 205         BUG_ON(slot == NULL || host->mmc == NULL);
 206         clk_disable(host->fclk);
 207
 208         spin_lock_irqsave(&host->slot_lock, flags);
 209         /* Check for any pending requests */
 210         for (i = 0; i < host->nr_slots; i++) {
 211                 struct mmc_omap_slot *new_slot;
 212                 struct mmc_request *rq;
 213
 214                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 215                         continue;
 216
 217                 new_slot = host->slots[i];
 218                 /* The current slot should not have a request in queue */
 219                 BUG_ON(new_slot == host->current_slot);
 220
 221                 host->mmc = new_slot->mmc;
 222                 spin_unlock_irqrestore(&host->slot_lock, flags);
 223                 mmc_omap_select_slot(new_slot, 1);
 224                 rq = new_slot->mrq;
 225                 new_slot->mrq = NULL;
 226                 mmc_omap_start_request(host, rq);
 227                 return;
 228         }
 229
 230         host->mmc = NULL;
 231         wake_up(&host->slot_wq);
 232         spin_unlock_irqrestore(&host->slot_lock, flags);
 233 }
 234
 235 static inline
 236 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 237 {
 238         return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
 239 }
 240
 241 static ssize_t
 242 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 243                            char *buf)
 244 {
 245         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 246         struct mmc_omap_slot *slot = mmc_priv(mmc);
 247
 248         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 249                        "closed");
 250 }
 251
 252 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 253
 254 /* Access to the R/O switch is required for production testing
 255  * purposes. */
 256 static ssize_t
 257 mmc_omap_show_ro(struct device *dev, struct device_attribute *attr, char *buf)
 258 {
 259         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 260         struct mmc_omap_slot *slot = mmc_priv(mmc);
 261
 262         return sprintf(buf, "%d\n", slot->pdata->get_ro(mmc_dev(mmc),
 263                                                         slot->id));
 264 }
 265
 266 static DEVICE_ATTR(ro, S_IRUGO, mmc_omap_show_ro, NULL);
 267
 268 static ssize_t
 269 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 270                         char *buf)
 271 {
 272         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 273         struct mmc_omap_slot *slot = mmc_priv(mmc);
 274
 275         return sprintf(buf, "%s\n", slot->pdata->name);
 276 }
 277
 278 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 279
 280 static void
 281 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 282 {
 283         u32 cmdreg;
 284         u32 resptype;
 285         u32 cmdtype;
 286
 287         host->cmd = cmd;
 288
 289         resptype = 0;
 290         cmdtype = 0;
 291
 292         /* Our hardware needs to know exact type */
 293         switch (mmc_resp_type(cmd)) {
 294         case MMC_RSP_NONE:
 295                 break;
 296         case MMC_RSP_R1:
 297         case MMC_RSP_R1B:
 298                 /* resp 1, 1b, 6, 7 */
 299                 resptype = 1;
 300                 break;
 301         case MMC_RSP_R2:
 302                 resptype = 2;
 303                 break;
 304         case MMC_RSP_R3:
 305                 resptype = 3;
 306                 break;
 307         default:
 308                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 309                 break;
 310         }
 311
 312         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 313                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 314         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 315                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 316         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 317                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 318         } else {
 319                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 320         }
 321
 322         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 323
 324         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 325                 cmdreg |= 1 << 6;
 326
 327         if (cmd->flags & MMC_RSP_BUSY)
 328                 cmdreg |= 1 << 11;
 329
 330         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 331                 cmdreg |= 1 << 15;
 332
 333         OMAP_MMC_WRITE(host, CTO, 200);
 334         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 335         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 336         OMAP_MMC_WRITE(host, IE,
 337                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 338                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 339                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 340                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 341                        OMAP_MMC_STAT_END_OF_DATA);
 342         OMAP_MMC_WRITE(host, CMD, cmdreg);
 343 }
 344
 345 static void
 346 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 347                      int abort)
 348 {
 349         enum dma_data_direction dma_data_dir;
 350
 351         BUG_ON(host->dma_ch < 0);
 352         if (data->error)
 353                 omap_stop_dma(host->dma_ch);
 354         /* Release DMA channel lazily */
 355         mod_timer(&host->dma_timer, jiffies + HZ);
 356         if (data->flags & MMC_DATA_WRITE)
 357                 dma_data_dir = DMA_TO_DEVICE;
 358         else
 359                 dma_data_dir = DMA_FROM_DEVICE;
 360         dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 361                      dma_data_dir);
 362 }
 363
 364 static void
 365 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 366 {
 367         if (host->dma_in_use)
 368                 mmc_omap_release_dma(host, data, data->error);
 369
 370         host->data = NULL;
 371         host->sg_len = 0;
 372
 373         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 374          * dozens of requests until the card finishes writing data.
 375          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 376          */
 377
 378         if (!data->stop) {
 379                 struct mmc_host *mmc;
 380
 381                 host->mrq = NULL;
 382                 mmc = host->mmc;
 383                 mmc_omap_release_slot(host->current_slot);
 384                 mmc_request_done(mmc, data->mrq);
 385                 return;
 386         }
 387
 388         mmc_omap_start_command(host, data->stop);
 389 }
 390
 391 static void
 392 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 393 {
 394         int loops;
 395         u16 ie;
 396
 397         if (host->dma_in_use)
 398                 mmc_omap_release_dma(host, data, 1);
 399
 400         host->data = NULL;
 401         host->sg_len = 0;
 402
 403         ie = OMAP_MMC_READ(host, IE);
 404         OMAP_MMC_WRITE(host, IE, 0);
 405         OMAP_MMC_WRITE(host, CMD, 1 << 7);
 406         loops = 0;
 407         while (!(OMAP_MMC_READ(host, STAT) & OMAP_MMC_STAT_END_OF_CMD)) {
 408                 udelay(1);
 409                 loops++;
 410                 if (loops == 100000)
 411                         break;
 412         }
 413         OMAP_MMC_WRITE(host, STAT, OMAP_MMC_STAT_END_OF_CMD);
 414         OMAP_MMC_WRITE(host, IE, ie);
 415 }
 416
 417 static void
 418 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 419 {
 420         unsigned long flags;
 421         int done;
 422
 423         if (!host->dma_in_use) {
 424                 mmc_omap_xfer_done(host, data);
 425                 return;
 426         }
 427         done = 0;
 428         spin_lock_irqsave(&host->dma_lock, flags);
 429         if (host->dma_done)
 430                 done = 1;
 431         else
 432                 host->brs_received = 1;
 433         spin_unlock_irqrestore(&host->dma_lock, flags);
 434         if (done)
 435                 mmc_omap_xfer_done(host, data);
 436 }
 437
 438 static void
 439 mmc_omap_dma_timer(unsigned long data)
 440 {
 441         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 442
 443         BUG_ON(host->dma_ch < 0);
 444         omap_free_dma(host->dma_ch);
 445         host->dma_ch = -1;
 446 }
 447
 448 static void
 449 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 450 {
 451         unsigned long flags;
 452         int done;
 453
 454         done = 0;
 455         spin_lock_irqsave(&host->dma_lock, flags);
 456         if (host->brs_received)
 457                 done = 1;
 458         else
 459                 host->dma_done = 1;
 460         spin_unlock_irqrestore(&host->dma_lock, flags);
 461         if (done)
 462                 mmc_omap_xfer_done(host, data);
 463 }
 464
 465 static void
 466 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 467 {
 468         host->cmd = NULL;
 469
 470         if (cmd->flags & MMC_RSP_PRESENT) {
 471                 if (cmd->flags & MMC_RSP_136) {
 472                         /* response type 2 */
 473                         cmd->resp[3] =
 474                                 OMAP_MMC_READ(host, RSP0) |
 475                                 (OMAP_MMC_READ(host, RSP1) << 16);
 476                         cmd->resp[2] =
 477                                 OMAP_MMC_READ(host, RSP2) |
 478                                 (OMAP_MMC_READ(host, RSP3) << 16);
 479                         cmd->resp[1] =
 480                                 OMAP_MMC_READ(host, RSP4) |
 481                                 (OMAP_MMC_READ(host, RSP5) << 16);
 482                         cmd->resp[0] =
 483                                 OMAP_MMC_READ(host, RSP6) |
 484                                 (OMAP_MMC_READ(host, RSP7) << 16);
 485                 } else {
 486                         /* response types 1, 1b, 3, 4, 5, 6 */
 487                         cmd->resp[0] =
 488                                 OMAP_MMC_READ(host, RSP6) |
 489                                 (OMAP_MMC_READ(host, RSP7) << 16);
 490                 }
 491         }
 492
 493         if (host->data == NULL || cmd->error) {
 494                 struct mmc_host *mmc;
 495
 496                 if (host->data != NULL)
 497                         mmc_omap_abort_xfer(host, host->data);
 498                 host->mrq = NULL;
 499                 mmc = host->mmc;
 500                 mmc_omap_release_slot(host->current_slot);
 501                 mmc_request_done(mmc, cmd->mrq);
 502         }
 503 }
 504
 505 /* PIO only */
 506 static void
 507 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 508 {
 509         struct scatterlist *sg;
 510
 511         sg = host->data->sg + host->sg_idx;
 512         host->buffer_bytes_left = sg->length;
 513         host->buffer = sg_virt(sg);
 514         if (host->buffer_bytes_left > host->total_bytes_left)
 515                 host->buffer_bytes_left = host->total_bytes_left;
 516 }
 517
 518 /* PIO only */
 519 static void
 520 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 521 {
 522         int n;
 523
 524         if (host->buffer_bytes_left == 0) {
 525                 host->sg_idx++;
 526                 BUG_ON(host->sg_idx == host->sg_len);
 527                 mmc_omap_sg_to_buf(host);
 528         }
 529         n = 64;
 530         if (n > host->buffer_bytes_left)
 531                 n = host->buffer_bytes_left;
 532         host->buffer_bytes_left -= n;
 533         host->total_bytes_left -= n;
 534         host->data->bytes_xfered += n;
 535
 536         if (write) {
 537                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 538         } else {
 539                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 540         }
 541 }
 542
 543 static inline void mmc_omap_report_irq(u16 status)
 544 {
 545         static const char *mmc_omap_status_bits[] = {
 546                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 547                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 548         };
 549         int i, c = 0;
 550
 551         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 552                 if (status & (1 << i)) {
 553                         if (c)
 554                                 printk(" ");
 555                         printk("%s", mmc_omap_status_bits[i]);
 556                         c++;
 557                 }
 558 }
 559
 560 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 561 {
 562         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 563         u16 status;
 564         int end_command;
 565         int end_transfer;
 566         int transfer_error, cmd_error;
 567
 568         if (host->cmd == NULL && host->data == NULL) {
 569                 status = OMAP_MMC_READ(host, STAT);
 570                 dev_info(mmc_dev(host->slots[0]->mmc),
 571                          "Spurious IRQ 0x%04x\n", status);
 572                 if (status != 0) {
 573                         OMAP_MMC_WRITE(host, STAT, status);
 574                         OMAP_MMC_WRITE(host, IE, 0);
 575                 }
 576                 return IRQ_HANDLED;
 577         }
 578
 579         end_command = 0;
 580         end_transfer = 0;
 581         transfer_error = 0;
 582         cmd_error = 0;
 583
 584         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 585                 int cmd;
 586
 587                 OMAP_MMC_WRITE(host, STAT, status);
 588                 if (host->cmd != NULL)
 589                         cmd = host->cmd->opcode;
 590                 else
 591                         cmd = -1;
 592 #ifdef CONFIG_MMC_DEBUG
 593                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 594                         status, cmd);
 595                 mmc_omap_report_irq(status);
 596                 printk("\n");
 597 #endif
 598                 if (host->total_bytes_left) {
 599                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 600                             (status & OMAP_MMC_STAT_END_OF_DATA))
 601                                 mmc_omap_xfer_data(host, 0);
 602                         if (status & OMAP_MMC_STAT_A_EMPTY)
 603                                 mmc_omap_xfer_data(host, 1);
 604                 }
 605
 606                 if (status & OMAP_MMC_STAT_END_OF_DATA)
 607                         end_transfer = 1;
 608
 609                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 610                         dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
 611                                 cmd);
 612                         if (host->data) {
 613                                 host->data->error = -ETIMEDOUT;
 614                                 transfer_error = 1;
 615                         }
 616                 }
 617
 618                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 619                         if (host->data) {
 620                                 host->data->error = -EILSEQ;
 621                                 dev_dbg(mmc_dev(host->mmc),
 622                                          "data CRC error, bytes left %d\n",
 623                                         host->total_bytes_left);
 624                                 transfer_error = 1;
 625                         } else {
 626                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 627                         }
 628                 }
 629
 630                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 631                         /* Timeouts are routine with some commands */
 632                         if (host->cmd) {
 633                                 struct mmc_omap_slot *slot =
 634                                         host->current_slot;
 635                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 636                                     host->cmd->opcode != MMC_SEND_OP_COND &&
 637                                     host->cmd->opcode != MMC_APP_CMD &&
 638                                     (slot == NULL ||
 639                                      !mmc_omap_cover_is_open(slot)))
 640                                         dev_err(mmc_dev(host->mmc),
 641                                                 "command timeout (CMD%d)\n",
 642                                                 cmd);
 643                                 host->cmd->error = -ETIMEDOUT;
 644                                 end_command = 1;
 645                                 cmd_error = 1;
 646                         }
 647                 }
 648
 649                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 650                         if (host->cmd) {
 651                                 dev_err(mmc_dev(host->mmc),
 652                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 653                                         cmd, host->cmd->arg);
 654                                 host->cmd->error = -EILSEQ;
 655                                 end_command = 1;
 656                                 cmd_error = 1;
 657                         } else
 658                                 dev_err(mmc_dev(host->mmc),
 659                                         "command CRC error without cmd?\n");
 660                 }
 661
 662                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 663                         dev_dbg(mmc_dev(host->mmc),
 664                                 "ignoring card status error (CMD%d)\n",
 665                                 cmd);
 666                         end_command = 1;
 667                 }
 668
 669                 /*
 670                  * NOTE: On 1610 the END_OF_CMD may come too early when
 671                  * starting a write
 672                  */
 673                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 674                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 675                         end_command = 1;
 676                 }
 677         }
 678
 679         if (end_command)
 680                 mmc_omap_cmd_done(host, host->cmd);
 681         if (host->data != NULL) {
 682                 if (transfer_error)
 683                         mmc_omap_xfer_done(host, host->data);
 684                 else if (end_transfer)
 685                         mmc_omap_end_of_data(host, host->data);
 686         }
 687
 688         return IRQ_HANDLED;
 689 }
 690
 691 void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed)
 692 {
 693         struct mmc_omap_host *host = dev_get_drvdata(dev);
 694
 695         BUG_ON(slot >= host->nr_slots);
 696
 697         /* Other subsystems can call in here before we're initialised. */
 698         if (host->nr_slots == 0 || !host->slots[slot])
 699                 return;
 700
 701         schedule_work(&host->slots[slot]->switch_work);
 702 }
 703
 704 static void mmc_omap_switch_timer(unsigned long arg)
 705 {
 706         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 707
 708         schedule_work(&slot->switch_work);
 709 }
 710
 711 static void mmc_omap_cover_handler(struct work_struct *work)
 712 {
 713         struct mmc_omap_slot *slot = container_of(work, struct mmc_omap_slot,
 714                                                   switch_work);
 715         int cover_open;
 716
 717         cover_open = mmc_omap_cover_is_open(slot);
 718         if (cover_open != slot->cover_open) {
 719                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 720                 slot->cover_open = cover_open;
 721                 dev_info(mmc_dev(slot->mmc), "cover is now %s\n",
 722                          cover_open ? "open" : "closed");
 723         }
 724         mmc_detect_change(slot->mmc, slot->id);
 725 }
 726
 727 /* Prepare to transfer the next segment of a scatterlist */
 728 static void
 729 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 730 {
 731         int dma_ch = host->dma_ch;
 732         unsigned long data_addr;
 733         u16 buf, frame;
 734         u32 count;
 735         struct scatterlist *sg = &data->sg[host->sg_idx];
 736         int src_port = 0;
 737         int dst_port = 0;
 738         int sync_dev = 0;
 739
 740         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 741         frame = data->blksz;
 742         count = sg_dma_len(sg);
 743
 744         if ((data->blocks == 1) && (count > data->blksz))
 745                 count = frame;
 746
 747         host->dma_len = count;
 748
 749         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 750          * Use 16 or 32 word frames when the blocksize is at least that large.
 751          * Blocksize is usually 512 bytes; but not for some SD reads.
 752          */
 753         if (cpu_is_omap15xx() && frame > 32)
 754                 frame = 32;
 755         else if (frame > 64)
 756                 frame = 64;
 757         count /= frame;
 758         frame >>= 1;
 759
 760         if (!(data->flags & MMC_DATA_WRITE)) {
 761                 buf = 0x800f | ((frame - 1) << 8);
 762
 763                 if (cpu_class_is_omap1()) {
 764                         src_port = OMAP_DMA_PORT_TIPB;
 765                         dst_port = OMAP_DMA_PORT_EMIFF;
 766                 }
 767                 if (cpu_is_omap24xx())
 768                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 769
 770                 omap_set_dma_src_params(dma_ch, src_port,
 771                                         OMAP_DMA_AMODE_CONSTANT,
 772                                         data_addr, 0, 0);
 773                 omap_set_dma_dest_params(dma_ch, dst_port,
 774                                          OMAP_DMA_AMODE_POST_INC,
 775                                          sg_dma_address(sg), 0, 0);
 776                 omap_set_dma_dest_data_pack(dma_ch, 1);
 777                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 778         } else {
 779                 buf = 0x0f80 | ((frame - 1) << 0);
 780
 781                 if (cpu_class_is_omap1()) {
 782                         src_port = OMAP_DMA_PORT_EMIFF;
 783                         dst_port = OMAP_DMA_PORT_TIPB;
 784                 }
 785                 if (cpu_is_omap24xx())
 786                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 787
 788                 omap_set_dma_dest_params(dma_ch, dst_port,
 789                                          OMAP_DMA_AMODE_CONSTANT,
 790                                          data_addr, 0, 0);
 791                 omap_set_dma_src_params(dma_ch, src_port,
 792                                         OMAP_DMA_AMODE_POST_INC,
 793                                         sg_dma_address(sg), 0, 0);
 794                 omap_set_dma_src_data_pack(dma_ch, 1);
 795                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 796         }
 797
 798         /* Max limit for DMA frame count is 0xffff */
 799         BUG_ON(count > 0xffff);
 800
 801         OMAP_MMC_WRITE(host, BUF, buf);
 802         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 803                                      frame, count, OMAP_DMA_SYNC_FRAME,
 804                                      sync_dev, 0);
 805 }
 806
 807 /* A scatterlist segment completed */
 808 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 809 {
 810         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 811         struct mmc_data *mmcdat = host->data;
 812
 813         if (unlikely(host->dma_ch < 0)) {
 814                 dev_err(mmc_dev(host->mmc),
 815                         "DMA callback while DMA not enabled\n");
 816                 return;
 817         }
 818         /* FIXME: We really should do something to _handle_ the errors */
 819         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 820                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 821                 return;
 822         }
 823         if (ch_status & OMAP_DMA_DROP_IRQ) {
 824                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 825                 return;
 826         }
 827         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 828                 return;
 829         }
 830         mmcdat->bytes_xfered += host->dma_len;
 831         host->sg_idx++;
 832         if (host->sg_idx < host->sg_len) {
 833                 mmc_omap_prepare_dma(host, host->data);
 834                 omap_start_dma(host->dma_ch);
 835         } else
 836                 mmc_omap_dma_done(host, host->data);
 837 }
 838
 839 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 840 {
 841         const char *dev_name;
 842         int sync_dev, dma_ch, is_read, r;
 843
 844         is_read = !(data->flags & MMC_DATA_WRITE);
 845         del_timer_sync(&host->dma_timer);
 846         if (host->dma_ch >= 0) {
 847                 if (is_read == host->dma_is_read)
 848                         return 0;
 849                 omap_free_dma(host->dma_ch);
 850                 host->dma_ch = -1;
 851         }
 852
 853         if (is_read) {
 854                 if (host->id == 1) {
 855                         sync_dev = OMAP_DMA_MMC_RX;
 856                         dev_name = "MMC1 read";
 857                 } else {
 858                         sync_dev = OMAP_DMA_MMC2_RX;
 859                         dev_name = "MMC2 read";
 860                 }
 861         } else {
 862                 if (host->id == 1) {
 863                         sync_dev = OMAP_DMA_MMC_TX;
 864                         dev_name = "MMC1 write";
 865                 } else {
 866                         sync_dev = OMAP_DMA_MMC2_TX;
 867                         dev_name = "MMC2 write";
 868                 }
 869         }
 870         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 871                              host, &dma_ch);
 872         if (r != 0) {
 873                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 874                 return r;
 875         }
 876         host->dma_ch = dma_ch;
 877         host->dma_is_read = is_read;
 878
 879         return 0;
 880 }
 881
 882 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 883 {
 884         u16 reg;
 885
 886         reg = OMAP_MMC_READ(host, SDIO);
 887         reg &= ~(1 << 5);
 888         OMAP_MMC_WRITE(host, SDIO, reg);
 889         /* Set maximum timeout */
 890         OMAP_MMC_WRITE(host, CTO, 0xff);
 891 }
 892
 893 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 894 {
 895         unsigned int timeout, cycle_ns;
 896         u16 reg;
 897
 898         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
 899         timeout = req->data->timeout_ns / cycle_ns;
 900         timeout += req->data->timeout_clks;
 901
 902         /* Check if we need to use timeout multiplier register */
 903         reg = OMAP_MMC_READ(host, SDIO);
 904         if (timeout > 0xffff) {
 905                 reg |= (1 << 5);
 906                 timeout /= 1024;
 907         } else
 908                 reg &= ~(1 << 5);
 909         OMAP_MMC_WRITE(host, SDIO, reg);
 910         OMAP_MMC_WRITE(host, DTO, timeout);
 911 }
 912
 913 static void
 914 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 915 {
 916         struct mmc_data *data = req->data;
 917         int i, use_dma, block_size;
 918         unsigned sg_len;
 919
 920         host->data = data;
 921         if (data == NULL) {
 922                 OMAP_MMC_WRITE(host, BLEN, 0);
 923                 OMAP_MMC_WRITE(host, NBLK, 0);
 924                 OMAP_MMC_WRITE(host, BUF, 0);
 925                 host->dma_in_use = 0;
 926                 set_cmd_timeout(host, req);
 927                 return;
 928         }
 929
 930         block_size = data->blksz;
 931
 932         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 933         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 934         set_data_timeout(host, req);
 935
 936         /* cope with calling layer confusion; it issues "single
 937          * block" writes using multi-block scatterlists.
 938          */
 939         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 940
 941         /* Only do DMA for entire blocks */
 942         use_dma = host->use_dma;
 943         if (use_dma) {
 944                 for (i = 0; i < sg_len; i++) {
 945                         if ((data->sg[i].length % block_size) != 0) {
 946                                 use_dma = 0;
 947                                 break;
 948                         }
 949                 }
 950         }
 951
 952         host->sg_idx = 0;
 953         if (use_dma) {
 954                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 955                         enum dma_data_direction dma_data_dir;
 956
 957                         if (data->flags & MMC_DATA_WRITE)
 958                                 dma_data_dir = DMA_TO_DEVICE;
 959                         else
 960                                 dma_data_dir = DMA_FROM_DEVICE;
 961
 962                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 963                                                 sg_len, dma_data_dir);
 964                         host->total_bytes_left = 0;
 965                         mmc_omap_prepare_dma(host, req->data);
 966                         host->brs_received = 0;
 967                         host->dma_done = 0;
 968                         host->dma_in_use = 1;
 969                 } else
 970                         use_dma = 0;
 971         }
 972
 973         /* Revert to PIO? */
 974         if (!use_dma) {
 975                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 976                 host->total_bytes_left = data->blocks * block_size;
 977                 host->sg_len = sg_len;
 978                 mmc_omap_sg_to_buf(host);
 979                 host->dma_in_use = 0;
 980         }
 981 }
 982
 983 static void mmc_omap_start_request(struct mmc_omap_host *host,
 984                                    struct mmc_request *req)
 985 {
 986         BUG_ON(host->mrq != NULL);
 987
 988         host->mrq = req;
 989
 990         /* only touch fifo AFTER the controller readies it */
 991         mmc_omap_prepare_data(host, req);
 992         mmc_omap_start_command(host, req->cmd);
 993         if (host->dma_in_use)
 994                 omap_start_dma(host->dma_ch);
 995         BUG_ON(irqs_disabled());
 996 }
 997
 998 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 999 {
1000         struct mmc_omap_slot *slot = mmc_priv(mmc);
1001         struct mmc_omap_host *host = slot->host;
1002         unsigned long flags;
1003
1004         spin_lock_irqsave(&host->slot_lock, flags);
1005         if (host->mmc != NULL) {
1006                 BUG_ON(slot->mrq != NULL);
1007                 slot->mrq = req;
1008                 spin_unlock_irqrestore(&host->slot_lock, flags);
1009                 return;
1010         } else
1011                 host->mmc = mmc;
1012         spin_unlock_irqrestore(&host->slot_lock, flags);
1013         mmc_omap_select_slot(slot, 1);
1014         mmc_omap_start_request(host, req);
1015 }
1016
1017 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1018                                 int vdd)
1019 {
1020         struct mmc_omap_host *host;
1021
1022         host = slot->host;
1023
1024         if (slot->pdata->set_power != NULL)
1025                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1026                                         vdd);
1027
1028         if (cpu_is_omap24xx()) {
1029                 u16 w;
1030
1031                 if (power_on) {
1032                         w = OMAP_MMC_READ(host, CON);
1033                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1034                 } else {
1035                         w = OMAP_MMC_READ(host, CON);
1036                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1037                 }
1038         }
1039 }
1040
1041 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1042 {
1043         struct mmc_omap_slot *slot = mmc_priv(mmc);
1044         struct mmc_omap_host *host = slot->host;
1045         int func_clk_rate = clk_get_rate(host->fclk);
1046         int dsor;
1047
1048         if (ios->clock == 0)
1049                 return 0;
1050
1051         dsor = func_clk_rate / ios->clock;
1052         if (dsor < 1)
1053                 dsor = 1;
1054
1055         if (func_clk_rate / dsor > ios->clock)
1056                 dsor++;
1057
1058         if (dsor > 250)
1059                 dsor = 250;
1060
1061         slot->fclk_freq = func_clk_rate / dsor;
1062
1063         if (ios->bus_width == MMC_BUS_WIDTH_4)
1064                 dsor |= 1 << 15;
1065
1066         return dsor;
1067 }
1068
1069 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1070 {
1071         struct mmc_omap_slot *slot = mmc_priv(mmc);
1072         struct mmc_omap_host *host = slot->host;
1073         int i, dsor;
1074
1075         dsor = mmc_omap_calc_divisor(mmc, ios);
1076
1077         mmc_omap_select_slot(slot, 0);
1078
1079         if (ios->vdd != slot->vdd)
1080                 slot->vdd = ios->vdd;
1081
1082         switch (ios->power_mode) {
1083         case MMC_POWER_OFF:
1084                 mmc_omap_set_power(slot, 0, ios->vdd);
1085                 break;
1086         case MMC_POWER_UP:
1087                 /* Cannot touch dsor yet, just power up MMC */
1088                 mmc_omap_set_power(slot, 1, ios->vdd);
1089                 goto exit;
1090         case MMC_POWER_ON:
1091                 dsor |= 1 << 11;
1092                 break;
1093         }
1094
1095         if (slot->bus_mode != ios->bus_mode) {
1096                 if (slot->pdata->set_bus_mode != NULL)
1097                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1098                                                   ios->bus_mode);
1099                 slot->bus_mode = ios->bus_mode;
1100         }
1101
1102         /* On insanely high arm_per frequencies something sometimes
1103          * goes somehow out of sync, and the POW bit is not being set,
1104          * which results in the while loop below getting stuck.
1105          * Writing to the CON register twice seems to do the trick. */
1106         for (i = 0; i < 2; i++)
1107                 OMAP_MMC_WRITE(host, CON, dsor);
1108         slot->saved_con = dsor;
1109         if (ios->power_mode == MMC_POWER_ON) {
1110                 /* Send clock cycles, poll completion */
1111                 OMAP_MMC_WRITE(host, IE, 0);
1112                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1113                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1114                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1115                 OMAP_MMC_WRITE(host, STAT, 1);
1116         }
1117
1118 exit:
1119         mmc_omap_release_slot(slot);
1120 }
1121
1122 static int mmc_omap_get_ro(struct mmc_host *mmc)
1123 {
1124         struct mmc_omap_slot *slot = mmc_priv(mmc);
1125
1126         if (slot->pdata->get_ro != NULL)
1127                 return slot->pdata->get_ro(mmc_dev(mmc), slot->id);
1128         return 0;
1129 }
1130
1131 static const struct mmc_host_ops mmc_omap_ops = {
1132         .request        = mmc_omap_request,
1133         .set_ios        = mmc_omap_set_ios,
1134         .get_ro         = mmc_omap_get_ro,
1135 };
1136
1137 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1138 {
1139         struct mmc_omap_slot *slot = NULL;
1140         struct mmc_host *mmc;
1141         int r;
1142
1143         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1144         if (mmc == NULL)
1145                 return -ENOMEM;
1146
1147         slot = mmc_priv(mmc);
1148         slot->host = host;
1149         slot->mmc = mmc;
1150         slot->id = id;
1151         slot->pdata = &host->pdata->slots[id];
1152
1153         host->slots[id] = slot;
1154
1155         mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
1156                     MMC_CAP_SD_HIGHSPEED;
1157         if (host->pdata->conf.wire4)
1158                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1159
1160         mmc->ops = &mmc_omap_ops;
1161         mmc->f_min = 400000;
1162
1163         if (cpu_class_is_omap2())
1164                 mmc->f_max = 48000000;
1165         else
1166                 mmc->f_max = 24000000;
1167         if (host->pdata->max_freq)
1168                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1169         mmc->ocr_avail = slot->pdata->ocr_mask;
1170
1171         /* Use scatterlist DMA to reduce per-transfer costs.
1172          * NOTE max_seg_size assumption that small blocks aren't
1173          * normally used (except e.g. for reading SD registers).
1174          */
1175         mmc->max_phys_segs = 32;
1176         mmc->max_hw_segs = 32;
1177         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1178         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1179         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1180         mmc->max_seg_size = mmc->max_req_size;
1181
1182         r = mmc_add_host(mmc);
1183         if (r < 0)
1184                 return r;
1185
1186         if (slot->pdata->name != NULL) {
1187                 r = device_create_file(&mmc->class_dev,
1188                                         &dev_attr_slot_name);
1189                 if (r < 0)
1190                         goto err_remove_host;
1191         }
1192
1193         if (slot->pdata->get_cover_state != NULL) {
1194                 r = device_create_file(&mmc->class_dev,
1195                                         &dev_attr_cover_switch);
1196                 if (r < 0)
1197                         goto err_remove_slot_name;
1198
1199                 INIT_WORK(&slot->switch_work, mmc_omap_cover_handler);
1200                 init_timer(&slot->switch_timer);
1201                 slot->switch_timer.function = mmc_omap_switch_timer;
1202                 slot->switch_timer.data = (unsigned long) slot;
1203                 schedule_work(&slot->switch_work);
1204         }
1205
1206         if (slot->pdata->get_ro != NULL) {
1207                 r = device_create_file(&mmc->class_dev,
1208                                         &dev_attr_ro);
1209                 if (r < 0)
1210                         goto err_remove_cover_attr;
1211         }
1212
1213         return 0;
1214
1215 err_remove_cover_attr:
1216         if (slot->pdata->get_cover_state != NULL)
1217                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1218 err_remove_slot_name:
1219         if (slot->pdata->name != NULL)
1220                 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1221 err_remove_host:
1222         mmc_remove_host(mmc);
1223         return r;
1224 }
1225
1226 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1227 {
1228         struct mmc_host *mmc = slot->mmc;
1229
1230         if (slot->pdata->name != NULL)
1231                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1232         if (slot->pdata->get_cover_state != NULL)
1233                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1234         if (slot->pdata->get_ro != NULL)
1235                 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1236
1237         del_timer_sync(&slot->switch_timer);
1238         flush_scheduled_work();
1239
1240         mmc_remove_host(mmc);
1241         mmc_free_host(mmc);
1242 }
1243
1244 static int __init mmc_omap_probe(struct platform_device *pdev)
1245 {
1246         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1247         struct mmc_omap_host *host = NULL;
1248         struct resource *res;
1249         int i, ret = 0;
1250         int irq;
1251
1252         if (pdata == NULL) {
1253                 dev_err(&pdev->dev, "platform data missing\n");
1254                 return -ENXIO;
1255         }
1256         if (pdata->nr_slots == 0) {
1257                 dev_err(&pdev->dev, "no slots\n");
1258                 return -ENXIO;
1259         }
1260
1261         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1262         irq = platform_get_irq(pdev, 0);
1263         if (res == NULL || irq < 0)
1264                 return -ENXIO;
1265
1266         res = request_mem_region(res->start, res->end - res->start + 1,
1267                                  pdev->name);
1268         if (res == NULL)
1269                 return -EBUSY;
1270
1271         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1272         if (host == NULL) {
1273                 ret = -ENOMEM;
1274                 goto err_free_mem_region;
1275         }
1276
1277         spin_lock_init(&host->dma_lock);
1278         init_timer(&host->dma_timer);
1279         spin_lock_init(&host->slot_lock);
1280         init_waitqueue_head(&host->slot_wq);
1281
1282         host->dma_timer.function = mmc_omap_dma_timer;
1283         host->dma_timer.data = (unsigned long) host;
1284
1285         host->pdata = pdata;
1286         host->dev = &pdev->dev;
1287         platform_set_drvdata(pdev, host);
1288
1289         host->id = pdev->id;
1290         host->mem_res = res;
1291         host->irq = irq;
1292
1293         host->use_dma = 1;
1294         host->dma_ch = -1;
1295
1296         host->irq = irq;
1297         host->phys_base = host->mem_res->start;
1298         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1299
1300         if (cpu_is_omap24xx()) {
1301                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1302                 if (IS_ERR(host->iclk))
1303                         goto err_free_mmc_host;
1304                 clk_enable(host->iclk);
1305         }
1306
1307         if (!cpu_is_omap24xx())
1308                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1309         else
1310                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1311
1312         if (IS_ERR(host->fclk)) {
1313                 ret = PTR_ERR(host->fclk);
1314                 goto err_free_iclk;
1315         }
1316
1317         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1318         if (ret)
1319                 goto err_free_fclk;
1320
1321         if (pdata->init != NULL) {
1322                 ret = pdata->init(&pdev->dev);
1323                 if (ret < 0)
1324                         goto err_free_irq;
1325         }
1326
1327         host->nr_slots = pdata->nr_slots;
1328         for (i = 0; i < pdata->nr_slots; i++) {
1329                 ret = mmc_omap_new_slot(host, i);
1330                 if (ret < 0) {
1331                         while (--i >= 0)
1332                                 mmc_omap_remove_slot(host->slots[i]);
1333
1334                         goto err_plat_cleanup;
1335                 }
1336         }
1337
1338         return 0;
1339
1340 err_plat_cleanup:
1341         if (pdata->cleanup)
1342                 pdata->cleanup(&pdev->dev);
1343 err_free_irq:
1344         free_irq(host->irq, host);
1345 err_free_fclk:
1346         clk_put(host->fclk);
1347 err_free_iclk:
1348         if (host->iclk != NULL) {
1349                 clk_disable(host->iclk);
1350                 clk_put(host->iclk);
1351         }
1352 err_free_mmc_host:
1353         kfree(host);
1354 err_free_mem_region:
1355         release_mem_region(res->start, res->end - res->start + 1);
1356         return ret;
1357 }
1358
1359 static int mmc_omap_remove(struct platform_device *pdev)
1360 {
1361         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1362         int i;
1363
1364         platform_set_drvdata(pdev, NULL);
1365
1366         BUG_ON(host == NULL);
1367
1368         for (i = 0; i < host->nr_slots; i++)
1369                 mmc_omap_remove_slot(host->slots[i]);
1370
1371         if (host->pdata->cleanup)
1372                 host->pdata->cleanup(&pdev->dev);
1373
1374         if (host->iclk && !IS_ERR(host->iclk))
1375                 clk_put(host->iclk);
1376         if (host->fclk && !IS_ERR(host->fclk))
1377                 clk_put(host->fclk);
1378
1379         release_mem_region(pdev->resource[0].start,
1380                            pdev->resource[0].end - pdev->resource[0].start + 1);
1381
1382         kfree(host);
1383
1384         return 0;
1385 }
1386
1387 #ifdef CONFIG_PM
1388 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1389 {
1390         int i, ret = 0;
1391         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1392
1393         if (host == NULL || host->suspended)
1394                 return 0;
1395
1396         for (i = 0; i < host->nr_slots; i++) {
1397                 struct mmc_omap_slot *slot;
1398
1399                 slot = host->slots[i];
1400                 ret = mmc_suspend_host(slot->mmc, mesg);
1401                 if (ret < 0) {
1402                         while (--i >= 0) {
1403                                 slot = host->slots[i];
1404                                 mmc_resume_host(slot->mmc);
1405                         }
1406                         return ret;
1407                 }
1408         }
1409         host->suspended = 1;
1410         return 0;
1411 }
1412
1413 static int mmc_omap_resume(struct platform_device *pdev)
1414 {
1415         int i, ret = 0;
1416         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1417
1418         if (host == NULL || !host->suspended)
1419                 return 0;
1420
1421         for (i = 0; i < host->nr_slots; i++) {
1422                 struct mmc_omap_slot *slot;
1423                 slot = host->slots[i];
1424                 ret = mmc_resume_host(slot->mmc);
1425                 if (ret < 0)
1426                         return ret;
1427
1428                 host->suspended = 0;
1429         }
1430         return 0;
1431 }
1432 #else
1433 #define mmc_omap_suspend        NULL
1434 #define mmc_omap_resume         NULL
1435 #endif
1436
1437 static struct platform_driver mmc_omap_driver = {
1438         .probe          = mmc_omap_probe,
1439         .remove         = mmc_omap_remove,
1440         .suspend        = mmc_omap_suspend,
1441         .resume         = mmc_omap_resume,
1442         .driver         = {
1443                 .name   = DRIVER_NAME,
1444         },
1445 };
1446
1447 static int __init mmc_omap_init(void)
1448 {
1449         return platform_driver_register(&mmc_omap_driver);
1450 }
1451
1452 static void __exit mmc_omap_exit(void)
1453 {
1454         platform_driver_unregister(&mmc_omap_driver);
1455 }
1456
1457 module_init(mmc_omap_init);
1458 module_exit(mmc_omap_exit);
1459
1460 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1461 MODULE_LICENSE("GPL");
1462 MODULE_ALIAS(DRIVER_NAME);
1463 MODULE_AUTHOR("Juha Yrjölä");