drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/clk.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/i2c/tps65010.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/mmc.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/dma.h>
  38 #include <asm/arch/mux.h>
  39 #include <asm/arch/fpga.h>
  40
  41 #define OMAP_MMC_REG_CMD        0x00
  42 #define OMAP_MMC_REG_ARGL       0x04
  43 #define OMAP_MMC_REG_ARGH       0x08
  44 #define OMAP_MMC_REG_CON        0x0c
  45 #define OMAP_MMC_REG_STAT       0x10
  46 #define OMAP_MMC_REG_IE         0x14
  47 #define OMAP_MMC_REG_CTO        0x18
  48 #define OMAP_MMC_REG_DTO        0x1c
  49 #define OMAP_MMC_REG_DATA       0x20
  50 #define OMAP_MMC_REG_BLEN       0x24
  51 #define OMAP_MMC_REG_NBLK       0x28
  52 #define OMAP_MMC_REG_BUF        0x2c
  53 #define OMAP_MMC_REG_SDIO       0x34
  54 #define OMAP_MMC_REG_REV        0x3c
  55 #define OMAP_MMC_REG_RSP0       0x40
  56 #define OMAP_MMC_REG_RSP1       0x44
  57 #define OMAP_MMC_REG_RSP2       0x48
  58 #define OMAP_MMC_REG_RSP3       0x4c
  59 #define OMAP_MMC_REG_RSP4       0x50
  60 #define OMAP_MMC_REG_RSP5       0x54
  61 #define OMAP_MMC_REG_RSP6       0x58
  62 #define OMAP_MMC_REG_RSP7       0x5c
  63 #define OMAP_MMC_REG_IOSR       0x60
  64 #define OMAP_MMC_REG_SYSC       0x64
  65 #define OMAP_MMC_REG_SYSS       0x68
  66
  67 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  68 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  69 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  70 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  71 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  72 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  73 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  74 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  75 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  76 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  77 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  78 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  79 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  80
  81 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  82 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  83
  84 /*
  85  * Command types
  86  */
  87 #define OMAP_MMC_CMDTYPE_BC     0
  88 #define OMAP_MMC_CMDTYPE_BCR    1
  89 #define OMAP_MMC_CMDTYPE_AC     2
  90 #define OMAP_MMC_CMDTYPE_ADTC   3
  91
  92
  93 #define DRIVER_NAME "mmci-omap"
  94
  95 /* Specifies how often in millisecs to poll for card status changes
  96  * when the cover switch is open */
  97 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  98
  99 struct mmc_omap_host;
 100
 101 struct mmc_omap_slot {
 102         int                     id;
 103         unsigned int            vdd;
 104         u16                     saved_con;
 105         u16                     bus_mode;
 106         unsigned int            fclk_freq;
 107         unsigned                powered:1;
 108
 109         struct mmc_request      *mrq;
 110         struct mmc_omap_host    *host;
 111         struct mmc_host         *mmc;
 112         struct omap_mmc_slot_data *pdata;
 113 };
 114
 115 struct mmc_omap_host {
 116         int                     initialized;
 117         int                     suspended;
 118         struct mmc_request *    mrq;
 119         struct mmc_command *    cmd;
 120         struct mmc_data *       data;
 121         struct mmc_host *       mmc;
 122         struct device *         dev;
 123         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 124         struct clk *            iclk;
 125         struct clk *            fclk;
 126         struct resource         *mem_res;
 127         void __iomem            *virt_base;
 128         unsigned int            phys_base;
 129         int                     irq;
 130         unsigned char           bus_mode;
 131         unsigned char           hw_bus_mode;
 132
 133         unsigned int            sg_len;
 134         int                     sg_idx;
 135         u16 *                   buffer;
 136         u32                     buffer_bytes_left;
 137         u32                     total_bytes_left;
 138
 139         unsigned                use_dma:1;
 140         unsigned                brs_received:1, dma_done:1;
 141         unsigned                dma_is_read:1;
 142         unsigned                dma_in_use:1;
 143         int                     dma_ch;
 144         spinlock_t              dma_lock;
 145         struct timer_list       dma_timer;
 146         unsigned                dma_len;
 147
 148         short                   power_pin;
 149
 150         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 151         struct mmc_omap_slot    *current_slot;
 152         spinlock_t              slot_lock;
 153         wait_queue_head_t       slot_wq;
 154         int                     nr_slots;
 155
 156         struct omap_mmc_platform_data *pdata;
 157 };
 158
 159 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 160 {
 161         struct mmc_omap_host *host = slot->host;
 162         unsigned long flags;
 163
 164         if (claimed)
 165                 goto no_claim;
 166         spin_lock_irqsave(&host->slot_lock, flags);
 167         while (host->mmc != NULL) {
 168                 spin_unlock_irqrestore(&host->slot_lock, flags);
 169                 wait_event(host->slot_wq, host->mmc == NULL);
 170                 spin_lock_irqsave(&host->slot_lock, flags);
 171         }
 172         host->mmc = slot->mmc;
 173         spin_unlock_irqrestore(&host->slot_lock, flags);
 174 no_claim:
 175         clk_enable(host->fclk);
 176         if (host->current_slot != slot) {
 177                 if (host->pdata->switch_slot != NULL)
 178                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 179                 host->current_slot = slot;
 180         }
 181
 182         /* Doing the dummy read here seems to work around some bug
 183          * at least in OMAP24xx silicon where the command would not
 184          * start after writing the CMD register. Sigh. */
 185         OMAP_MMC_READ(host, CON);
 186
 187         OMAP_MMC_WRITE(host, CON, slot->saved_con);
 188 }
 189
 190 static void mmc_omap_start_request(struct mmc_omap_host *host,
 191                                    struct mmc_request *req);
 192
 193 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
 194 {
 195         struct mmc_omap_host *host = slot->host;
 196         unsigned long flags;
 197         int i;
 198
 199         BUG_ON(slot == NULL || host->mmc == NULL);
 200         clk_disable(host->fclk);
 201
 202         spin_lock_irqsave(&host->slot_lock, flags);
 203         /* Check for any pending requests */
 204         for (i = 0; i < host->nr_slots; i++) {
 205                 struct mmc_omap_slot *new_slot;
 206                 struct mmc_request *rq;
 207
 208                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 209                         continue;
 210
 211                 new_slot = host->slots[i];
 212                 /* The current slot should not have a request in queue */
 213                 BUG_ON(new_slot == host->current_slot);
 214
 215                 host->mmc = new_slot->mmc;
 216                 spin_unlock_irqrestore(&host->slot_lock, flags);
 217                 mmc_omap_select_slot(new_slot, 1);
 218                 rq = new_slot->mrq;
 219                 new_slot->mrq = NULL;
 220                 mmc_omap_start_request(host, rq);
 221                 return;
 222         }
 223
 224         host->mmc = NULL;
 225         wake_up(&host->slot_wq);
 226         spin_unlock_irqrestore(&host->slot_lock, flags);
 227 }
 228
 229 static ssize_t
 230 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 231                         char *buf)
 232 {
 233         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 234         struct mmc_omap_slot *slot = mmc_priv(mmc);
 235
 236         return sprintf(buf, "%s\n", slot->pdata->name);
 237 }
 238
 239 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 240
 241 static void
 242 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 243 {
 244         u32 cmdreg;
 245         u32 resptype;
 246         u32 cmdtype;
 247
 248         host->cmd = cmd;
 249
 250         resptype = 0;
 251         cmdtype = 0;
 252
 253         /* Our hardware needs to know exact type */
 254         switch (mmc_resp_type(cmd)) {
 255         case MMC_RSP_NONE:
 256                 break;
 257         case MMC_RSP_R1:
 258         case MMC_RSP_R1B:
 259                 /* resp 1, 1b, 6, 7 */
 260                 resptype = 1;
 261                 break;
 262         case MMC_RSP_R2:
 263                 resptype = 2;
 264                 break;
 265         case MMC_RSP_R3:
 266                 resptype = 3;
 267                 break;
 268         default:
 269                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 270                 break;
 271         }
 272
 273         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 274                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 275         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 276                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 277         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 278                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 279         } else {
 280                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 281         }
 282
 283         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 284
 285         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 286                 cmdreg |= 1 << 6;
 287
 288         if (cmd->flags & MMC_RSP_BUSY)
 289                 cmdreg |= 1 << 11;
 290
 291         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 292                 cmdreg |= 1 << 15;
 293
 294         OMAP_MMC_WRITE(host, CTO, 200);
 295         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 296         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 297         OMAP_MMC_WRITE(host, IE,
 298                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 299                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 300                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 301                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 302                        OMAP_MMC_STAT_END_OF_DATA);
 303         OMAP_MMC_WRITE(host, CMD, cmdreg);
 304 }
 305
 306 static void
 307 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 308 {
 309         if (host->dma_in_use) {
 310                 enum dma_data_direction dma_data_dir;
 311
 312                 BUG_ON(host->dma_ch < 0);
 313                 if (data->error)
 314                         omap_stop_dma(host->dma_ch);
 315                 /* Release DMA channel lazily */
 316                 mod_timer(&host->dma_timer, jiffies + HZ);
 317                 if (data->flags & MMC_DATA_WRITE)
 318                         dma_data_dir = DMA_TO_DEVICE;
 319                 else
 320                         dma_data_dir = DMA_FROM_DEVICE;
 321                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 322                              dma_data_dir);
 323         }
 324         host->data = NULL;
 325         host->sg_len = 0;
 326         clk_disable(host->fclk);
 327
 328         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 329          * dozens of requests until the card finishes writing data.
 330          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 331          */
 332
 333         if (!data->stop) {
 334                 host->mrq = NULL;
 335                 mmc_request_done(host->mmc, data->mrq);
 336                 return;
 337         }
 338
 339         mmc_omap_start_command(host, data->stop);
 340 }
 341
 342 static void
 343 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 344 {
 345         unsigned long flags;
 346         int done;
 347
 348         if (!host->dma_in_use) {
 349                 mmc_omap_xfer_done(host, data);
 350                 return;
 351         }
 352         done = 0;
 353         spin_lock_irqsave(&host->dma_lock, flags);
 354         if (host->dma_done)
 355                 done = 1;
 356         else
 357                 host->brs_received = 1;
 358         spin_unlock_irqrestore(&host->dma_lock, flags);
 359         if (done)
 360                 mmc_omap_xfer_done(host, data);
 361 }
 362
 363 static void
 364 mmc_omap_dma_timer(unsigned long data)
 365 {
 366         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 367
 368         BUG_ON(host->dma_ch < 0);
 369         omap_free_dma(host->dma_ch);
 370         host->dma_ch = -1;
 371 }
 372
 373 static void
 374 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 375 {
 376         unsigned long flags;
 377         int done;
 378
 379         done = 0;
 380         spin_lock_irqsave(&host->dma_lock, flags);
 381         if (host->brs_received)
 382                 done = 1;
 383         else
 384                 host->dma_done = 1;
 385         spin_unlock_irqrestore(&host->dma_lock, flags);
 386         if (done)
 387                 mmc_omap_xfer_done(host, data);
 388 }
 389
 390 static void
 391 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 392 {
 393         host->cmd = NULL;
 394
 395         if (cmd->flags & MMC_RSP_PRESENT) {
 396                 if (cmd->flags & MMC_RSP_136) {
 397                         /* response type 2 */
 398                         cmd->resp[3] =
 399                                 OMAP_MMC_READ(host, RSP0) |
 400                                 (OMAP_MMC_READ(host, RSP1) << 16);
 401                         cmd->resp[2] =
 402                                 OMAP_MMC_READ(host, RSP2) |
 403                                 (OMAP_MMC_READ(host, RSP3) << 16);
 404                         cmd->resp[1] =
 405                                 OMAP_MMC_READ(host, RSP4) |
 406                                 (OMAP_MMC_READ(host, RSP5) << 16);
 407                         cmd->resp[0] =
 408                                 OMAP_MMC_READ(host, RSP6) |
 409                                 (OMAP_MMC_READ(host, RSP7) << 16);
 410                 } else {
 411                         /* response types 1, 1b, 3, 4, 5, 6 */
 412                         cmd->resp[0] =
 413                                 OMAP_MMC_READ(host, RSP6) |
 414                                 (OMAP_MMC_READ(host, RSP7) << 16);
 415                 }
 416         }
 417
 418         if (host->data == NULL || cmd->error) {
 419                 host->mrq = NULL;
 420                 clk_disable(host->fclk);
 421                 mmc_request_done(host->mmc, cmd->mrq);
 422         }
 423 }
 424
 425 /* PIO only */
 426 static void
 427 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 428 {
 429         struct scatterlist *sg;
 430
 431         sg = host->data->sg + host->sg_idx;
 432         host->buffer_bytes_left = sg->length;
 433         host->buffer = sg_virt(sg);
 434         if (host->buffer_bytes_left > host->total_bytes_left)
 435                 host->buffer_bytes_left = host->total_bytes_left;
 436 }
 437
 438 /* PIO only */
 439 static void
 440 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 441 {
 442         int n;
 443
 444         if (host->buffer_bytes_left == 0) {
 445                 host->sg_idx++;
 446                 BUG_ON(host->sg_idx == host->sg_len);
 447                 mmc_omap_sg_to_buf(host);
 448         }
 449         n = 64;
 450         if (n > host->buffer_bytes_left)
 451                 n = host->buffer_bytes_left;
 452         host->buffer_bytes_left -= n;
 453         host->total_bytes_left -= n;
 454         host->data->bytes_xfered += n;
 455
 456         if (write) {
 457                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 458         } else {
 459                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 460         }
 461 }
 462
 463 static inline void mmc_omap_report_irq(u16 status)
 464 {
 465         static const char *mmc_omap_status_bits[] = {
 466                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 467                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 468         };
 469         int i, c = 0;
 470
 471         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 472                 if (status & (1 << i)) {
 473                         if (c)
 474                                 printk(" ");
 475                         printk("%s", mmc_omap_status_bits[i]);
 476                         c++;
 477                 }
 478 }
 479
 480 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 481 {
 482         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 483         u16 status;
 484         int end_command;
 485         int end_transfer;
 486         int transfer_error;
 487
 488         if (host->cmd == NULL && host->data == NULL) {
 489                 status = OMAP_MMC_READ(host, STAT);
 490                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 491                 if (status != 0) {
 492                         OMAP_MMC_WRITE(host, STAT, status);
 493                         OMAP_MMC_WRITE(host, IE, 0);
 494                 }
 495                 return IRQ_HANDLED;
 496         }
 497
 498         end_command = 0;
 499         end_transfer = 0;
 500         transfer_error = 0;
 501
 502         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 503                 OMAP_MMC_WRITE(host, STAT, status);
 504 #ifdef CONFIG_MMC_DEBUG
 505                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 506                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 507                 mmc_omap_report_irq(status);
 508                 printk("\n");
 509 #endif
 510                 if (host->total_bytes_left) {
 511                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 512                             (status & OMAP_MMC_STAT_END_OF_DATA))
 513                                 mmc_omap_xfer_data(host, 0);
 514                         if (status & OMAP_MMC_STAT_A_EMPTY)
 515                                 mmc_omap_xfer_data(host, 1);
 516                 }
 517
 518                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 519                         end_transfer = 1;
 520                 }
 521
 522                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 523                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 524                         if (host->data) {
 525                                 host->data->error = -ETIMEDOUT;
 526                                 transfer_error = 1;
 527                         }
 528                 }
 529
 530                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 531                         if (host->data) {
 532                                 host->data->error = -EILSEQ;
 533                                 dev_dbg(mmc_dev(host->mmc),
 534                                          "data CRC error, bytes left %d\n",
 535                                         host->total_bytes_left);
 536                                 transfer_error = 1;
 537                         } else {
 538                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 539                         }
 540                 }
 541
 542                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 543                         /* Timeouts are routine with some commands */
 544                         if (host->cmd) {
 545                                 struct mmc_omap_slot *slot =
 546                                         host->current_slot;
 547                                 dev_err(mmc_dev(host->mmc),
 548                                         "command timeout, CMD %d\n",
 549                                         host->cmd->opcode);
 550                                 host->cmd->error = -ETIMEDOUT;
 551                                 end_command = 1;
 552                         }
 553                 }
 554
 555                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 556                         if (host->cmd) {
 557                                 dev_err(mmc_dev(host->mmc),
 558                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 559                                         host->cmd->opcode, host->cmd->arg);
 560                                 host->cmd->error = -EILSEQ;
 561                                 end_command = 1;
 562                         } else
 563                                 dev_err(mmc_dev(host->mmc),
 564                                         "command CRC error without cmd?\n");
 565                 }
 566
 567                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 568                         dev_dbg(mmc_dev(host->mmc),
 569                                 "ignoring card status error (CMD%d)\n",
 570                                 host->cmd->opcode);
 571                         end_command = 1;
 572                 }
 573
 574                 /*
 575                  * NOTE: On 1610 the END_OF_CMD may come too early when
 576                  * starting a write
 577                  */
 578                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 579                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 580                         end_command = 1;
 581                 }
 582         }
 583
 584         if (end_command) {
 585                 mmc_omap_cmd_done(host, host->cmd);
 586         }
 587         if (transfer_error)
 588                 mmc_omap_xfer_done(host, host->data);
 589         else if (end_transfer)
 590                 mmc_omap_end_of_data(host, host->data);
 591
 592         return IRQ_HANDLED;
 593 }
 594
 595 /* Prepare to transfer the next segment of a scatterlist */
 596 static void
 597 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 598 {
 599         int dma_ch = host->dma_ch;
 600         unsigned long data_addr;
 601         u16 buf, frame;
 602         u32 count;
 603         struct scatterlist *sg = &data->sg[host->sg_idx];
 604         int src_port = 0;
 605         int dst_port = 0;
 606         int sync_dev = 0;
 607
 608         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 609         frame = data->blksz;
 610         count = sg_dma_len(sg);
 611
 612         if ((data->blocks == 1) && (count > data->blksz))
 613                 count = frame;
 614
 615         host->dma_len = count;
 616
 617         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 618          * Use 16 or 32 word frames when the blocksize is at least that large.
 619          * Blocksize is usually 512 bytes; but not for some SD reads.
 620          */
 621         if (cpu_is_omap15xx() && frame > 32)
 622                 frame = 32;
 623         else if (frame > 64)
 624                 frame = 64;
 625         count /= frame;
 626         frame >>= 1;
 627
 628         if (!(data->flags & MMC_DATA_WRITE)) {
 629                 buf = 0x800f | ((frame - 1) << 8);
 630
 631                 if (cpu_class_is_omap1()) {
 632                         src_port = OMAP_DMA_PORT_TIPB;
 633                         dst_port = OMAP_DMA_PORT_EMIFF;
 634                 }
 635                 if (cpu_is_omap24xx())
 636                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 637
 638                 omap_set_dma_src_params(dma_ch, src_port,
 639                                         OMAP_DMA_AMODE_CONSTANT,
 640                                         data_addr, 0, 0);
 641                 omap_set_dma_dest_params(dma_ch, dst_port,
 642                                          OMAP_DMA_AMODE_POST_INC,
 643                                          sg_dma_address(sg), 0, 0);
 644                 omap_set_dma_dest_data_pack(dma_ch, 1);
 645                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 646         } else {
 647                 buf = 0x0f80 | ((frame - 1) << 0);
 648
 649                 if (cpu_class_is_omap1()) {
 650                         src_port = OMAP_DMA_PORT_EMIFF;
 651                         dst_port = OMAP_DMA_PORT_TIPB;
 652                 }
 653                 if (cpu_is_omap24xx())
 654                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 655
 656                 omap_set_dma_dest_params(dma_ch, dst_port,
 657                                          OMAP_DMA_AMODE_CONSTANT,
 658                                          data_addr, 0, 0);
 659                 omap_set_dma_src_params(dma_ch, src_port,
 660                                         OMAP_DMA_AMODE_POST_INC,
 661                                         sg_dma_address(sg), 0, 0);
 662                 omap_set_dma_src_data_pack(dma_ch, 1);
 663                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 664         }
 665
 666         /* Max limit for DMA frame count is 0xffff */
 667         BUG_ON(count > 0xffff);
 668
 669         OMAP_MMC_WRITE(host, BUF, buf);
 670         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 671                                      frame, count, OMAP_DMA_SYNC_FRAME,
 672                                      sync_dev, 0);
 673 }
 674
 675 /* A scatterlist segment completed */
 676 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 677 {
 678         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 679         struct mmc_data *mmcdat = host->data;
 680
 681         if (unlikely(host->dma_ch < 0)) {
 682                 dev_err(mmc_dev(host->mmc),
 683                         "DMA callback while DMA not enabled\n");
 684                 return;
 685         }
 686         /* FIXME: We really should do something to _handle_ the errors */
 687         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 688                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 689                 return;
 690         }
 691         if (ch_status & OMAP_DMA_DROP_IRQ) {
 692                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 693                 return;
 694         }
 695         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 696                 return;
 697         }
 698         mmcdat->bytes_xfered += host->dma_len;
 699         host->sg_idx++;
 700         if (host->sg_idx < host->sg_len) {
 701                 mmc_omap_prepare_dma(host, host->data);
 702                 omap_start_dma(host->dma_ch);
 703         } else
 704                 mmc_omap_dma_done(host, host->data);
 705 }
 706
 707 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 708 {
 709         const char *dev_name;
 710         int sync_dev, dma_ch, is_read, r;
 711
 712         is_read = !(data->flags & MMC_DATA_WRITE);
 713         del_timer_sync(&host->dma_timer);
 714         if (host->dma_ch >= 0) {
 715                 if (is_read == host->dma_is_read)
 716                         return 0;
 717                 omap_free_dma(host->dma_ch);
 718                 host->dma_ch = -1;
 719         }
 720
 721         if (is_read) {
 722                 if (host->id == 1) {
 723                         sync_dev = OMAP_DMA_MMC_RX;
 724                         dev_name = "MMC1 read";
 725                 } else {
 726                         sync_dev = OMAP_DMA_MMC2_RX;
 727                         dev_name = "MMC2 read";
 728                 }
 729         } else {
 730                 if (host->id == 1) {
 731                         sync_dev = OMAP_DMA_MMC_TX;
 732                         dev_name = "MMC1 write";
 733                 } else {
 734                         sync_dev = OMAP_DMA_MMC2_TX;
 735                         dev_name = "MMC2 write";
 736                 }
 737         }
 738         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 739                              host, &dma_ch);
 740         if (r != 0) {
 741                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 742                 return r;
 743         }
 744         host->dma_ch = dma_ch;
 745         host->dma_is_read = is_read;
 746
 747         return 0;
 748 }
 749
 750 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 751 {
 752         u16 reg;
 753
 754         reg = OMAP_MMC_READ(host, SDIO);
 755         reg &= ~(1 << 5);
 756         OMAP_MMC_WRITE(host, SDIO, reg);
 757         /* Set maximum timeout */
 758         OMAP_MMC_WRITE(host, CTO, 0xff);
 759 }
 760
 761 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 762 {
 763         int timeout;
 764         u16 reg;
 765
 766         /* Convert ns to clock cycles by assuming 20MHz frequency
 767          * 1 cycle at 20MHz = 500 ns
 768          */
 769         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 770
 771         /* Check if we need to use timeout multiplier register */
 772         reg = OMAP_MMC_READ(host, SDIO);
 773         if (timeout > 0xffff) {
 774                 reg |= (1 << 5);
 775                 timeout /= 1024;
 776         } else
 777                 reg &= ~(1 << 5);
 778         OMAP_MMC_WRITE(host, SDIO, reg);
 779         OMAP_MMC_WRITE(host, DTO, timeout);
 780 }
 781
 782 static void
 783 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 784 {
 785         struct mmc_data *data = req->data;
 786         int i, use_dma, block_size;
 787         unsigned sg_len;
 788
 789         host->data = data;
 790         if (data == NULL) {
 791                 OMAP_MMC_WRITE(host, BLEN, 0);
 792                 OMAP_MMC_WRITE(host, NBLK, 0);
 793                 OMAP_MMC_WRITE(host, BUF, 0);
 794                 host->dma_in_use = 0;
 795                 set_cmd_timeout(host, req);
 796                 return;
 797         }
 798
 799         block_size = data->blksz;
 800
 801         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 802         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 803         set_data_timeout(host, req);
 804
 805         /* cope with calling layer confusion; it issues "single
 806          * block" writes using multi-block scatterlists.
 807          */
 808         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 809
 810         /* Only do DMA for entire blocks */
 811         use_dma = host->use_dma;
 812         if (use_dma) {
 813                 for (i = 0; i < sg_len; i++) {
 814                         if ((data->sg[i].length % block_size) != 0) {
 815                                 use_dma = 0;
 816                                 break;
 817                         }
 818                 }
 819         }
 820
 821         host->sg_idx = 0;
 822         if (use_dma) {
 823                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 824                         enum dma_data_direction dma_data_dir;
 825
 826                         if (data->flags & MMC_DATA_WRITE)
 827                                 dma_data_dir = DMA_TO_DEVICE;
 828                         else
 829                                 dma_data_dir = DMA_FROM_DEVICE;
 830
 831                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 832                                                 sg_len, dma_data_dir);
 833                         host->total_bytes_left = 0;
 834                         mmc_omap_prepare_dma(host, req->data);
 835                         host->brs_received = 0;
 836                         host->dma_done = 0;
 837                         host->dma_in_use = 1;
 838                 } else
 839                         use_dma = 0;
 840         }
 841
 842         /* Revert to PIO? */
 843         if (!use_dma) {
 844                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 845                 host->total_bytes_left = data->blocks * block_size;
 846                 host->sg_len = sg_len;
 847                 mmc_omap_sg_to_buf(host);
 848                 host->dma_in_use = 0;
 849         }
 850 }
 851
 852 static void mmc_omap_start_request(struct mmc_omap_host *host,
 853                                    struct mmc_request *req)
 854 {
 855         BUG_ON(host->mrq != NULL);
 856
 857         host->mrq = req;
 858
 859         /* only touch fifo AFTER the controller readies it */
 860         mmc_omap_prepare_data(host, req);
 861         mmc_omap_start_command(host, req->cmd);
 862         if (host->dma_in_use)
 863                 omap_start_dma(host->dma_ch);
 864         BUG_ON(irqs_disabled());
 865 }
 866
 867 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 868 {
 869         struct mmc_omap_slot *slot = mmc_priv(mmc);
 870         struct mmc_omap_host *host = slot->host;
 871         unsigned long flags;
 872
 873         spin_lock_irqsave(&host->slot_lock, flags);
 874         if (host->mmc != NULL) {
 875                 BUG_ON(slot->mrq != NULL);
 876                 slot->mrq = req;
 877                 spin_unlock_irqrestore(&host->slot_lock, flags);
 878                 return;
 879         } else
 880                 host->mmc = mmc;
 881         spin_unlock_irqrestore(&host->slot_lock, flags);
 882         mmc_omap_select_slot(slot, 1);
 883         mmc_omap_start_request(host, req);
 884 }
 885
 886 static void innovator_fpga_socket_power(int on)
 887 {
 888 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 889         if (on) {
 890                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 891                      OMAP1510_FPGA_POWER);
 892         } else {
 893                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 894                      OMAP1510_FPGA_POWER);
 895         }
 896 #endif
 897 }
 898
 899 /*
 900  * Turn the socket power on/off. Innovator uses FPGA, most boards
 901  * probably use GPIO.
 902  */
 903 static void mmc_omap_power(struct mmc_omap_host *host, int on)
 904 {
 905         if (on) {
 906                 if (machine_is_omap_innovator())
 907                         innovator_fpga_socket_power(1);
 908                 else if (machine_is_omap_h2())
 909                         tps65010_set_gpio_out_value(GPIO3, HIGH);
 910                 else if (machine_is_omap_h3())
 911                         /* GPIO 4 of TPS65010 sends SD_EN signal */
 912                         tps65010_set_gpio_out_value(GPIO4, HIGH);
 913                 else if (cpu_is_omap24xx()) {
 914                         u16 reg = OMAP_MMC_READ(host, CON);
 915                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
 916                 } else
 917                         if (host->power_pin >= 0)
 918                                 omap_set_gpio_dataout(host->power_pin, 1);
 919         } else {
 920                 if (machine_is_omap_innovator())
 921                         innovator_fpga_socket_power(0);
 922                 else if (machine_is_omap_h2())
 923                         tps65010_set_gpio_out_value(GPIO3, LOW);
 924                 else if (machine_is_omap_h3())
 925                         tps65010_set_gpio_out_value(GPIO4, LOW);
 926                 else if (cpu_is_omap24xx()) {
 927                         u16 reg = OMAP_MMC_READ(host, CON);
 928                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
 929                 } else
 930                         if (host->power_pin >= 0)
 931                                 omap_set_gpio_dataout(host->power_pin, 0);
 932         }
 933 }
 934
 935 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
 936 {
 937         struct mmc_omap_slot *slot = mmc_priv(mmc);
 938         struct mmc_omap_host *host = slot->host;
 939         int func_clk_rate = clk_get_rate(host->fclk);
 940         int dsor;
 941
 942         if (ios->clock == 0)
 943                 return 0;
 944
 945         dsor = func_clk_rate / ios->clock;
 946         if (dsor < 1)
 947                 dsor = 1;
 948
 949         if (func_clk_rate / dsor > ios->clock)
 950                 dsor++;
 951
 952         if (dsor > 250)
 953                 dsor = 250;
 954
 955         slot->fclk_freq = func_clk_rate / dsor;
 956
 957         if (ios->bus_width == MMC_BUS_WIDTH_4)
 958                 dsor |= 1 << 15;
 959
 960         return dsor;
 961 }
 962
 963 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 964 {
 965         struct mmc_omap_slot *slot = mmc_priv(mmc);
 966         struct mmc_omap_host *host = slot->host;
 967         int i, dsor;
 968
 969         dsor = mmc_omap_calc_divisor(mmc, ios);
 970         host->bus_mode = ios->bus_mode;
 971         host->hw_bus_mode = host->bus_mode;
 972
 973         switch (ios->power_mode) {
 974         case MMC_POWER_OFF:
 975                 mmc_omap_power(host, 0);
 976                 break;
 977         case MMC_POWER_UP:
 978                 /* Cannot touch dsor yet, just power up MMC */
 979                 mmc_omap_power(host, 1);
 980                 return;
 981         case MMC_POWER_ON:
 982                 dsor |= 1 << 11;
 983                 break;
 984         }
 985
 986         clk_enable(host->fclk);
 987
 988         /* On insanely high arm_per frequencies something sometimes
 989          * goes somehow out of sync, and the POW bit is not being set,
 990          * which results in the while loop below getting stuck.
 991          * Writing to the CON register twice seems to do the trick. */
 992         for (i = 0; i < 2; i++)
 993                 OMAP_MMC_WRITE(host, CON, dsor);
 994         if (ios->power_mode == MMC_POWER_ON) {
 995                 /* Send clock cycles, poll completion */
 996                 OMAP_MMC_WRITE(host, IE, 0);
 997                 OMAP_MMC_WRITE(host, STAT, 0xffff);
 998                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
 999                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1000                 OMAP_MMC_WRITE(host, STAT, 1);
1001         }
1002         clk_disable(host->fclk);
1003 }
1004
1005 static const struct mmc_host_ops mmc_omap_ops = {
1006         .request        = mmc_omap_request,
1007         .set_ios        = mmc_omap_set_ios,
1008 };
1009
1010 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1011 {
1012         struct mmc_omap_slot *slot = NULL;
1013         struct mmc_host *mmc;
1014         int r;
1015
1016         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1017         if (mmc == NULL)
1018                 return -ENOMEM;
1019
1020         slot = mmc_priv(mmc);
1021         slot->host = host;
1022         slot->mmc = mmc;
1023         slot->id = id;
1024         slot->pdata = &host->pdata->slots[id];
1025
1026         host->slots[id] = slot;
1027
1028         mmc->caps = MMC_CAP_MULTIWRITE;
1029         if (host->pdata->conf.wire4)
1030                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1031
1032         mmc->ops = &mmc_omap_ops;
1033         mmc->f_min = 400000;
1034
1035         if (cpu_class_is_omap2())
1036                 mmc->f_max = 48000000;
1037         else
1038                 mmc->f_max = 24000000;
1039         if (host->pdata->max_freq)
1040                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1041         mmc->ocr_avail = slot->pdata->ocr_mask;
1042
1043         /* Use scatterlist DMA to reduce per-transfer costs.
1044          * NOTE max_seg_size assumption that small blocks aren't
1045          * normally used (except e.g. for reading SD registers).
1046          */
1047         mmc->max_phys_segs = 32;
1048         mmc->max_hw_segs = 32;
1049         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1050         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1051         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1052         mmc->max_seg_size = mmc->max_req_size;
1053
1054         r = mmc_add_host(mmc);
1055         if (r < 0)
1056                 goto err_remove_host;
1057
1058         if (slot->pdata->name != NULL) {
1059                 r = device_create_file(&mmc->class_dev,
1060                                         &dev_attr_slot_name);
1061                 if (r < 0)
1062                         goto err_remove_host;
1063         }
1064
1065         return 0;
1066
1067 err_remove_host:
1068         mmc_remove_host(mmc);
1069         mmc_free_host(mmc);
1070         return r;
1071 }
1072
1073 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1074 {
1075         struct mmc_host *mmc = slot->mmc;
1076
1077         if (slot->pdata->name != NULL)
1078                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1079
1080         mmc_remove_host(mmc);
1081         mmc_free_host(mmc);
1082 }
1083
1084 static int __init mmc_omap_probe(struct platform_device *pdev)
1085 {
1086         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1087         struct mmc_omap_host *host = NULL;
1088         struct resource *res;
1089         int i, ret = 0;
1090         int irq;
1091
1092         if (pdata == NULL) {
1093                 dev_err(&pdev->dev, "platform data missing\n");
1094                 return -ENXIO;
1095         }
1096         if (pdata->nr_slots == 0) {
1097                 dev_err(&pdev->dev, "no slots\n");
1098                 return -ENXIO;
1099         }
1100
1101         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1102         irq = platform_get_irq(pdev, 0);
1103         if (res == NULL || irq < 0)
1104                 return -ENXIO;
1105
1106         res = request_mem_region(res->start, res->end - res->start + 1,
1107                                  pdev->name);
1108         if (res == NULL)
1109                 return -EBUSY;
1110
1111         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1112         if (host == NULL) {
1113                 ret = -ENOMEM;
1114                 goto err_free_mem_region;
1115         }
1116
1117         spin_lock_init(&host->dma_lock);
1118         init_timer(&host->dma_timer);
1119         spin_lock_init(&host->slot_lock);
1120         init_waitqueue_head(&host->slot_wq);
1121
1122         host->dma_timer.function = mmc_omap_dma_timer;
1123         host->dma_timer.data = (unsigned long) host;
1124
1125         host->pdata = pdata;
1126         host->dev = &pdev->dev;
1127         platform_set_drvdata(pdev, host);
1128
1129         host->id = pdev->id;
1130         host->mem_res = res;
1131         host->irq = irq;
1132
1133         host->use_dma = 1;
1134         host->dma_ch = -1;
1135
1136         host->irq = irq;
1137         host->phys_base = host->mem_res->start;
1138         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1139
1140         if (cpu_is_omap24xx()) {
1141                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1142                 if (IS_ERR(host->iclk))
1143                         goto err_free_mmc_host;
1144                 clk_enable(host->iclk);
1145         }
1146
1147         if (!cpu_is_omap24xx())
1148                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1149         else
1150                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1151
1152         if (IS_ERR(host->fclk)) {
1153                 ret = PTR_ERR(host->fclk);
1154                 goto err_free_iclk;
1155         }
1156
1157         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1158         if (ret)
1159                 goto err_free_fclk;
1160
1161         if (pdata->init != NULL) {
1162                 ret = pdata->init(&pdev->dev);
1163                 if (ret < 0)
1164                         goto err_free_irq;
1165         }
1166
1167         host->nr_slots = pdata->nr_slots;
1168         for (i = 0; i < pdata->nr_slots; i++) {
1169                 ret = mmc_omap_new_slot(host, i);
1170                 if (ret < 0) {
1171                         while (--i >= 0)
1172                                 mmc_omap_remove_slot(host->slots[i]);
1173
1174                         goto err_plat_cleanup;
1175                 }
1176         }
1177
1178         return 0;
1179
1180 err_plat_cleanup:
1181         if (pdata->cleanup)
1182                 pdata->cleanup(&pdev->dev);
1183 err_free_irq:
1184         free_irq(host->irq, host);
1185 err_free_fclk:
1186         clk_put(host->fclk);
1187 err_free_iclk:
1188         if (host->iclk != NULL) {
1189                 clk_disable(host->iclk);
1190                 clk_put(host->iclk);
1191         }
1192 err_free_mmc_host:
1193         kfree(host);
1194 err_free_mem_region:
1195         release_mem_region(res->start, res->end - res->start + 1);
1196         return ret;
1197 }
1198
1199 static int mmc_omap_remove(struct platform_device *pdev)
1200 {
1201         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1202         int i;
1203
1204         platform_set_drvdata(pdev, NULL);
1205
1206         BUG_ON(host == NULL);
1207
1208         for (i = 0; i < host->nr_slots; i++)
1209                 mmc_omap_remove_slot(host->slots[i]);
1210
1211         if (host->pdata->cleanup)
1212                 host->pdata->cleanup(&pdev->dev);
1213
1214         if (host->iclk && !IS_ERR(host->iclk))
1215                 clk_put(host->iclk);
1216         if (host->fclk && !IS_ERR(host->fclk))
1217                 clk_put(host->fclk);
1218
1219         release_mem_region(pdev->resource[0].start,
1220                            pdev->resource[0].end - pdev->resource[0].start + 1);
1221
1222         kfree(host);
1223
1224         return 0;
1225 }
1226
1227 #ifdef CONFIG_PM
1228 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1229 {
1230         int i, ret = 0;
1231         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1232
1233         if (host == NULL || host->suspended)
1234                 return 0;
1235
1236         for (i = 0; i < host->nr_slots; i++) {
1237                 struct mmc_omap_slot *slot;
1238
1239                 slot = host->slots[i];
1240                 ret = mmc_suspend_host(slot->mmc, mesg);
1241                 if (ret < 0) {
1242                         while (--i >= 0) {
1243                                 slot = host->slots[i];
1244                                 mmc_resume_host(slot->mmc);
1245                         }
1246                         return ret;
1247                 }
1248         }
1249         host->suspended = 1;
1250         return 0;
1251 }
1252
1253 static int mmc_omap_resume(struct platform_device *pdev)
1254 {
1255         int i, ret = 0;
1256         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1257
1258         if (host == NULL || !host->suspended)
1259                 return 0;
1260
1261         for (i = 0; i < host->nr_slots; i++) {
1262                 struct mmc_omap_slot *slot;
1263                 slot = host->slots[i];
1264                 ret = mmc_resume_host(slot->mmc);
1265                 if (ret < 0)
1266                         return ret;
1267
1268                 host->suspended = 0;
1269         }
1270         return 0;
1271 }
1272 #else
1273 #define mmc_omap_suspend        NULL
1274 #define mmc_omap_resume         NULL
1275 #endif
1276
1277 static struct platform_driver mmc_omap_driver = {
1278         .probe          = mmc_omap_probe,
1279         .remove         = mmc_omap_remove,
1280         .suspend        = mmc_omap_suspend,
1281         .resume         = mmc_omap_resume,
1282         .driver         = {
1283                 .name   = DRIVER_NAME,
1284                 .owner  = THIS_MODULE,
1285         },
1286 };
1287
1288 static int __init mmc_omap_init(void)
1289 {
1290         return platform_driver_register(&mmc_omap_driver);
1291 }
1292
1293 static void __exit mmc_omap_exit(void)
1294 {
1295         platform_driver_unregister(&mmc_omap_driver);
1296 }
1297
1298 module_init(mmc_omap_init);
1299 module_exit(mmc_omap_exit);
1300
1301 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1302 MODULE_LICENSE("GPL");
1303 MODULE_ALIAS("platform:" DRIVER_NAME);
1304 MODULE_AUTHOR("Juha Yrjölä");