drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/clk.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/i2c/tps65010.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/mmc.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/dma.h>
  38 #include <asm/arch/mux.h>
  39 #include <asm/arch/fpga.h>
  40
  41 #define OMAP_MMC_REG_CMD        0x00
  42 #define OMAP_MMC_REG_ARGL       0x04
  43 #define OMAP_MMC_REG_ARGH       0x08
  44 #define OMAP_MMC_REG_CON        0x0c
  45 #define OMAP_MMC_REG_STAT       0x10
  46 #define OMAP_MMC_REG_IE         0x14
  47 #define OMAP_MMC_REG_CTO        0x18
  48 #define OMAP_MMC_REG_DTO        0x1c
  49 #define OMAP_MMC_REG_DATA       0x20
  50 #define OMAP_MMC_REG_BLEN       0x24
  51 #define OMAP_MMC_REG_NBLK       0x28
  52 #define OMAP_MMC_REG_BUF        0x2c
  53 #define OMAP_MMC_REG_SDIO       0x34
  54 #define OMAP_MMC_REG_REV        0x3c
  55 #define OMAP_MMC_REG_RSP0       0x40
  56 #define OMAP_MMC_REG_RSP1       0x44
  57 #define OMAP_MMC_REG_RSP2       0x48
  58 #define OMAP_MMC_REG_RSP3       0x4c
  59 #define OMAP_MMC_REG_RSP4       0x50
  60 #define OMAP_MMC_REG_RSP5       0x54
  61 #define OMAP_MMC_REG_RSP6       0x58
  62 #define OMAP_MMC_REG_RSP7       0x5c
  63 #define OMAP_MMC_REG_IOSR       0x60
  64 #define OMAP_MMC_REG_SYSC       0x64
  65 #define OMAP_MMC_REG_SYSS       0x68
  66
  67 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  68 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  69 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  70 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  71 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  72 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  73 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  74 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  75 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  76 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  77 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  78 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  79 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  80
  81 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  82 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  83
  84 /*
  85  * Command types
  86  */
  87 #define OMAP_MMC_CMDTYPE_BC     0
  88 #define OMAP_MMC_CMDTYPE_BCR    1
  89 #define OMAP_MMC_CMDTYPE_AC     2
  90 #define OMAP_MMC_CMDTYPE_ADTC   3
  91
  92
  93 #define DRIVER_NAME "mmci-omap"
  94
  95 /* Specifies how often in millisecs to poll for card status changes
  96  * when the cover switch is open */
  97 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  98
  99 struct mmc_omap_host;
 100
 101 struct mmc_omap_slot {
 102         int                     id;
 103         unsigned int            vdd;
 104         u16                     saved_con;
 105         u16                     bus_mode;
 106         unsigned int            fclk_freq;
 107         unsigned                powered:1;
 108
 109         struct work_struct      switch_work;
 110         struct timer_list       switch_timer;
 111         unsigned                cover_open;
 112
 113         struct mmc_request      *mrq;
 114         struct mmc_omap_host    *host;
 115         struct mmc_host         *mmc;
 116         struct omap_mmc_slot_data *pdata;
 117 };
 118
 119 struct mmc_omap_host {
 120         int                     initialized;
 121         int                     suspended;
 122         struct mmc_request *    mrq;
 123         struct mmc_command *    cmd;
 124         struct mmc_data *       data;
 125         struct mmc_host *       mmc;
 126         struct device *         dev;
 127         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 128         struct clk *            iclk;
 129         struct clk *            fclk;
 130         struct resource         *mem_res;
 131         void __iomem            *virt_base;
 132         unsigned int            phys_base;
 133         int                     irq;
 134         unsigned char           bus_mode;
 135         unsigned char           hw_bus_mode;
 136
 137         unsigned int            sg_len;
 138         int                     sg_idx;
 139         u16 *                   buffer;
 140         u32                     buffer_bytes_left;
 141         u32                     total_bytes_left;
 142
 143         unsigned                use_dma:1;
 144         unsigned                brs_received:1, dma_done:1;
 145         unsigned                dma_is_read:1;
 146         unsigned                dma_in_use:1;
 147         int                     dma_ch;
 148         spinlock_t              dma_lock;
 149         struct timer_list       dma_timer;
 150         unsigned                dma_len;
 151
 152         short                   power_pin;
 153
 154         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 155         struct mmc_omap_slot    *current_slot;
 156         spinlock_t              slot_lock;
 157         wait_queue_head_t       slot_wq;
 158         int                     nr_slots;
 159
 160         struct omap_mmc_platform_data *pdata;
 161 };
 162
 163 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 164 {
 165         struct mmc_omap_host *host = slot->host;
 166         unsigned long flags;
 167
 168         if (claimed)
 169                 goto no_claim;
 170         spin_lock_irqsave(&host->slot_lock, flags);
 171         while (host->mmc != NULL) {
 172                 spin_unlock_irqrestore(&host->slot_lock, flags);
 173                 wait_event(host->slot_wq, host->mmc == NULL);
 174                 spin_lock_irqsave(&host->slot_lock, flags);
 175         }
 176         host->mmc = slot->mmc;
 177         spin_unlock_irqrestore(&host->slot_lock, flags);
 178 no_claim:
 179         clk_enable(host->fclk);
 180         if (host->current_slot != slot) {
 181                 if (host->pdata->switch_slot != NULL)
 182                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 183                 host->current_slot = slot;
 184         }
 185
 186         /* Doing the dummy read here seems to work around some bug
 187          * at least in OMAP24xx silicon where the command would not
 188          * start after writing the CMD register. Sigh. */
 189         OMAP_MMC_READ(host, CON);
 190
 191         OMAP_MMC_WRITE(host, CON, slot->saved_con);
 192 }
 193
 194 static void mmc_omap_start_request(struct mmc_omap_host *host,
 195                                    struct mmc_request *req);
 196
 197 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
 198 {
 199         struct mmc_omap_host *host = slot->host;
 200         unsigned long flags;
 201         int i;
 202
 203         BUG_ON(slot == NULL || host->mmc == NULL);
 204         clk_disable(host->fclk);
 205
 206         spin_lock_irqsave(&host->slot_lock, flags);
 207         /* Check for any pending requests */
 208         for (i = 0; i < host->nr_slots; i++) {
 209                 struct mmc_omap_slot *new_slot;
 210                 struct mmc_request *rq;
 211
 212                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 213                         continue;
 214
 215                 new_slot = host->slots[i];
 216                 /* The current slot should not have a request in queue */
 217                 BUG_ON(new_slot == host->current_slot);
 218
 219                 host->mmc = new_slot->mmc;
 220                 spin_unlock_irqrestore(&host->slot_lock, flags);
 221                 mmc_omap_select_slot(new_slot, 1);
 222                 rq = new_slot->mrq;
 223                 new_slot->mrq = NULL;
 224                 mmc_omap_start_request(host, rq);
 225                 return;
 226         }
 227
 228         host->mmc = NULL;
 229         wake_up(&host->slot_wq);
 230         spin_unlock_irqrestore(&host->slot_lock, flags);
 231 }
 232
 233 static inline
 234 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 235 {
 236         return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
 237 }
 238
 239 static ssize_t
 240 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 241                            char *buf)
 242 {
 243         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 244         struct mmc_omap_slot *slot = mmc_priv(mmc);
 245
 246         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 247                        "closed");
 248 }
 249
 250 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 251
 252 static ssize_t
 253 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 254                         char *buf)
 255 {
 256         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 257         struct mmc_omap_slot *slot = mmc_priv(mmc);
 258
 259         return sprintf(buf, "%s\n", slot->pdata->name);
 260 }
 261
 262 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 263
 264 static void
 265 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 266 {
 267         u32 cmdreg;
 268         u32 resptype;
 269         u32 cmdtype;
 270
 271         host->cmd = cmd;
 272
 273         resptype = 0;
 274         cmdtype = 0;
 275
 276         /* Our hardware needs to know exact type */
 277         switch (mmc_resp_type(cmd)) {
 278         case MMC_RSP_NONE:
 279                 break;
 280         case MMC_RSP_R1:
 281         case MMC_RSP_R1B:
 282                 /* resp 1, 1b, 6, 7 */
 283                 resptype = 1;
 284                 break;
 285         case MMC_RSP_R2:
 286                 resptype = 2;
 287                 break;
 288         case MMC_RSP_R3:
 289                 resptype = 3;
 290                 break;
 291         default:
 292                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 293                 break;
 294         }
 295
 296         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 297                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 298         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 299                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 300         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 301                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 302         } else {
 303                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 304         }
 305
 306         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 307
 308         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 309                 cmdreg |= 1 << 6;
 310
 311         if (cmd->flags & MMC_RSP_BUSY)
 312                 cmdreg |= 1 << 11;
 313
 314         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 315                 cmdreg |= 1 << 15;
 316
 317         OMAP_MMC_WRITE(host, CTO, 200);
 318         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 319         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 320         OMAP_MMC_WRITE(host, IE,
 321                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 322                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 323                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 324                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 325                        OMAP_MMC_STAT_END_OF_DATA);
 326         OMAP_MMC_WRITE(host, CMD, cmdreg);
 327 }
 328
 329 static void
 330 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 331                      int abort)
 332 {
 333         enum dma_data_direction dma_data_dir;
 334
 335         BUG_ON(host->dma_ch < 0);
 336         if (data->error)
 337                 omap_stop_dma(host->dma_ch);
 338         /* Release DMA channel lazily */
 339         mod_timer(&host->dma_timer, jiffies + HZ);
 340         if (data->flags & MMC_DATA_WRITE)
 341                 dma_data_dir = DMA_TO_DEVICE;
 342         else
 343                 dma_data_dir = DMA_FROM_DEVICE;
 344         dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 345                      dma_data_dir);
 346 }
 347
 348 static void
 349 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 350 {
 351         if (host->dma_in_use)
 352                 mmc_omap_release_dma(host, data, data->error);
 353
 354         host->data = NULL;
 355         host->sg_len = 0;
 356
 357         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 358          * dozens of requests until the card finishes writing data.
 359          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 360          */
 361
 362         if (!data->stop) {
 363                 struct mmc_host *mmc;
 364
 365                 host->mrq = NULL;
 366                 mmc = host->mmc;
 367                 mmc_omap_release_slot(host->current_slot);
 368                 mmc_request_done(mmc, data->mrq);
 369                 return;
 370         }
 371
 372         mmc_omap_start_command(host, data->stop);
 373 }
 374
 375 static void
 376 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 377 {
 378         int loops;
 379         u16 ie;
 380
 381         if (host->dma_in_use)
 382                 mmc_omap_release_dma(host, data, 1);
 383
 384         host->data = NULL;
 385         host->sg_len = 0;
 386
 387         ie = OMAP_MMC_READ(host, IE);
 388         OMAP_MMC_WRITE(host, IE, 0);
 389         OMAP_MMC_WRITE(host, CMD, 1 << 7);
 390         loops = 0;
 391         while (!(OMAP_MMC_READ(host, STAT) & OMAP_MMC_STAT_END_OF_CMD)) {
 392                 udelay(1);
 393                 loops++;
 394                 if (loops == 100000)
 395                         break;
 396         }
 397         OMAP_MMC_WRITE(host, STAT, OMAP_MMC_STAT_END_OF_CMD);
 398         OMAP_MMC_WRITE(host, IE, ie);
 399 }
 400
 401 static void
 402 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 403 {
 404         unsigned long flags;
 405         int done;
 406
 407         if (!host->dma_in_use) {
 408                 mmc_omap_xfer_done(host, data);
 409                 return;
 410         }
 411         done = 0;
 412         spin_lock_irqsave(&host->dma_lock, flags);
 413         if (host->dma_done)
 414                 done = 1;
 415         else
 416                 host->brs_received = 1;
 417         spin_unlock_irqrestore(&host->dma_lock, flags);
 418         if (done)
 419                 mmc_omap_xfer_done(host, data);
 420 }
 421
 422 static void
 423 mmc_omap_dma_timer(unsigned long data)
 424 {
 425         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 426
 427         BUG_ON(host->dma_ch < 0);
 428         omap_free_dma(host->dma_ch);
 429         host->dma_ch = -1;
 430 }
 431
 432 static void
 433 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 434 {
 435         unsigned long flags;
 436         int done;
 437
 438         done = 0;
 439         spin_lock_irqsave(&host->dma_lock, flags);
 440         if (host->brs_received)
 441                 done = 1;
 442         else
 443                 host->dma_done = 1;
 444         spin_unlock_irqrestore(&host->dma_lock, flags);
 445         if (done)
 446                 mmc_omap_xfer_done(host, data);
 447 }
 448
 449 static void
 450 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 451 {
 452         host->cmd = NULL;
 453
 454         if (cmd->flags & MMC_RSP_PRESENT) {
 455                 if (cmd->flags & MMC_RSP_136) {
 456                         /* response type 2 */
 457                         cmd->resp[3] =
 458                                 OMAP_MMC_READ(host, RSP0) |
 459                                 (OMAP_MMC_READ(host, RSP1) << 16);
 460                         cmd->resp[2] =
 461                                 OMAP_MMC_READ(host, RSP2) |
 462                                 (OMAP_MMC_READ(host, RSP3) << 16);
 463                         cmd->resp[1] =
 464                                 OMAP_MMC_READ(host, RSP4) |
 465                                 (OMAP_MMC_READ(host, RSP5) << 16);
 466                         cmd->resp[0] =
 467                                 OMAP_MMC_READ(host, RSP6) |
 468                                 (OMAP_MMC_READ(host, RSP7) << 16);
 469                 } else {
 470                         /* response types 1, 1b, 3, 4, 5, 6 */
 471                         cmd->resp[0] =
 472                                 OMAP_MMC_READ(host, RSP6) |
 473                                 (OMAP_MMC_READ(host, RSP7) << 16);
 474                 }
 475         }
 476
 477         if (host->data == NULL || cmd->error) {
 478                 struct mmc_host *mmc;
 479
 480                 if (host->data != NULL)
 481                         mmc_omap_abort_xfer(host, host->data);
 482                 host->mrq = NULL;
 483                 mmc = host->mmc;
 484                 mmc_omap_release_slot(host->current_slot);
 485                 mmc_request_done(mmc, cmd->mrq);
 486         }
 487 }
 488
 489 /* PIO only */
 490 static void
 491 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 492 {
 493         struct scatterlist *sg;
 494
 495         sg = host->data->sg + host->sg_idx;
 496         host->buffer_bytes_left = sg->length;
 497         host->buffer = sg_virt(sg);
 498         if (host->buffer_bytes_left > host->total_bytes_left)
 499                 host->buffer_bytes_left = host->total_bytes_left;
 500 }
 501
 502 /* PIO only */
 503 static void
 504 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 505 {
 506         int n;
 507
 508         if (host->buffer_bytes_left == 0) {
 509                 host->sg_idx++;
 510                 BUG_ON(host->sg_idx == host->sg_len);
 511                 mmc_omap_sg_to_buf(host);
 512         }
 513         n = 64;
 514         if (n > host->buffer_bytes_left)
 515                 n = host->buffer_bytes_left;
 516         host->buffer_bytes_left -= n;
 517         host->total_bytes_left -= n;
 518         host->data->bytes_xfered += n;
 519
 520         if (write) {
 521                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 522         } else {
 523                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 524         }
 525 }
 526
 527 static inline void mmc_omap_report_irq(u16 status)
 528 {
 529         static const char *mmc_omap_status_bits[] = {
 530                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 531                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 532         };
 533         int i, c = 0;
 534
 535         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 536                 if (status & (1 << i)) {
 537                         if (c)
 538                                 printk(" ");
 539                         printk("%s", mmc_omap_status_bits[i]);
 540                         c++;
 541                 }
 542 }
 543
 544 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 545 {
 546         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 547         u16 status;
 548         int end_command;
 549         int end_transfer;
 550         int transfer_error, cmd_error;
 551
 552         if (host->cmd == NULL && host->data == NULL) {
 553                 status = OMAP_MMC_READ(host, STAT);
 554                 dev_info(mmc_dev(host->slots[0]->mmc),
 555                          "Spurious IRQ 0x%04x\n", status);
 556                 if (status != 0) {
 557                         OMAP_MMC_WRITE(host, STAT, status);
 558                         OMAP_MMC_WRITE(host, IE, 0);
 559                 }
 560                 return IRQ_HANDLED;
 561         }
 562
 563         end_command = 0;
 564         end_transfer = 0;
 565         transfer_error = 0;
 566         cmd_error = 0;
 567
 568         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 569                 int cmd;
 570
 571                 OMAP_MMC_WRITE(host, STAT, status);
 572                 if (host->cmd != NULL)
 573                         cmd = host->cmd->opcode;
 574                 else
 575                         cmd = -1;
 576 #ifdef CONFIG_MMC_DEBUG
 577                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 578                         status, cmd);
 579                 mmc_omap_report_irq(status);
 580                 printk("\n");
 581 #endif
 582                 if (host->total_bytes_left) {
 583                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 584                             (status & OMAP_MMC_STAT_END_OF_DATA))
 585                                 mmc_omap_xfer_data(host, 0);
 586                         if (status & OMAP_MMC_STAT_A_EMPTY)
 587                                 mmc_omap_xfer_data(host, 1);
 588                 }
 589
 590                 if (status & OMAP_MMC_STAT_END_OF_DATA)
 591                         end_transfer = 1;
 592
 593                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 594                         dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
 595                                 cmd);
 596                         if (host->data) {
 597                                 host->data->error = -ETIMEDOUT;
 598                                 transfer_error = 1;
 599                         }
 600                 }
 601
 602                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 603                         if (host->data) {
 604                                 host->data->error = -EILSEQ;
 605                                 dev_dbg(mmc_dev(host->mmc),
 606                                          "data CRC error, bytes left %d\n",
 607                                         host->total_bytes_left);
 608                                 transfer_error = 1;
 609                         } else {
 610                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 611                         }
 612                 }
 613
 614                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 615                         /* Timeouts are routine with some commands */
 616                         if (host->cmd) {
 617                                 struct mmc_omap_slot *slot =
 618                                         host->current_slot;
 619                                 if (slot == NULL ||
 620                                     !mmc_omap_cover_is_open(slot))
 621                                         dev_err(mmc_dev(host->mmc),
 622                                                 "command timeout (CMD%d)\n",
 623                                                 cmd);
 624                                 host->cmd->error = -ETIMEDOUT;
 625                                 end_command = 1;
 626                                 cmd_error = 1;
 627                         }
 628                 }
 629
 630                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 631                         if (host->cmd) {
 632                                 dev_err(mmc_dev(host->mmc),
 633                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 634                                         cmd, host->cmd->arg);
 635                                 host->cmd->error = -EILSEQ;
 636                                 end_command = 1;
 637                                 cmd_error = 1;
 638                         } else
 639                                 dev_err(mmc_dev(host->mmc),
 640                                         "command CRC error without cmd?\n");
 641                 }
 642
 643                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 644                         dev_dbg(mmc_dev(host->mmc),
 645                                 "ignoring card status error (CMD%d)\n",
 646                                 cmd);
 647                         end_command = 1;
 648                 }
 649
 650                 /*
 651                  * NOTE: On 1610 the END_OF_CMD may come too early when
 652                  * starting a write
 653                  */
 654                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 655                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 656                         end_command = 1;
 657                 }
 658         }
 659
 660         if (end_command)
 661                 mmc_omap_cmd_done(host, host->cmd);
 662         if (host->data != NULL) {
 663                 if (transfer_error)
 664                         mmc_omap_xfer_done(host, host->data);
 665                 else if (end_transfer)
 666                         mmc_omap_end_of_data(host, host->data);
 667         }
 668
 669         return IRQ_HANDLED;
 670 }
 671
 672 void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed)
 673 {
 674         struct mmc_omap_host *host = dev_get_drvdata(dev);
 675
 676         BUG_ON(slot >= host->nr_slots);
 677
 678         /* Other subsystems can call in here before we're initialised. */
 679         if (host->nr_slots == 0 || !host->slots[slot])
 680                 return;
 681
 682         schedule_work(&host->slots[slot]->switch_work);
 683 }
 684
 685 static void mmc_omap_switch_timer(unsigned long arg)
 686 {
 687         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 688
 689         schedule_work(&slot->switch_work);
 690 }
 691
 692 static void mmc_omap_cover_handler(struct work_struct *work)
 693 {
 694         struct mmc_omap_slot *slot = container_of(work, struct mmc_omap_slot,
 695                                                   switch_work);
 696         int cover_open;
 697
 698         cover_open = mmc_omap_cover_is_open(slot);
 699         if (cover_open != slot->cover_open) {
 700                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 701                 slot->cover_open = cover_open;
 702                 dev_info(mmc_dev(slot->mmc), "cover is now %s\n",
 703                          cover_open ? "open" : "closed");
 704         }
 705         mmc_detect_change(slot->mmc, slot->id);
 706 }
 707
 708 /* Prepare to transfer the next segment of a scatterlist */
 709 static void
 710 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 711 {
 712         int dma_ch = host->dma_ch;
 713         unsigned long data_addr;
 714         u16 buf, frame;
 715         u32 count;
 716         struct scatterlist *sg = &data->sg[host->sg_idx];
 717         int src_port = 0;
 718         int dst_port = 0;
 719         int sync_dev = 0;
 720
 721         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 722         frame = data->blksz;
 723         count = sg_dma_len(sg);
 724
 725         if ((data->blocks == 1) && (count > data->blksz))
 726                 count = frame;
 727
 728         host->dma_len = count;
 729
 730         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 731          * Use 16 or 32 word frames when the blocksize is at least that large.
 732          * Blocksize is usually 512 bytes; but not for some SD reads.
 733          */
 734         if (cpu_is_omap15xx() && frame > 32)
 735                 frame = 32;
 736         else if (frame > 64)
 737                 frame = 64;
 738         count /= frame;
 739         frame >>= 1;
 740
 741         if (!(data->flags & MMC_DATA_WRITE)) {
 742                 buf = 0x800f | ((frame - 1) << 8);
 743
 744                 if (cpu_class_is_omap1()) {
 745                         src_port = OMAP_DMA_PORT_TIPB;
 746                         dst_port = OMAP_DMA_PORT_EMIFF;
 747                 }
 748                 if (cpu_is_omap24xx())
 749                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 750
 751                 omap_set_dma_src_params(dma_ch, src_port,
 752                                         OMAP_DMA_AMODE_CONSTANT,
 753                                         data_addr, 0, 0);
 754                 omap_set_dma_dest_params(dma_ch, dst_port,
 755                                          OMAP_DMA_AMODE_POST_INC,
 756                                          sg_dma_address(sg), 0, 0);
 757                 omap_set_dma_dest_data_pack(dma_ch, 1);
 758                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 759         } else {
 760                 buf = 0x0f80 | ((frame - 1) << 0);
 761
 762                 if (cpu_class_is_omap1()) {
 763                         src_port = OMAP_DMA_PORT_EMIFF;
 764                         dst_port = OMAP_DMA_PORT_TIPB;
 765                 }
 766                 if (cpu_is_omap24xx())
 767                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 768
 769                 omap_set_dma_dest_params(dma_ch, dst_port,
 770                                          OMAP_DMA_AMODE_CONSTANT,
 771                                          data_addr, 0, 0);
 772                 omap_set_dma_src_params(dma_ch, src_port,
 773                                         OMAP_DMA_AMODE_POST_INC,
 774                                         sg_dma_address(sg), 0, 0);
 775                 omap_set_dma_src_data_pack(dma_ch, 1);
 776                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 777         }
 778
 779         /* Max limit for DMA frame count is 0xffff */
 780         BUG_ON(count > 0xffff);
 781
 782         OMAP_MMC_WRITE(host, BUF, buf);
 783         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 784                                      frame, count, OMAP_DMA_SYNC_FRAME,
 785                                      sync_dev, 0);
 786 }
 787
 788 /* A scatterlist segment completed */
 789 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 790 {
 791         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 792         struct mmc_data *mmcdat = host->data;
 793
 794         if (unlikely(host->dma_ch < 0)) {
 795                 dev_err(mmc_dev(host->mmc),
 796                         "DMA callback while DMA not enabled\n");
 797                 return;
 798         }
 799         /* FIXME: We really should do something to _handle_ the errors */
 800         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 801                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 802                 return;
 803         }
 804         if (ch_status & OMAP_DMA_DROP_IRQ) {
 805                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 806                 return;
 807         }
 808         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 809                 return;
 810         }
 811         mmcdat->bytes_xfered += host->dma_len;
 812         host->sg_idx++;
 813         if (host->sg_idx < host->sg_len) {
 814                 mmc_omap_prepare_dma(host, host->data);
 815                 omap_start_dma(host->dma_ch);
 816         } else
 817                 mmc_omap_dma_done(host, host->data);
 818 }
 819
 820 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 821 {
 822         const char *dev_name;
 823         int sync_dev, dma_ch, is_read, r;
 824
 825         is_read = !(data->flags & MMC_DATA_WRITE);
 826         del_timer_sync(&host->dma_timer);
 827         if (host->dma_ch >= 0) {
 828                 if (is_read == host->dma_is_read)
 829                         return 0;
 830                 omap_free_dma(host->dma_ch);
 831                 host->dma_ch = -1;
 832         }
 833
 834         if (is_read) {
 835                 if (host->id == 1) {
 836                         sync_dev = OMAP_DMA_MMC_RX;
 837                         dev_name = "MMC1 read";
 838                 } else {
 839                         sync_dev = OMAP_DMA_MMC2_RX;
 840                         dev_name = "MMC2 read";
 841                 }
 842         } else {
 843                 if (host->id == 1) {
 844                         sync_dev = OMAP_DMA_MMC_TX;
 845                         dev_name = "MMC1 write";
 846                 } else {
 847                         sync_dev = OMAP_DMA_MMC2_TX;
 848                         dev_name = "MMC2 write";
 849                 }
 850         }
 851         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 852                              host, &dma_ch);
 853         if (r != 0) {
 854                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 855                 return r;
 856         }
 857         host->dma_ch = dma_ch;
 858         host->dma_is_read = is_read;
 859
 860         return 0;
 861 }
 862
 863 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 864 {
 865         u16 reg;
 866
 867         reg = OMAP_MMC_READ(host, SDIO);
 868         reg &= ~(1 << 5);
 869         OMAP_MMC_WRITE(host, SDIO, reg);
 870         /* Set maximum timeout */
 871         OMAP_MMC_WRITE(host, CTO, 0xff);
 872 }
 873
 874 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 875 {
 876         unsigned int timeout, cycle_ns;
 877         u16 reg;
 878
 879         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
 880         timeout = req->data->timeout_ns / cycle_ns;
 881         timeout += req->data->timeout_clks;
 882
 883         /* Check if we need to use timeout multiplier register */
 884         reg = OMAP_MMC_READ(host, SDIO);
 885         if (timeout > 0xffff) {
 886                 reg |= (1 << 5);
 887                 timeout /= 1024;
 888         } else
 889                 reg &= ~(1 << 5);
 890         OMAP_MMC_WRITE(host, SDIO, reg);
 891         OMAP_MMC_WRITE(host, DTO, timeout);
 892 }
 893
 894 static void
 895 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 896 {
 897         struct mmc_data *data = req->data;
 898         int i, use_dma, block_size;
 899         unsigned sg_len;
 900
 901         host->data = data;
 902         if (data == NULL) {
 903                 OMAP_MMC_WRITE(host, BLEN, 0);
 904                 OMAP_MMC_WRITE(host, NBLK, 0);
 905                 OMAP_MMC_WRITE(host, BUF, 0);
 906                 host->dma_in_use = 0;
 907                 set_cmd_timeout(host, req);
 908                 return;
 909         }
 910
 911         block_size = data->blksz;
 912
 913         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 914         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 915         set_data_timeout(host, req);
 916
 917         /* cope with calling layer confusion; it issues "single
 918          * block" writes using multi-block scatterlists.
 919          */
 920         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 921
 922         /* Only do DMA for entire blocks */
 923         use_dma = host->use_dma;
 924         if (use_dma) {
 925                 for (i = 0; i < sg_len; i++) {
 926                         if ((data->sg[i].length % block_size) != 0) {
 927                                 use_dma = 0;
 928                                 break;
 929                         }
 930                 }
 931         }
 932
 933         host->sg_idx = 0;
 934         if (use_dma) {
 935                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 936                         enum dma_data_direction dma_data_dir;
 937
 938                         if (data->flags & MMC_DATA_WRITE)
 939                                 dma_data_dir = DMA_TO_DEVICE;
 940                         else
 941                                 dma_data_dir = DMA_FROM_DEVICE;
 942
 943                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 944                                                 sg_len, dma_data_dir);
 945                         host->total_bytes_left = 0;
 946                         mmc_omap_prepare_dma(host, req->data);
 947                         host->brs_received = 0;
 948                         host->dma_done = 0;
 949                         host->dma_in_use = 1;
 950                 } else
 951                         use_dma = 0;
 952         }
 953
 954         /* Revert to PIO? */
 955         if (!use_dma) {
 956                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 957                 host->total_bytes_left = data->blocks * block_size;
 958                 host->sg_len = sg_len;
 959                 mmc_omap_sg_to_buf(host);
 960                 host->dma_in_use = 0;
 961         }
 962 }
 963
 964 static void mmc_omap_start_request(struct mmc_omap_host *host,
 965                                    struct mmc_request *req)
 966 {
 967         BUG_ON(host->mrq != NULL);
 968
 969         host->mrq = req;
 970
 971         /* only touch fifo AFTER the controller readies it */
 972         mmc_omap_prepare_data(host, req);
 973         mmc_omap_start_command(host, req->cmd);
 974         if (host->dma_in_use)
 975                 omap_start_dma(host->dma_ch);
 976         BUG_ON(irqs_disabled());
 977 }
 978
 979 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 980 {
 981         struct mmc_omap_slot *slot = mmc_priv(mmc);
 982         struct mmc_omap_host *host = slot->host;
 983         unsigned long flags;
 984
 985         spin_lock_irqsave(&host->slot_lock, flags);
 986         if (host->mmc != NULL) {
 987                 BUG_ON(slot->mrq != NULL);
 988                 slot->mrq = req;
 989                 spin_unlock_irqrestore(&host->slot_lock, flags);
 990                 return;
 991         } else
 992                 host->mmc = mmc;
 993         spin_unlock_irqrestore(&host->slot_lock, flags);
 994         mmc_omap_select_slot(slot, 1);
 995         mmc_omap_start_request(host, req);
 996 }
 997
 998 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
 999                                 int vdd)
1000 {
1001         struct mmc_omap_host *host;
1002
1003         host = slot->host;
1004
1005         if (slot->pdata->set_power != NULL)
1006                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1007                                         vdd);
1008
1009         if (cpu_is_omap24xx()) {
1010                 u16 w;
1011
1012                 if (power_on) {
1013                         w = OMAP_MMC_READ(host, CON);
1014                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1015                 } else {
1016                         w = OMAP_MMC_READ(host, CON);
1017                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1018                 }
1019         }
1020 }
1021
1022 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1023 {
1024         struct mmc_omap_slot *slot = mmc_priv(mmc);
1025         struct mmc_omap_host *host = slot->host;
1026         int func_clk_rate = clk_get_rate(host->fclk);
1027         int dsor;
1028
1029         if (ios->clock == 0)
1030                 return 0;
1031
1032         dsor = func_clk_rate / ios->clock;
1033         if (dsor < 1)
1034                 dsor = 1;
1035
1036         if (func_clk_rate / dsor > ios->clock)
1037                 dsor++;
1038
1039         if (dsor > 250)
1040                 dsor = 250;
1041
1042         slot->fclk_freq = func_clk_rate / dsor;
1043
1044         if (ios->bus_width == MMC_BUS_WIDTH_4)
1045                 dsor |= 1 << 15;
1046
1047         return dsor;
1048 }
1049
1050 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1051 {
1052         struct mmc_omap_slot *slot = mmc_priv(mmc);
1053         struct mmc_omap_host *host = slot->host;
1054         int i, dsor;
1055
1056         dsor = mmc_omap_calc_divisor(mmc, ios);
1057
1058         mmc_omap_select_slot(slot, 0);
1059
1060         if (ios->vdd != slot->vdd)
1061                 slot->vdd = ios->vdd;
1062
1063         switch (ios->power_mode) {
1064         case MMC_POWER_OFF:
1065                 mmc_omap_set_power(slot, 0, ios->vdd);
1066                 break;
1067         case MMC_POWER_UP:
1068                 /* Cannot touch dsor yet, just power up MMC */
1069                 mmc_omap_set_power(slot, 1, ios->vdd);
1070                 goto exit;
1071         case MMC_POWER_ON:
1072                 dsor |= 1 << 11;
1073                 break;
1074         }
1075
1076         if (slot->bus_mode != ios->bus_mode) {
1077                 if (slot->pdata->set_bus_mode != NULL)
1078                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1079                                                   ios->bus_mode);
1080                 slot->bus_mode = ios->bus_mode;
1081         }
1082
1083         /* On insanely high arm_per frequencies something sometimes
1084          * goes somehow out of sync, and the POW bit is not being set,
1085          * which results in the while loop below getting stuck.
1086          * Writing to the CON register twice seems to do the trick. */
1087         for (i = 0; i < 2; i++)
1088                 OMAP_MMC_WRITE(host, CON, dsor);
1089         slot->saved_con = dsor;
1090         if (ios->power_mode == MMC_POWER_ON) {
1091                 /* Send clock cycles, poll completion */
1092                 OMAP_MMC_WRITE(host, IE, 0);
1093                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1094                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1095                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1096                 OMAP_MMC_WRITE(host, STAT, 1);
1097         }
1098
1099 exit:
1100         mmc_omap_release_slot(slot);
1101 }
1102
1103 static const struct mmc_host_ops mmc_omap_ops = {
1104         .request        = mmc_omap_request,
1105         .set_ios        = mmc_omap_set_ios,
1106 };
1107
1108 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1109 {
1110         struct mmc_omap_slot *slot = NULL;
1111         struct mmc_host *mmc;
1112         int r;
1113
1114         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1115         if (mmc == NULL)
1116                 return -ENOMEM;
1117
1118         slot = mmc_priv(mmc);
1119         slot->host = host;
1120         slot->mmc = mmc;
1121         slot->id = id;
1122         slot->pdata = &host->pdata->slots[id];
1123
1124         host->slots[id] = slot;
1125
1126         mmc->caps = MMC_CAP_MULTIWRITE;
1127         if (host->pdata->conf.wire4)
1128                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1129
1130         mmc->ops = &mmc_omap_ops;
1131         mmc->f_min = 400000;
1132
1133         if (cpu_class_is_omap2())
1134                 mmc->f_max = 48000000;
1135         else
1136                 mmc->f_max = 24000000;
1137         if (host->pdata->max_freq)
1138                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1139         mmc->ocr_avail = slot->pdata->ocr_mask;
1140
1141         /* Use scatterlist DMA to reduce per-transfer costs.
1142          * NOTE max_seg_size assumption that small blocks aren't
1143          * normally used (except e.g. for reading SD registers).
1144          */
1145         mmc->max_phys_segs = 32;
1146         mmc->max_hw_segs = 32;
1147         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1148         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1149         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1150         mmc->max_seg_size = mmc->max_req_size;
1151
1152         r = mmc_add_host(mmc);
1153         if (r < 0)
1154                 goto err_remove_host;
1155
1156         if (slot->pdata->name != NULL) {
1157                 r = device_create_file(&mmc->class_dev,
1158                                         &dev_attr_slot_name);
1159                 if (r < 0)
1160                         goto err_remove_host;
1161         }
1162
1163         if (slot->pdata->get_cover_state != NULL) {
1164                 r = device_create_file(&mmc->class_dev,
1165                                         &dev_attr_cover_switch);
1166                 if (r < 0)
1167                         goto err_remove_slot_name;
1168
1169                 INIT_WORK(&slot->switch_work, mmc_omap_cover_handler);
1170                 init_timer(&slot->switch_timer);
1171                 slot->switch_timer.function = mmc_omap_switch_timer;
1172                 slot->switch_timer.data = (unsigned long) slot;
1173                 schedule_work(&slot->switch_work);
1174         }
1175
1176         return 0;
1177
1178 err_remove_slot_name:
1179         if (slot->pdata->name != NULL)
1180                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1181 err_remove_host:
1182         mmc_remove_host(mmc);
1183         mmc_free_host(mmc);
1184         return r;
1185 }
1186
1187 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1188 {
1189         struct mmc_host *mmc = slot->mmc;
1190
1191         if (slot->pdata->name != NULL)
1192                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1193         if (slot->pdata->get_cover_state != NULL)
1194                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1195
1196         del_timer_sync(&slot->switch_timer);
1197         flush_scheduled_work();
1198
1199         mmc_remove_host(mmc);
1200         mmc_free_host(mmc);
1201 }
1202
1203 static int __init mmc_omap_probe(struct platform_device *pdev)
1204 {
1205         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1206         struct mmc_omap_host *host = NULL;
1207         struct resource *res;
1208         int i, ret = 0;
1209         int irq;
1210
1211         if (pdata == NULL) {
1212                 dev_err(&pdev->dev, "platform data missing\n");
1213                 return -ENXIO;
1214         }
1215         if (pdata->nr_slots == 0) {
1216                 dev_err(&pdev->dev, "no slots\n");
1217                 return -ENXIO;
1218         }
1219
1220         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1221         irq = platform_get_irq(pdev, 0);
1222         if (res == NULL || irq < 0)
1223                 return -ENXIO;
1224
1225         res = request_mem_region(res->start, res->end - res->start + 1,
1226                                  pdev->name);
1227         if (res == NULL)
1228                 return -EBUSY;
1229
1230         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1231         if (host == NULL) {
1232                 ret = -ENOMEM;
1233                 goto err_free_mem_region;
1234         }
1235
1236         spin_lock_init(&host->dma_lock);
1237         init_timer(&host->dma_timer);
1238         spin_lock_init(&host->slot_lock);
1239         init_waitqueue_head(&host->slot_wq);
1240
1241         host->dma_timer.function = mmc_omap_dma_timer;
1242         host->dma_timer.data = (unsigned long) host;
1243
1244         host->pdata = pdata;
1245         host->dev = &pdev->dev;
1246         platform_set_drvdata(pdev, host);
1247
1248         host->id = pdev->id;
1249         host->mem_res = res;
1250         host->irq = irq;
1251
1252         host->use_dma = 1;
1253         host->dma_ch = -1;
1254
1255         host->irq = irq;
1256         host->phys_base = host->mem_res->start;
1257         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1258
1259         if (cpu_is_omap24xx()) {
1260                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1261                 if (IS_ERR(host->iclk))
1262                         goto err_free_mmc_host;
1263                 clk_enable(host->iclk);
1264         }
1265
1266         if (!cpu_is_omap24xx())
1267                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1268         else
1269                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1270
1271         if (IS_ERR(host->fclk)) {
1272                 ret = PTR_ERR(host->fclk);
1273                 goto err_free_iclk;
1274         }
1275
1276         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1277         if (ret)
1278                 goto err_free_fclk;
1279
1280         if (pdata->init != NULL) {
1281                 ret = pdata->init(&pdev->dev);
1282                 if (ret < 0)
1283                         goto err_free_irq;
1284         }
1285
1286         host->nr_slots = pdata->nr_slots;
1287         for (i = 0; i < pdata->nr_slots; i++) {
1288                 ret = mmc_omap_new_slot(host, i);
1289                 if (ret < 0) {
1290                         while (--i >= 0)
1291                                 mmc_omap_remove_slot(host->slots[i]);
1292
1293                         goto err_plat_cleanup;
1294                 }
1295         }
1296
1297         return 0;
1298
1299 err_plat_cleanup:
1300         if (pdata->cleanup)
1301                 pdata->cleanup(&pdev->dev);
1302 err_free_irq:
1303         free_irq(host->irq, host);
1304 err_free_fclk:
1305         clk_put(host->fclk);
1306 err_free_iclk:
1307         if (host->iclk != NULL) {
1308                 clk_disable(host->iclk);
1309                 clk_put(host->iclk);
1310         }
1311 err_free_mmc_host:
1312         kfree(host);
1313 err_free_mem_region:
1314         release_mem_region(res->start, res->end - res->start + 1);
1315         return ret;
1316 }
1317
1318 static int mmc_omap_remove(struct platform_device *pdev)
1319 {
1320         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1321         int i;
1322
1323         platform_set_drvdata(pdev, NULL);
1324
1325         BUG_ON(host == NULL);
1326
1327         for (i = 0; i < host->nr_slots; i++)
1328                 mmc_omap_remove_slot(host->slots[i]);
1329
1330         if (host->pdata->cleanup)
1331                 host->pdata->cleanup(&pdev->dev);
1332
1333         if (host->iclk && !IS_ERR(host->iclk))
1334                 clk_put(host->iclk);
1335         if (host->fclk && !IS_ERR(host->fclk))
1336                 clk_put(host->fclk);
1337
1338         release_mem_region(pdev->resource[0].start,
1339                            pdev->resource[0].end - pdev->resource[0].start + 1);
1340
1341         kfree(host);
1342
1343         return 0;
1344 }
1345
1346 #ifdef CONFIG_PM
1347 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1348 {
1349         int i, ret = 0;
1350         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1351
1352         if (host == NULL || host->suspended)
1353                 return 0;
1354
1355         for (i = 0; i < host->nr_slots; i++) {
1356                 struct mmc_omap_slot *slot;
1357
1358                 slot = host->slots[i];
1359                 ret = mmc_suspend_host(slot->mmc, mesg);
1360                 if (ret < 0) {
1361                         while (--i >= 0) {
1362                                 slot = host->slots[i];
1363                                 mmc_resume_host(slot->mmc);
1364                         }
1365                         return ret;
1366                 }
1367         }
1368         host->suspended = 1;
1369         return 0;
1370 }
1371
1372 static int mmc_omap_resume(struct platform_device *pdev)
1373 {
1374         int i, ret = 0;
1375         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1376
1377         if (host == NULL || !host->suspended)
1378                 return 0;
1379
1380         for (i = 0; i < host->nr_slots; i++) {
1381                 struct mmc_omap_slot *slot;
1382                 slot = host->slots[i];
1383                 ret = mmc_resume_host(slot->mmc);
1384                 if (ret < 0)
1385                         return ret;
1386
1387                 host->suspended = 0;
1388         }
1389         return 0;
1390 }
1391 #else
1392 #define mmc_omap_suspend        NULL
1393 #define mmc_omap_resume         NULL
1394 #endif
1395
1396 static struct platform_driver mmc_omap_driver = {
1397         .probe          = mmc_omap_probe,
1398         .remove         = mmc_omap_remove,
1399         .suspend        = mmc_omap_suspend,
1400         .resume         = mmc_omap_resume,
1401         .driver         = {
1402                 .name   = DRIVER_NAME,
1403                 .owner  = THIS_MODULE,
1404         },
1405 };
1406
1407 static int __init mmc_omap_init(void)
1408 {
1409         return platform_driver_register(&mmc_omap_driver);
1410 }
1411
1412 static void __exit mmc_omap_exit(void)
1413 {
1414         platform_driver_unregister(&mmc_omap_driver);
1415 }
1416
1417 module_init(mmc_omap_init);
1418 module_exit(mmc_omap_exit);
1419
1420 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1421 MODULE_LICENSE("GPL");
1422 MODULE_ALIAS("platform:" DRIVER_NAME);
1423 MODULE_AUTHOR("Juha Yrjölä");