drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/mmc.h>
  25 #include <linux/mmc/host.h>
  26 #include <linux/mmc/card.h>
  27 #include <linux/clk.h>
  28 #include <linux/scatterlist.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/mmc.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/dma.h>
  38 #include <asm/arch/mux.h>
  39 #include <asm/arch/fpga.h>
  40 #include <asm/arch/tps65010.h>
  41 #include <asm/arch/board-sx1.h>
  42
  43 #define OMAP_MMC_REG_CMD        0x00
  44 #define OMAP_MMC_REG_ARGL       0x04
  45 #define OMAP_MMC_REG_ARGH       0x08
  46 #define OMAP_MMC_REG_CON        0x0c
  47 #define OMAP_MMC_REG_STAT       0x10
  48 #define OMAP_MMC_REG_IE         0x14
  49 #define OMAP_MMC_REG_CTO        0x18
  50 #define OMAP_MMC_REG_DTO        0x1c
  51 #define OMAP_MMC_REG_DATA       0x20
  52 #define OMAP_MMC_REG_BLEN       0x24
  53 #define OMAP_MMC_REG_NBLK       0x28
  54 #define OMAP_MMC_REG_BUF        0x2c
  55 #define OMAP_MMC_REG_SDIO       0x34
  56 #define OMAP_MMC_REG_REV        0x3c
  57 #define OMAP_MMC_REG_RSP0       0x40
  58 #define OMAP_MMC_REG_RSP1       0x44
  59 #define OMAP_MMC_REG_RSP2       0x48
  60 #define OMAP_MMC_REG_RSP3       0x4c
  61 #define OMAP_MMC_REG_RSP4       0x50
  62 #define OMAP_MMC_REG_RSP5       0x54
  63 #define OMAP_MMC_REG_RSP6       0x58
  64 #define OMAP_MMC_REG_RSP7       0x5c
  65 #define OMAP_MMC_REG_IOSR       0x60
  66 #define OMAP_MMC_REG_SYSC       0x64
  67 #define OMAP_MMC_REG_SYSS       0x68
  68
  69 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  70 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  71 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  72 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  73 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  74 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  75 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  76 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  77 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  78 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  79 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  80 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  81 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  82
  83 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  84 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  85
  86 /*
  87  * Command types
  88  */
  89 #define OMAP_MMC_CMDTYPE_BC     0
  90 #define OMAP_MMC_CMDTYPE_BCR    1
  91 #define OMAP_MMC_CMDTYPE_AC     2
  92 #define OMAP_MMC_CMDTYPE_ADTC   3
  93
  94
  95 #define DRIVER_NAME "mmci-omap"
  96
  97 /* Specifies how often in millisecs to poll for card status changes
  98  * when the cover switch is open */
  99 #define OMAP_MMC_SWITCH_POLL_DELAY      500
 100
 101 struct mmc_omap_host;
 102
 103 struct mmc_omap_slot {
 104         int                     id;
 105         unsigned int            vdd;
 106         u16                     saved_con;
 107         u16                     bus_mode;
 108         unsigned int            fclk_freq;
 109         unsigned                powered:1;
 110
 111         struct work_struct      switch_work;
 112         struct timer_list       switch_timer;
 113         unsigned                cover_open;
 114
 115         struct mmc_request      *mrq;
 116         struct mmc_omap_host    *host;
 117         struct mmc_host         *mmc;
 118         struct omap_mmc_slot_data *pdata;
 119 };
 120
 121 struct mmc_omap_host {
 122         int                     initialized;
 123         int                     suspended;
 124         struct mmc_request *    mrq;
 125         struct mmc_command *    cmd;
 126         struct mmc_data *       data;
 127         struct mmc_host *       mmc;
 128         struct device *         dev;
 129         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 130         struct clk *            iclk;
 131         struct clk *            fclk;
 132         struct resource         *mem_res;
 133         void __iomem            *virt_base;
 134         unsigned int            phys_base;
 135         int                     irq;
 136         unsigned char           bus_mode;
 137         unsigned char           hw_bus_mode;
 138
 139         unsigned int            sg_len;
 140         int                     sg_idx;
 141         u16 *                   buffer;
 142         u32                     buffer_bytes_left;
 143         u32                     total_bytes_left;
 144
 145         unsigned                use_dma:1;
 146         unsigned                brs_received:1, dma_done:1;
 147         unsigned                dma_is_read:1;
 148         unsigned                dma_in_use:1;
 149         int                     dma_ch;
 150         spinlock_t              dma_lock;
 151         struct timer_list       dma_timer;
 152         unsigned                dma_len;
 153
 154         short                   power_pin;
 155
 156         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 157         struct mmc_omap_slot    *current_slot;
 158         spinlock_t              slot_lock;
 159         wait_queue_head_t       slot_wq;
 160         int                     nr_slots;
 161
 162         struct omap_mmc_platform_data *pdata;
 163 };
 164
 165 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 166 {
 167         struct mmc_omap_host *host = slot->host;
 168         unsigned long flags;
 169
 170         if (claimed)
 171                 goto no_claim;
 172         spin_lock_irqsave(&host->slot_lock, flags);
 173         while (host->mmc != NULL) {
 174                 spin_unlock_irqrestore(&host->slot_lock, flags);
 175                 wait_event(host->slot_wq, host->mmc == NULL);
 176                 spin_lock_irqsave(&host->slot_lock, flags);
 177         }
 178         host->mmc = slot->mmc;
 179         spin_unlock_irqrestore(&host->slot_lock, flags);
 180 no_claim:
 181         clk_enable(host->fclk);
 182         if (host->current_slot != slot) {
 183                 if (host->pdata->switch_slot != NULL)
 184                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 185                 host->current_slot = slot;
 186         }
 187
 188         /* Doing the dummy read here seems to work around some bug
 189          * at least in OMAP24xx silicon where the command would not
 190          * start after writing the CMD register. Sigh. */
 191         OMAP_MMC_READ(host, CON);
 192
 193         OMAP_MMC_WRITE(host, CON, slot->saved_con);
 194 }
 195
 196 static void mmc_omap_start_request(struct mmc_omap_host *host,
 197                                    struct mmc_request *req);
 198
 199 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
 200 {
 201         struct mmc_omap_host *host = slot->host;
 202         unsigned long flags;
 203         int i;
 204
 205         BUG_ON(slot == NULL || host->mmc == NULL);
 206         clk_disable(host->fclk);
 207
 208         spin_lock_irqsave(&host->slot_lock, flags);
 209         /* Check for any pending requests */
 210         for (i = 0; i < host->nr_slots; i++) {
 211                 struct mmc_omap_slot *new_slot;
 212                 struct mmc_request *rq;
 213
 214                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 215                         continue;
 216
 217                 new_slot = host->slots[i];
 218                 /* The current slot should not have a request in queue */
 219                 BUG_ON(new_slot == host->current_slot);
 220
 221                 host->mmc = new_slot->mmc;
 222                 spin_unlock_irqrestore(&host->slot_lock, flags);
 223                 mmc_omap_select_slot(new_slot, 1);
 224                 rq = new_slot->mrq;
 225                 new_slot->mrq = NULL;
 226                 mmc_omap_start_request(host, rq);
 227                 return;
 228         }
 229
 230         host->mmc = NULL;
 231         wake_up(&host->slot_wq);
 232         spin_unlock_irqrestore(&host->slot_lock, flags);
 233 }
 234
 235 static inline
 236 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 237 {
 238         return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
 239 }
 240
 241 static ssize_t
 242 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 243                            char *buf)
 244 {
 245         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 246         struct mmc_omap_slot *slot = mmc_priv(mmc);
 247
 248         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 249                        "closed");
 250 }
 251
 252 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 253
 254 /* Access to the R/O switch is required for production testing
 255  * purposes. */
 256 static ssize_t
 257 mmc_omap_show_ro(struct device *dev, struct device_attribute *attr, char *buf)
 258 {
 259         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 260         struct mmc_omap_slot *slot = mmc_priv(mmc);
 261
 262         return sprintf(buf, "%d\n", slot->pdata->get_ro(mmc_dev(mmc),
 263                                                         slot->id));
 264 }
 265
 266 static DEVICE_ATTR(ro, S_IRUGO, mmc_omap_show_ro, NULL);
 267
 268 static ssize_t
 269 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 270                         char *buf)
 271 {
 272         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 273         struct mmc_omap_slot *slot = mmc_priv(mmc);
 274
 275         return sprintf(buf, "%s\n", slot->pdata->name);
 276 }
 277
 278 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 279
 280 static void
 281 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 282 {
 283         u32 cmdreg;
 284         u32 resptype;
 285         u32 cmdtype;
 286
 287         host->cmd = cmd;
 288
 289         resptype = 0;
 290         cmdtype = 0;
 291
 292         /* Our hardware needs to know exact type */
 293         switch (mmc_resp_type(cmd)) {
 294         case MMC_RSP_NONE:
 295                 break;
 296         case MMC_RSP_R1:
 297         case MMC_RSP_R1B:
 298                 /* resp 1, 1b, 6, 7 */
 299                 resptype = 1;
 300                 break;
 301         case MMC_RSP_R2:
 302                 resptype = 2;
 303                 break;
 304         case MMC_RSP_R3:
 305                 resptype = 3;
 306                 break;
 307         default:
 308                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 309                 break;
 310         }
 311
 312         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 313                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 314         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 315                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 316         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 317                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 318         } else {
 319                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 320         }
 321
 322         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 323
 324         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 325                 cmdreg |= 1 << 6;
 326
 327         if (cmd->flags & MMC_RSP_BUSY)
 328                 cmdreg |= 1 << 11;
 329
 330         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 331                 cmdreg |= 1 << 15;
 332
 333         OMAP_MMC_WRITE(host, CTO, 200);
 334         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 335         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 336         OMAP_MMC_WRITE(host, IE,
 337                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 338                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 339                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 340                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 341                        OMAP_MMC_STAT_END_OF_DATA);
 342         OMAP_MMC_WRITE(host, CMD, cmdreg);
 343 }
 344
 345 static void
 346 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 347                      int abort)
 348 {
 349         enum dma_data_direction dma_data_dir;
 350
 351         BUG_ON(host->dma_ch < 0);
 352         if (data->error)
 353                 omap_stop_dma(host->dma_ch);
 354         /* Release DMA channel lazily */
 355         mod_timer(&host->dma_timer, jiffies + HZ);
 356         if (data->flags & MMC_DATA_WRITE)
 357                 dma_data_dir = DMA_TO_DEVICE;
 358         else
 359                 dma_data_dir = DMA_FROM_DEVICE;
 360         dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 361                      dma_data_dir);
 362 }
 363
 364 static void
 365 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 366 {
 367         if (host->dma_in_use)
 368                 mmc_omap_release_dma(host, data, data->error);
 369
 370         host->data = NULL;
 371         host->sg_len = 0;
 372
 373         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 374          * dozens of requests until the card finishes writing data.
 375          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 376          */
 377
 378         if (!data->stop) {
 379                 struct mmc_host *mmc;
 380
 381                 host->mrq = NULL;
 382                 mmc = host->mmc;
 383                 mmc_omap_release_slot(host->current_slot);
 384                 mmc_request_done(mmc, data->mrq);
 385                 return;
 386         }
 387
 388         mmc_omap_start_command(host, data->stop);
 389 }
 390
 391 static void
 392 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 393 {
 394         int loops;
 395         u16 ie;
 396
 397         if (host->dma_in_use)
 398                 mmc_omap_release_dma(host, data, 1);
 399
 400         host->data = NULL;
 401         host->sg_len = 0;
 402
 403         ie = OMAP_MMC_READ(host, IE);
 404         OMAP_MMC_WRITE(host, IE, 0);
 405         OMAP_MMC_WRITE(host, CMD, 1 << 7);
 406         loops = 0;
 407         while (!(OMAP_MMC_READ(host, STAT) & OMAP_MMC_STAT_END_OF_CMD)) {
 408                 udelay(1);
 409                 loops++;
 410                 if (loops == 100000)
 411                         break;
 412         }
 413         OMAP_MMC_WRITE(host, STAT, OMAP_MMC_STAT_END_OF_CMD);
 414         OMAP_MMC_WRITE(host, IE, ie);
 415 }
 416
 417 static void
 418 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 419 {
 420         unsigned long flags;
 421         int done;
 422
 423         if (!host->dma_in_use) {
 424                 mmc_omap_xfer_done(host, data);
 425                 return;
 426         }
 427         done = 0;
 428         spin_lock_irqsave(&host->dma_lock, flags);
 429         if (host->dma_done)
 430                 done = 1;
 431         else
 432                 host->brs_received = 1;
 433         spin_unlock_irqrestore(&host->dma_lock, flags);
 434         if (done)
 435                 mmc_omap_xfer_done(host, data);
 436 }
 437
 438 static void
 439 mmc_omap_dma_timer(unsigned long data)
 440 {
 441         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 442
 443         BUG_ON(host->dma_ch < 0);
 444         omap_free_dma(host->dma_ch);
 445         host->dma_ch = -1;
 446 }
 447
 448 static void
 449 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 450 {
 451         unsigned long flags;
 452         int done;
 453
 454         done = 0;
 455         spin_lock_irqsave(&host->dma_lock, flags);
 456         if (host->brs_received)
 457                 done = 1;
 458         else
 459                 host->dma_done = 1;
 460         spin_unlock_irqrestore(&host->dma_lock, flags);
 461         if (done)
 462                 mmc_omap_xfer_done(host, data);
 463 }
 464
 465 static void
 466 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 467 {
 468         host->cmd = NULL;
 469
 470         if (cmd->flags & MMC_RSP_PRESENT) {
 471                 if (cmd->flags & MMC_RSP_136) {
 472                         /* response type 2 */
 473                         cmd->resp[3] =
 474                                 OMAP_MMC_READ(host, RSP0) |
 475                                 (OMAP_MMC_READ(host, RSP1) << 16);
 476                         cmd->resp[2] =
 477                                 OMAP_MMC_READ(host, RSP2) |
 478                                 (OMAP_MMC_READ(host, RSP3) << 16);
 479                         cmd->resp[1] =
 480                                 OMAP_MMC_READ(host, RSP4) |
 481                                 (OMAP_MMC_READ(host, RSP5) << 16);
 482                         cmd->resp[0] =
 483                                 OMAP_MMC_READ(host, RSP6) |
 484                                 (OMAP_MMC_READ(host, RSP7) << 16);
 485                 } else {
 486                         /* response types 1, 1b, 3, 4, 5, 6 */
 487                         cmd->resp[0] =
 488                                 OMAP_MMC_READ(host, RSP6) |
 489                                 (OMAP_MMC_READ(host, RSP7) << 16);
 490                 }
 491         }
 492
 493         if (host->data == NULL || cmd->error) {
 494                 struct mmc_host *mmc;
 495
 496                 if (host->data != NULL)
 497                         mmc_omap_abort_xfer(host, host->data);
 498                 host->mrq = NULL;
 499                 mmc = host->mmc;
 500                 mmc_omap_release_slot(host->current_slot);
 501                 mmc_request_done(mmc, cmd->mrq);
 502         }
 503 }
 504
 505 /* PIO only */
 506 static void
 507 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 508 {
 509         struct scatterlist *sg;
 510
 511         sg = host->data->sg + host->sg_idx;
 512         host->buffer_bytes_left = sg->length;
 513         host->buffer = sg_virt(sg);
 514         if (host->buffer_bytes_left > host->total_bytes_left)
 515                 host->buffer_bytes_left = host->total_bytes_left;
 516 }
 517
 518 /* PIO only */
 519 static void
 520 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 521 {
 522         int n;
 523
 524         if (host->buffer_bytes_left == 0) {
 525                 host->sg_idx++;
 526                 BUG_ON(host->sg_idx == host->sg_len);
 527                 mmc_omap_sg_to_buf(host);
 528         }
 529         n = 64;
 530         if (n > host->buffer_bytes_left)
 531                 n = host->buffer_bytes_left;
 532         host->buffer_bytes_left -= n;
 533         host->total_bytes_left -= n;
 534         host->data->bytes_xfered += n;
 535
 536         if (write) {
 537                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 538         } else {
 539                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 540         }
 541 }
 542
 543 static inline void mmc_omap_report_irq(u16 status)
 544 {
 545         static const char *mmc_omap_status_bits[] = {
 546                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 547                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 548         };
 549         int i, c = 0;
 550
 551         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 552                 if (status & (1 << i)) {
 553                         if (c)
 554                                 printk(" ");
 555                         printk("%s", mmc_omap_status_bits[i]);
 556                         c++;
 557                 }
 558 }
 559
 560 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 561 {
 562         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 563         u16 status;
 564         int end_command;
 565         int end_transfer;
 566         int transfer_error;
 567
 568         if (host->cmd == NULL && host->data == NULL) {
 569                 status = OMAP_MMC_READ(host, STAT);
 570                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 571                 if (status != 0) {
 572                         OMAP_MMC_WRITE(host, STAT, status);
 573                         OMAP_MMC_WRITE(host, IE, 0);
 574                 }
 575                 return IRQ_HANDLED;
 576         }
 577
 578         end_command = 0;
 579         end_transfer = 0;
 580         transfer_error = 0;
 581
 582         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 583                 OMAP_MMC_WRITE(host, STAT, status);
 584 #ifdef CONFIG_MMC_DEBUG
 585                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 586                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 587                 mmc_omap_report_irq(status);
 588                 printk("\n");
 589 #endif
 590                 if (host->total_bytes_left) {
 591                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 592                             (status & OMAP_MMC_STAT_END_OF_DATA))
 593                                 mmc_omap_xfer_data(host, 0);
 594                         if (status & OMAP_MMC_STAT_A_EMPTY)
 595                                 mmc_omap_xfer_data(host, 1);
 596                 }
 597
 598                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 599                         end_transfer = 1;
 600                 }
 601
 602                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 603                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 604                         if (host->data) {
 605                                 host->data->error = -ETIMEDOUT;
 606                                 transfer_error = 1;
 607                         }
 608                 }
 609
 610                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 611                         if (host->data) {
 612                                 host->data->error = -EILSEQ;
 613                                 dev_dbg(mmc_dev(host->mmc),
 614                                          "data CRC error, bytes left %d\n",
 615                                         host->total_bytes_left);
 616                                 transfer_error = 1;
 617                         } else {
 618                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 619                         }
 620                 }
 621
 622                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 623                         /* Timeouts are routine with some commands */
 624                         if (host->cmd) {
 625                                 struct mmc_omap_slot *slot =
 626                                         host->current_slot;
 627                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 628                                                 host->cmd->opcode !=
 629                                                 MMC_SEND_OP_COND &&
 630                                                 host->cmd->opcode !=
 631                                                 MMC_APP_CMD &&
 632                                                 !mmc_omap_cover_is_open(slot))
 633                                         dev_err(mmc_dev(host->mmc),
 634                                                 "command timeout, CMD %d\n",
 635                                                 host->cmd->opcode);
 636                                 host->cmd->error = -ETIMEDOUT;
 637                                 end_command = 1;
 638                         }
 639                 }
 640
 641                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 642                         if (host->cmd) {
 643                                 dev_err(mmc_dev(host->mmc),
 644                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 645                                         host->cmd->opcode, host->cmd->arg);
 646                                 host->cmd->error = -EILSEQ;
 647                                 end_command = 1;
 648                         } else
 649                                 dev_err(mmc_dev(host->mmc),
 650                                         "command CRC error without cmd?\n");
 651                 }
 652
 653                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 654                         dev_dbg(mmc_dev(host->mmc),
 655                                 "ignoring card status error (CMD%d)\n",
 656                                 host->cmd->opcode);
 657                         end_command = 1;
 658                 }
 659
 660                 /*
 661                  * NOTE: On 1610 the END_OF_CMD may come too early when
 662                  * starting a write
 663                  */
 664                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 665                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 666                         end_command = 1;
 667                 }
 668         }
 669
 670         if (end_command) {
 671                 mmc_omap_cmd_done(host, host->cmd);
 672         }
 673         if (transfer_error)
 674                 mmc_omap_xfer_done(host, host->data);
 675         else if (end_transfer)
 676                 mmc_omap_end_of_data(host, host->data);
 677
 678         return IRQ_HANDLED;
 679 }
 680
 681 void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed)
 682 {
 683         struct mmc_omap_host *host = dev_get_drvdata(dev);
 684
 685         BUG_ON(slot >= host->nr_slots);
 686
 687         /* Other subsystems can call in here before we're initialised. */
 688         if (host->nr_slots == 0 || !host->slots[slot])
 689                 return;
 690
 691         schedule_work(&host->slots[slot]->switch_work);
 692 }
 693
 694 static void mmc_omap_switch_timer(unsigned long arg)
 695 {
 696         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 697
 698         schedule_work(&slot->switch_work);
 699 }
 700
 701 static void mmc_omap_cover_handler(struct work_struct *work)
 702 {
 703         struct mmc_omap_slot *slot = container_of(work, struct mmc_omap_slot,
 704                                                   switch_work);
 705         int cover_open;
 706
 707         cover_open = mmc_omap_cover_is_open(slot);
 708         if (cover_open != slot->cover_open) {
 709                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 710                 slot->cover_open = cover_open;
 711                 dev_info(mmc_dev(slot->mmc), "cover is now %s\n",
 712                          cover_open ? "open" : "closed");
 713         }
 714         mmc_detect_change(slot->mmc, slot->id);
 715 }
 716
 717 /* Prepare to transfer the next segment of a scatterlist */
 718 static void
 719 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 720 {
 721         int dma_ch = host->dma_ch;
 722         unsigned long data_addr;
 723         u16 buf, frame;
 724         u32 count;
 725         struct scatterlist *sg = &data->sg[host->sg_idx];
 726         int src_port = 0;
 727         int dst_port = 0;
 728         int sync_dev = 0;
 729
 730         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 731         frame = data->blksz;
 732         count = sg_dma_len(sg);
 733
 734         if ((data->blocks == 1) && (count > data->blksz))
 735                 count = frame;
 736
 737         host->dma_len = count;
 738
 739         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 740          * Use 16 or 32 word frames when the blocksize is at least that large.
 741          * Blocksize is usually 512 bytes; but not for some SD reads.
 742          */
 743         if (cpu_is_omap15xx() && frame > 32)
 744                 frame = 32;
 745         else if (frame > 64)
 746                 frame = 64;
 747         count /= frame;
 748         frame >>= 1;
 749
 750         if (!(data->flags & MMC_DATA_WRITE)) {
 751                 buf = 0x800f | ((frame - 1) << 8);
 752
 753                 if (cpu_class_is_omap1()) {
 754                         src_port = OMAP_DMA_PORT_TIPB;
 755                         dst_port = OMAP_DMA_PORT_EMIFF;
 756                 }
 757                 if (cpu_is_omap24xx())
 758                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 759
 760                 omap_set_dma_src_params(dma_ch, src_port,
 761                                         OMAP_DMA_AMODE_CONSTANT,
 762                                         data_addr, 0, 0);
 763                 omap_set_dma_dest_params(dma_ch, dst_port,
 764                                          OMAP_DMA_AMODE_POST_INC,
 765                                          sg_dma_address(sg), 0, 0);
 766                 omap_set_dma_dest_data_pack(dma_ch, 1);
 767                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 768         } else {
 769                 buf = 0x0f80 | ((frame - 1) << 0);
 770
 771                 if (cpu_class_is_omap1()) {
 772                         src_port = OMAP_DMA_PORT_EMIFF;
 773                         dst_port = OMAP_DMA_PORT_TIPB;
 774                 }
 775                 if (cpu_is_omap24xx())
 776                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 777
 778                 omap_set_dma_dest_params(dma_ch, dst_port,
 779                                          OMAP_DMA_AMODE_CONSTANT,
 780                                          data_addr, 0, 0);
 781                 omap_set_dma_src_params(dma_ch, src_port,
 782                                         OMAP_DMA_AMODE_POST_INC,
 783                                         sg_dma_address(sg), 0, 0);
 784                 omap_set_dma_src_data_pack(dma_ch, 1);
 785                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 786         }
 787
 788         /* Max limit for DMA frame count is 0xffff */
 789         BUG_ON(count > 0xffff);
 790
 791         OMAP_MMC_WRITE(host, BUF, buf);
 792         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 793                                      frame, count, OMAP_DMA_SYNC_FRAME,
 794                                      sync_dev, 0);
 795 }
 796
 797 /* A scatterlist segment completed */
 798 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 799 {
 800         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 801         struct mmc_data *mmcdat = host->data;
 802
 803         if (unlikely(host->dma_ch < 0)) {
 804                 dev_err(mmc_dev(host->mmc),
 805                         "DMA callback while DMA not enabled\n");
 806                 return;
 807         }
 808         /* FIXME: We really should do something to _handle_ the errors */
 809         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 810                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 811                 return;
 812         }
 813         if (ch_status & OMAP_DMA_DROP_IRQ) {
 814                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 815                 return;
 816         }
 817         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 818                 return;
 819         }
 820         mmcdat->bytes_xfered += host->dma_len;
 821         host->sg_idx++;
 822         if (host->sg_idx < host->sg_len) {
 823                 mmc_omap_prepare_dma(host, host->data);
 824                 omap_start_dma(host->dma_ch);
 825         } else
 826                 mmc_omap_dma_done(host, host->data);
 827 }
 828
 829 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 830 {
 831         const char *dev_name;
 832         int sync_dev, dma_ch, is_read, r;
 833
 834         is_read = !(data->flags & MMC_DATA_WRITE);
 835         del_timer_sync(&host->dma_timer);
 836         if (host->dma_ch >= 0) {
 837                 if (is_read == host->dma_is_read)
 838                         return 0;
 839                 omap_free_dma(host->dma_ch);
 840                 host->dma_ch = -1;
 841         }
 842
 843         if (is_read) {
 844                 if (host->id == 1) {
 845                         sync_dev = OMAP_DMA_MMC_RX;
 846                         dev_name = "MMC1 read";
 847                 } else {
 848                         sync_dev = OMAP_DMA_MMC2_RX;
 849                         dev_name = "MMC2 read";
 850                 }
 851         } else {
 852                 if (host->id == 1) {
 853                         sync_dev = OMAP_DMA_MMC_TX;
 854                         dev_name = "MMC1 write";
 855                 } else {
 856                         sync_dev = OMAP_DMA_MMC2_TX;
 857                         dev_name = "MMC2 write";
 858                 }
 859         }
 860         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 861                              host, &dma_ch);
 862         if (r != 0) {
 863                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 864                 return r;
 865         }
 866         host->dma_ch = dma_ch;
 867         host->dma_is_read = is_read;
 868
 869         return 0;
 870 }
 871
 872 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 873 {
 874         u16 reg;
 875
 876         reg = OMAP_MMC_READ(host, SDIO);
 877         reg &= ~(1 << 5);
 878         OMAP_MMC_WRITE(host, SDIO, reg);
 879         /* Set maximum timeout */
 880         OMAP_MMC_WRITE(host, CTO, 0xff);
 881 }
 882
 883 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 884 {
 885         unsigned int timeout, cycle_ns;
 886         u16 reg;
 887
 888         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
 889         timeout = req->data->timeout_ns / cycle_ns;
 890         timeout += req->data->timeout_clks;
 891
 892         /* Check if we need to use timeout multiplier register */
 893         reg = OMAP_MMC_READ(host, SDIO);
 894         if (timeout > 0xffff) {
 895                 reg |= (1 << 5);
 896                 timeout /= 1024;
 897         } else
 898                 reg &= ~(1 << 5);
 899         OMAP_MMC_WRITE(host, SDIO, reg);
 900         OMAP_MMC_WRITE(host, DTO, timeout);
 901 }
 902
 903 static void
 904 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 905 {
 906         struct mmc_data *data = req->data;
 907         int i, use_dma, block_size;
 908         unsigned sg_len;
 909
 910         host->data = data;
 911         if (data == NULL) {
 912                 OMAP_MMC_WRITE(host, BLEN, 0);
 913                 OMAP_MMC_WRITE(host, NBLK, 0);
 914                 OMAP_MMC_WRITE(host, BUF, 0);
 915                 host->dma_in_use = 0;
 916                 set_cmd_timeout(host, req);
 917                 return;
 918         }
 919
 920         block_size = data->blksz;
 921
 922         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 923         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 924         set_data_timeout(host, req);
 925
 926         /* cope with calling layer confusion; it issues "single
 927          * block" writes using multi-block scatterlists.
 928          */
 929         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 930
 931         /* Only do DMA for entire blocks */
 932         use_dma = host->use_dma;
 933         if (use_dma) {
 934                 for (i = 0; i < sg_len; i++) {
 935                         if ((data->sg[i].length % block_size) != 0) {
 936                                 use_dma = 0;
 937                                 break;
 938                         }
 939                 }
 940         }
 941
 942         host->sg_idx = 0;
 943         if (use_dma) {
 944                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 945                         enum dma_data_direction dma_data_dir;
 946
 947                         if (data->flags & MMC_DATA_WRITE)
 948                                 dma_data_dir = DMA_TO_DEVICE;
 949                         else
 950                                 dma_data_dir = DMA_FROM_DEVICE;
 951
 952                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 953                                                 sg_len, dma_data_dir);
 954                         host->total_bytes_left = 0;
 955                         mmc_omap_prepare_dma(host, req->data);
 956                         host->brs_received = 0;
 957                         host->dma_done = 0;
 958                         host->dma_in_use = 1;
 959                 } else
 960                         use_dma = 0;
 961         }
 962
 963         /* Revert to PIO? */
 964         if (!use_dma) {
 965                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 966                 host->total_bytes_left = data->blocks * block_size;
 967                 host->sg_len = sg_len;
 968                 mmc_omap_sg_to_buf(host);
 969                 host->dma_in_use = 0;
 970         }
 971 }
 972
 973 static void mmc_omap_start_request(struct mmc_omap_host *host,
 974                                    struct mmc_request *req)
 975 {
 976         BUG_ON(host->mrq != NULL);
 977
 978         host->mrq = req;
 979
 980         /* only touch fifo AFTER the controller readies it */
 981         mmc_omap_prepare_data(host, req);
 982         mmc_omap_start_command(host, req->cmd);
 983         if (host->dma_in_use)
 984                 omap_start_dma(host->dma_ch);
 985         BUG_ON(irqs_disabled());
 986 }
 987
 988 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 989 {
 990         struct mmc_omap_slot *slot = mmc_priv(mmc);
 991         struct mmc_omap_host *host = slot->host;
 992         unsigned long flags;
 993
 994         spin_lock_irqsave(&host->slot_lock, flags);
 995         if (host->mmc != NULL) {
 996                 BUG_ON(slot->mrq != NULL);
 997                 slot->mrq = req;
 998                 spin_unlock_irqrestore(&host->slot_lock, flags);
 999                 return;
1000         } else
1001                 host->mmc = mmc;
1002         spin_unlock_irqrestore(&host->slot_lock, flags);
1003         mmc_omap_select_slot(slot, 1);
1004         mmc_omap_start_request(host, req);
1005 }
1006
1007 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1008                                 int vdd)
1009 {
1010         struct mmc_omap_host *host;
1011
1012         host = slot->host;
1013
1014         if (slot->pdata->set_power != NULL)
1015                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1016                                         vdd);
1017
1018         if (cpu_is_omap24xx()) {
1019                 u16 w;
1020
1021                 if (power_on) {
1022                         w = OMAP_MMC_READ(host, CON);
1023                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1024                 } else {
1025                         w = OMAP_MMC_READ(host, CON);
1026                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1027                 }
1028         }
1029 }
1030
1031 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1032 {
1033         struct mmc_omap_slot *slot = mmc_priv(mmc);
1034         struct mmc_omap_host *host = slot->host;
1035         int func_clk_rate = clk_get_rate(host->fclk);
1036         int dsor;
1037
1038         if (ios->clock == 0)
1039                 return 0;
1040
1041         dsor = func_clk_rate / ios->clock;
1042         if (dsor < 1)
1043                 dsor = 1;
1044
1045         if (func_clk_rate / dsor > ios->clock)
1046                 dsor++;
1047
1048         if (dsor > 250)
1049                 dsor = 250;
1050
1051         slot->fclk_freq = func_clk_rate / dsor;
1052
1053         if (ios->bus_width == MMC_BUS_WIDTH_4)
1054                 dsor |= 1 << 15;
1055
1056         return dsor;
1057 }
1058
1059 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1060 {
1061         struct mmc_omap_slot *slot = mmc_priv(mmc);
1062         struct mmc_omap_host *host = slot->host;
1063         int i, dsor;
1064
1065         dsor = mmc_omap_calc_divisor(mmc, ios);
1066
1067         mmc_omap_select_slot(slot, 0);
1068
1069         if (ios->vdd != slot->vdd)
1070                 slot->vdd = ios->vdd;
1071
1072         switch (ios->power_mode) {
1073         case MMC_POWER_OFF:
1074                 mmc_omap_set_power(slot, 0, ios->vdd);
1075                 break;
1076         case MMC_POWER_UP:
1077                 /* Cannot touch dsor yet, just power up MMC */
1078                 mmc_omap_set_power(slot, 1, ios->vdd);
1079                 goto exit;
1080         case MMC_POWER_ON:
1081                 dsor |= 1 << 11;
1082                 break;
1083         }
1084
1085         if (slot->bus_mode != ios->bus_mode) {
1086                 if (slot->pdata->set_bus_mode != NULL)
1087                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1088                                                   ios->bus_mode);
1089                 slot->bus_mode = ios->bus_mode;
1090         }
1091
1092         /* On insanely high arm_per frequencies something sometimes
1093          * goes somehow out of sync, and the POW bit is not being set,
1094          * which results in the while loop below getting stuck.
1095          * Writing to the CON register twice seems to do the trick. */
1096         for (i = 0; i < 2; i++)
1097                 OMAP_MMC_WRITE(host, CON, dsor);
1098         slot->saved_con = dsor;
1099         if (ios->power_mode == MMC_POWER_ON) {
1100                 /* Send clock cycles, poll completion */
1101                 OMAP_MMC_WRITE(host, IE, 0);
1102                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1103                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1104                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1105                 OMAP_MMC_WRITE(host, STAT, 1);
1106         }
1107
1108 exit:
1109         mmc_omap_release_slot(slot);
1110 }
1111
1112 static int mmc_omap_get_ro(struct mmc_host *mmc)
1113 {
1114         struct mmc_omap_slot *slot = mmc_priv(mmc);
1115
1116         if (slot->pdata->get_ro != NULL)
1117                 return slot->pdata->get_ro(mmc_dev(mmc), slot->id);
1118         return 0;
1119 }
1120
1121 static const struct mmc_host_ops mmc_omap_ops = {
1122         .request        = mmc_omap_request,
1123         .set_ios        = mmc_omap_set_ios,
1124         .get_ro         = mmc_omap_get_ro,
1125 };
1126
1127 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1128 {
1129         struct mmc_omap_slot *slot = NULL;
1130         struct mmc_host *mmc;
1131         int r;
1132
1133         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1134         if (mmc == NULL)
1135                 return -ENOMEM;
1136
1137         slot = mmc_priv(mmc);
1138         slot->host = host;
1139         slot->mmc = mmc;
1140         slot->id = id;
1141         slot->pdata = &host->pdata->slots[id];
1142
1143         host->slots[id] = slot;
1144
1145         mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
1146                     MMC_CAP_SD_HIGHSPEED;
1147         if (host->pdata->conf.wire4)
1148                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1149
1150         mmc->ops = &mmc_omap_ops;
1151         mmc->f_min = 400000;
1152
1153         if (cpu_class_is_omap2())
1154                 mmc->f_max = 48000000;
1155         else
1156                 mmc->f_max = 24000000;
1157         if (host->pdata->max_freq)
1158                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1159         mmc->ocr_avail = slot->pdata->ocr_mask;
1160
1161         /* Use scatterlist DMA to reduce per-transfer costs.
1162          * NOTE max_seg_size assumption that small blocks aren't
1163          * normally used (except e.g. for reading SD registers).
1164          */
1165         mmc->max_phys_segs = 32;
1166         mmc->max_hw_segs = 32;
1167         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1168         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1169         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1170         mmc->max_seg_size = mmc->max_req_size;
1171
1172         r = mmc_add_host(mmc);
1173         if (r < 0)
1174                 return r;
1175
1176         if (slot->pdata->name != NULL) {
1177                 r = device_create_file(&mmc->class_dev,
1178                                         &dev_attr_slot_name);
1179                 if (r < 0)
1180                         goto err_remove_host;
1181         }
1182
1183         if (slot->pdata->get_cover_state != NULL) {
1184                 r = device_create_file(&mmc->class_dev,
1185                                         &dev_attr_cover_switch);
1186                 if (r < 0)
1187                         goto err_remove_slot_name;
1188
1189                 INIT_WORK(&slot->switch_work, mmc_omap_cover_handler);
1190                 init_timer(&slot->switch_timer);
1191                 slot->switch_timer.function = mmc_omap_switch_timer;
1192                 slot->switch_timer.data = (unsigned long) slot;
1193                 schedule_work(&slot->switch_work);
1194         }
1195
1196         if (slot->pdata->get_ro != NULL) {
1197                 r = device_create_file(&mmc->class_dev,
1198                                         &dev_attr_ro);
1199                 if (r < 0)
1200                         goto err_remove_cover_attr;
1201         }
1202
1203         return 0;
1204
1205 err_remove_cover_attr:
1206         if (slot->pdata->get_cover_state != NULL)
1207                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1208 err_remove_slot_name:
1209         if (slot->pdata->name != NULL)
1210                 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1211 err_remove_host:
1212         mmc_remove_host(mmc);
1213         return r;
1214 }
1215
1216 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1217 {
1218         struct mmc_host *mmc = slot->mmc;
1219
1220         if (slot->pdata->name != NULL)
1221                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1222         if (slot->pdata->get_cover_state != NULL)
1223                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1224         if (slot->pdata->get_ro != NULL)
1225                 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1226
1227         del_timer_sync(&slot->switch_timer);
1228         flush_scheduled_work();
1229
1230         mmc_remove_host(mmc);
1231         mmc_free_host(mmc);
1232 }
1233
1234 static int __init mmc_omap_probe(struct platform_device *pdev)
1235 {
1236         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1237         struct mmc_omap_host *host = NULL;
1238         struct resource *res;
1239         int i, ret = 0;
1240         int irq;
1241
1242         if (pdata == NULL) {
1243                 dev_err(&pdev->dev, "platform data missing\n");
1244                 return -ENXIO;
1245         }
1246         if (pdata->nr_slots == 0) {
1247                 dev_err(&pdev->dev, "no slots\n");
1248                 return -ENXIO;
1249         }
1250
1251         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1252         irq = platform_get_irq(pdev, 0);
1253         if (res == NULL || irq < 0)
1254                 return -ENXIO;
1255
1256         res = request_mem_region(res->start, res->end - res->start + 1,
1257                                  pdev->name);
1258         if (res == NULL)
1259                 return -EBUSY;
1260
1261         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1262         if (host == NULL) {
1263                 ret = -ENOMEM;
1264                 goto err_free_mem_region;
1265         }
1266
1267         spin_lock_init(&host->dma_lock);
1268         init_timer(&host->dma_timer);
1269         spin_lock_init(&host->slot_lock);
1270         init_waitqueue_head(&host->slot_wq);
1271
1272         host->dma_timer.function = mmc_omap_dma_timer;
1273         host->dma_timer.data = (unsigned long) host;
1274
1275         host->pdata = pdata;
1276         host->dev = &pdev->dev;
1277         platform_set_drvdata(pdev, host);
1278
1279         host->id = pdev->id;
1280         host->mem_res = res;
1281         host->irq = irq;
1282
1283         host->use_dma = 1;
1284         host->dma_ch = -1;
1285
1286         host->irq = irq;
1287         host->phys_base = host->mem_res->start;
1288         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1289
1290         if (cpu_is_omap24xx()) {
1291                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1292                 if (IS_ERR(host->iclk))
1293                         goto err_free_mmc_host;
1294                 clk_enable(host->iclk);
1295         }
1296
1297         if (!cpu_is_omap24xx())
1298                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1299         else
1300                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1301
1302         if (IS_ERR(host->fclk)) {
1303                 ret = PTR_ERR(host->fclk);
1304                 goto err_free_iclk;
1305         }
1306
1307         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1308         if (ret)
1309                 goto err_free_fclk;
1310
1311         if (pdata->init != NULL) {
1312                 ret = pdata->init(&pdev->dev);
1313                 if (ret < 0)
1314                         goto err_free_irq;
1315         }
1316
1317         host->nr_slots = pdata->nr_slots;
1318         for (i = 0; i < pdata->nr_slots; i++) {
1319                 ret = mmc_omap_new_slot(host, i);
1320                 if (ret < 0) {
1321                         while (--i >= 0)
1322                                 mmc_omap_remove_slot(host->slots[i]);
1323
1324                         goto err_plat_cleanup;
1325                 }
1326         }
1327
1328         return 0;
1329
1330 err_plat_cleanup:
1331         if (pdata->cleanup)
1332                 pdata->cleanup(&pdev->dev);
1333 err_free_irq:
1334         free_irq(host->irq, host);
1335 err_free_fclk:
1336         clk_put(host->fclk);
1337 err_free_iclk:
1338         if (host->iclk != NULL) {
1339                 clk_disable(host->iclk);
1340                 clk_put(host->iclk);
1341         }
1342 err_free_mmc_host:
1343         kfree(host);
1344 err_free_mem_region:
1345         release_mem_region(res->start, res->end - res->start + 1);
1346         return ret;
1347 }
1348
1349 static int mmc_omap_remove(struct platform_device *pdev)
1350 {
1351         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1352         int i;
1353
1354         platform_set_drvdata(pdev, NULL);
1355
1356         BUG_ON(host == NULL);
1357
1358         for (i = 0; i < host->nr_slots; i++)
1359                 mmc_omap_remove_slot(host->slots[i]);
1360
1361         if (host->pdata->cleanup)
1362                 host->pdata->cleanup(&pdev->dev);
1363
1364         if (host->iclk && !IS_ERR(host->iclk))
1365                 clk_put(host->iclk);
1366         if (host->fclk && !IS_ERR(host->fclk))
1367                 clk_put(host->fclk);
1368
1369         release_mem_region(pdev->resource[0].start,
1370                            pdev->resource[0].end - pdev->resource[0].start + 1);
1371
1372         kfree(host);
1373
1374         return 0;
1375 }
1376
1377 #ifdef CONFIG_PM
1378 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1379 {
1380         int i, ret = 0;
1381         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1382
1383         if (host == NULL || host->suspended)
1384                 return 0;
1385
1386         for (i = 0; i < host->nr_slots; i++) {
1387                 struct mmc_omap_slot *slot;
1388
1389                 slot = host->slots[i];
1390                 ret = mmc_suspend_host(slot->mmc, mesg);
1391                 if (ret < 0) {
1392                         while (--i >= 0) {
1393                                 slot = host->slots[i];
1394                                 mmc_resume_host(slot->mmc);
1395                         }
1396                         return ret;
1397                 }
1398         }
1399         host->suspended = 1;
1400         return 0;
1401 }
1402
1403 static int mmc_omap_resume(struct platform_device *pdev)
1404 {
1405         int i, ret = 0;
1406         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1407
1408         if (host == NULL || !host->suspended)
1409                 return 0;
1410
1411         for (i = 0; i < host->nr_slots; i++) {
1412                 struct mmc_omap_slot *slot;
1413                 slot = host->slots[i];
1414                 ret = mmc_resume_host(slot->mmc);
1415                 if (ret < 0)
1416                         return ret;
1417
1418                 host->suspended = 0;
1419         }
1420         return 0;
1421 }
1422 #else
1423 #define mmc_omap_suspend        NULL
1424 #define mmc_omap_resume         NULL
1425 #endif
1426
1427 static struct platform_driver mmc_omap_driver = {
1428         .probe          = mmc_omap_probe,
1429         .remove         = mmc_omap_remove,
1430         .suspend        = mmc_omap_suspend,
1431         .resume         = mmc_omap_resume,
1432         .driver         = {
1433                 .name   = DRIVER_NAME,
1434         },
1435 };
1436
1437 static int __init mmc_omap_init(void)
1438 {
1439         return platform_driver_register(&mmc_omap_driver);
1440 }
1441
1442 static void __exit mmc_omap_exit(void)
1443 {
1444         platform_driver_unregister(&mmc_omap_driver);
1445 }
1446
1447 module_init(mmc_omap_init);
1448 module_exit(mmc_omap_exit);
1449
1450 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1451 MODULE_LICENSE("GPL");
1452 MODULE_ALIAS(DRIVER_NAME);
1453 MODULE_AUTHOR("Juha Yrjölä");