2 * linux/drivers/mmc/host/omap.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/timer.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/clk.h>
28 #include <linux/scatterlist.h>
32 #include <asm/mach-types.h>
34 #include <asm/arch/board.h>
35 #include <asm/arch/mmc.h>
36 #include <asm/arch/gpio.h>
37 #include <asm/arch/dma.h>
38 #include <asm/arch/mux.h>
39 #include <asm/arch/fpga.h>
40 #include <asm/arch/tps65010.h>
41 #include <asm/arch/board-sx1.h>
43 #define OMAP_MMC_REG_CMD 0x00
44 #define OMAP_MMC_REG_ARGL 0x04
45 #define OMAP_MMC_REG_ARGH 0x08
46 #define OMAP_MMC_REG_CON 0x0c
47 #define OMAP_MMC_REG_STAT 0x10
48 #define OMAP_MMC_REG_IE 0x14
49 #define OMAP_MMC_REG_CTO 0x18
50 #define OMAP_MMC_REG_DTO 0x1c
51 #define OMAP_MMC_REG_DATA 0x20
52 #define OMAP_MMC_REG_BLEN 0x24
53 #define OMAP_MMC_REG_NBLK 0x28
54 #define OMAP_MMC_REG_BUF 0x2c
55 #define OMAP_MMC_REG_SDIO 0x34
56 #define OMAP_MMC_REG_REV 0x3c
57 #define OMAP_MMC_REG_RSP0 0x40
58 #define OMAP_MMC_REG_RSP1 0x44
59 #define OMAP_MMC_REG_RSP2 0x48
60 #define OMAP_MMC_REG_RSP3 0x4c
61 #define OMAP_MMC_REG_RSP4 0x50
62 #define OMAP_MMC_REG_RSP5 0x54
63 #define OMAP_MMC_REG_RSP6 0x58
64 #define OMAP_MMC_REG_RSP7 0x5c
65 #define OMAP_MMC_REG_IOSR 0x60
66 #define OMAP_MMC_REG_SYSC 0x64
67 #define OMAP_MMC_REG_SYSS 0x68
69 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
70 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
71 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
72 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
73 #define OMAP_MMC_STAT_A_FULL (1 << 10)
74 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
75 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
76 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
77 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
78 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
79 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
80 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
81 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
83 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
84 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
89 #define OMAP_MMC_CMDTYPE_BC 0
90 #define OMAP_MMC_CMDTYPE_BCR 1
91 #define OMAP_MMC_CMDTYPE_AC 2
92 #define OMAP_MMC_CMDTYPE_ADTC 3
95 #define DRIVER_NAME "mmci-omap"
97 /* Specifies how often in millisecs to poll for card status changes
98 * when the cover switch is open */
99 #define OMAP_MMC_SWITCH_POLL_DELAY 500
101 struct mmc_omap_host;
103 struct mmc_omap_slot {
108 unsigned int fclk_freq;
111 struct mmc_request *mrq;
112 struct mmc_omap_host *host;
113 struct mmc_host *mmc;
114 struct omap_mmc_slot_data *pdata;
117 struct mmc_omap_host {
120 struct mmc_request * mrq;
121 struct mmc_command * cmd;
122 struct mmc_data * data;
123 struct mmc_host * mmc;
125 unsigned char id; /* 16xx chips have 2 MMC blocks */
128 struct resource *mem_res;
129 void __iomem *virt_base;
130 unsigned int phys_base;
132 unsigned char bus_mode;
133 unsigned char hw_bus_mode;
138 u32 buffer_bytes_left;
139 u32 total_bytes_left;
142 unsigned brs_received:1, dma_done:1;
143 unsigned dma_is_read:1;
144 unsigned dma_in_use:1;
147 struct timer_list dma_timer;
152 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
153 struct mmc_omap_slot *current_slot;
154 spinlock_t slot_lock;
155 wait_queue_head_t slot_wq;
158 struct omap_mmc_platform_data *pdata;
161 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
163 struct mmc_omap_host *host = slot->host;
168 spin_lock_irqsave(&host->slot_lock, flags);
169 while (host->mmc != NULL) {
170 spin_unlock_irqrestore(&host->slot_lock, flags);
171 wait_event(host->slot_wq, host->mmc == NULL);
172 spin_lock_irqsave(&host->slot_lock, flags);
174 host->mmc = slot->mmc;
175 spin_unlock_irqrestore(&host->slot_lock, flags);
177 clk_enable(host->fclk);
178 if (host->current_slot != slot) {
179 if (host->pdata->switch_slot != NULL)
180 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
181 host->current_slot = slot;
184 /* Doing the dummy read here seems to work around some bug
185 * at least in OMAP24xx silicon where the command would not
186 * start after writing the CMD register. Sigh. */
187 OMAP_MMC_READ(host, CON);
189 OMAP_MMC_WRITE(host, CON, slot->saved_con);
192 static void mmc_omap_start_request(struct mmc_omap_host *host,
193 struct mmc_request *req);
195 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
197 struct mmc_omap_host *host = slot->host;
201 BUG_ON(slot == NULL || host->mmc == NULL);
202 clk_disable(host->fclk);
204 spin_lock_irqsave(&host->slot_lock, flags);
205 /* Check for any pending requests */
206 for (i = 0; i < host->nr_slots; i++) {
207 struct mmc_omap_slot *new_slot;
208 struct mmc_request *rq;
210 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
213 new_slot = host->slots[i];
214 /* The current slot should not have a request in queue */
215 BUG_ON(new_slot == host->current_slot);
217 host->mmc = new_slot->mmc;
218 spin_unlock_irqrestore(&host->slot_lock, flags);
219 mmc_omap_select_slot(new_slot, 1);
221 new_slot->mrq = NULL;
222 mmc_omap_start_request(host, rq);
227 wake_up(&host->slot_wq);
228 spin_unlock_irqrestore(&host->slot_lock, flags);
231 /* Access to the R/O switch is required for production testing
234 mmc_omap_show_ro(struct device *dev, struct device_attribute *attr, char *buf)
236 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
237 struct mmc_omap_slot *slot = mmc_priv(mmc);
239 return sprintf(buf, "%d\n", slot->pdata->get_ro(mmc_dev(mmc),
243 static DEVICE_ATTR(ro, S_IRUGO, mmc_omap_show_ro, NULL);
246 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
249 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
250 struct mmc_omap_slot *slot = mmc_priv(mmc);
252 return sprintf(buf, "%s\n", slot->pdata->name);
255 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
258 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
269 /* Our hardware needs to know exact type */
270 switch (mmc_resp_type(cmd)) {
275 /* resp 1, 1b, 6, 7 */
285 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
289 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
290 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
291 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
292 cmdtype = OMAP_MMC_CMDTYPE_BC;
293 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
294 cmdtype = OMAP_MMC_CMDTYPE_BCR;
296 cmdtype = OMAP_MMC_CMDTYPE_AC;
299 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
301 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
304 if (cmd->flags & MMC_RSP_BUSY)
307 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
310 OMAP_MMC_WRITE(host, CTO, 200);
311 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
312 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
313 OMAP_MMC_WRITE(host, IE,
314 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
315 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
316 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
317 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
318 OMAP_MMC_STAT_END_OF_DATA);
319 OMAP_MMC_WRITE(host, CMD, cmdreg);
323 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
325 if (host->dma_in_use) {
326 enum dma_data_direction dma_data_dir;
328 BUG_ON(host->dma_ch < 0);
330 omap_stop_dma(host->dma_ch);
331 /* Release DMA channel lazily */
332 mod_timer(&host->dma_timer, jiffies + HZ);
333 if (data->flags & MMC_DATA_WRITE)
334 dma_data_dir = DMA_TO_DEVICE;
336 dma_data_dir = DMA_FROM_DEVICE;
337 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
342 clk_disable(host->fclk);
344 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
345 * dozens of requests until the card finishes writing data.
346 * It'd be cheaper to just wait till an EOFB interrupt arrives...
351 mmc_request_done(host->mmc, data->mrq);
355 mmc_omap_start_command(host, data->stop);
359 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
364 if (!host->dma_in_use) {
365 mmc_omap_xfer_done(host, data);
369 spin_lock_irqsave(&host->dma_lock, flags);
373 host->brs_received = 1;
374 spin_unlock_irqrestore(&host->dma_lock, flags);
376 mmc_omap_xfer_done(host, data);
380 mmc_omap_dma_timer(unsigned long data)
382 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
384 BUG_ON(host->dma_ch < 0);
385 omap_free_dma(host->dma_ch);
390 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
396 spin_lock_irqsave(&host->dma_lock, flags);
397 if (host->brs_received)
401 spin_unlock_irqrestore(&host->dma_lock, flags);
403 mmc_omap_xfer_done(host, data);
407 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
411 if (cmd->flags & MMC_RSP_PRESENT) {
412 if (cmd->flags & MMC_RSP_136) {
413 /* response type 2 */
415 OMAP_MMC_READ(host, RSP0) |
416 (OMAP_MMC_READ(host, RSP1) << 16);
418 OMAP_MMC_READ(host, RSP2) |
419 (OMAP_MMC_READ(host, RSP3) << 16);
421 OMAP_MMC_READ(host, RSP4) |
422 (OMAP_MMC_READ(host, RSP5) << 16);
424 OMAP_MMC_READ(host, RSP6) |
425 (OMAP_MMC_READ(host, RSP7) << 16);
427 /* response types 1, 1b, 3, 4, 5, 6 */
429 OMAP_MMC_READ(host, RSP6) |
430 (OMAP_MMC_READ(host, RSP7) << 16);
434 if (host->data == NULL || cmd->error) {
436 clk_disable(host->fclk);
437 mmc_request_done(host->mmc, cmd->mrq);
443 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
445 struct scatterlist *sg;
447 sg = host->data->sg + host->sg_idx;
448 host->buffer_bytes_left = sg->length;
449 host->buffer = sg_virt(sg);
450 if (host->buffer_bytes_left > host->total_bytes_left)
451 host->buffer_bytes_left = host->total_bytes_left;
456 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
460 if (host->buffer_bytes_left == 0) {
462 BUG_ON(host->sg_idx == host->sg_len);
463 mmc_omap_sg_to_buf(host);
466 if (n > host->buffer_bytes_left)
467 n = host->buffer_bytes_left;
468 host->buffer_bytes_left -= n;
469 host->total_bytes_left -= n;
470 host->data->bytes_xfered += n;
473 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
475 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
479 static inline void mmc_omap_report_irq(u16 status)
481 static const char *mmc_omap_status_bits[] = {
482 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
483 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
487 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
488 if (status & (1 << i)) {
491 printk("%s", mmc_omap_status_bits[i]);
496 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
498 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
504 if (host->cmd == NULL && host->data == NULL) {
505 status = OMAP_MMC_READ(host, STAT);
506 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
508 OMAP_MMC_WRITE(host, STAT, status);
509 OMAP_MMC_WRITE(host, IE, 0);
518 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
519 OMAP_MMC_WRITE(host, STAT, status);
520 #ifdef CONFIG_MMC_DEBUG
521 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
522 status, host->cmd != NULL ? host->cmd->opcode : -1);
523 mmc_omap_report_irq(status);
526 if (host->total_bytes_left) {
527 if ((status & OMAP_MMC_STAT_A_FULL) ||
528 (status & OMAP_MMC_STAT_END_OF_DATA))
529 mmc_omap_xfer_data(host, 0);
530 if (status & OMAP_MMC_STAT_A_EMPTY)
531 mmc_omap_xfer_data(host, 1);
534 if (status & OMAP_MMC_STAT_END_OF_DATA) {
538 if (status & OMAP_MMC_STAT_DATA_TOUT) {
539 dev_dbg(mmc_dev(host->mmc), "data timeout\n");
541 host->data->error = -ETIMEDOUT;
546 if (status & OMAP_MMC_STAT_DATA_CRC) {
548 host->data->error = -EILSEQ;
549 dev_dbg(mmc_dev(host->mmc),
550 "data CRC error, bytes left %d\n",
551 host->total_bytes_left);
554 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
558 if (status & OMAP_MMC_STAT_CMD_TOUT) {
559 /* Timeouts are routine with some commands */
561 struct mmc_omap_slot *slot =
563 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
568 dev_err(mmc_dev(host->mmc),
569 "command timeout, CMD %d\n",
571 host->cmd->error = -ETIMEDOUT;
576 if (status & OMAP_MMC_STAT_CMD_CRC) {
578 dev_err(mmc_dev(host->mmc),
579 "command CRC error (CMD%d, arg 0x%08x)\n",
580 host->cmd->opcode, host->cmd->arg);
581 host->cmd->error = -EILSEQ;
584 dev_err(mmc_dev(host->mmc),
585 "command CRC error without cmd?\n");
588 if (status & OMAP_MMC_STAT_CARD_ERR) {
589 dev_dbg(mmc_dev(host->mmc),
590 "ignoring card status error (CMD%d)\n",
596 * NOTE: On 1610 the END_OF_CMD may come too early when
599 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
600 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
606 mmc_omap_cmd_done(host, host->cmd);
609 mmc_omap_xfer_done(host, host->data);
610 else if (end_transfer)
611 mmc_omap_end_of_data(host, host->data);
616 /* Prepare to transfer the next segment of a scatterlist */
618 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
620 int dma_ch = host->dma_ch;
621 unsigned long data_addr;
624 struct scatterlist *sg = &data->sg[host->sg_idx];
629 data_addr = host->phys_base + OMAP_MMC_REG_DATA;
631 count = sg_dma_len(sg);
633 if ((data->blocks == 1) && (count > data->blksz))
636 host->dma_len = count;
638 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
639 * Use 16 or 32 word frames when the blocksize is at least that large.
640 * Blocksize is usually 512 bytes; but not for some SD reads.
642 if (cpu_is_omap15xx() && frame > 32)
649 if (!(data->flags & MMC_DATA_WRITE)) {
650 buf = 0x800f | ((frame - 1) << 8);
652 if (cpu_class_is_omap1()) {
653 src_port = OMAP_DMA_PORT_TIPB;
654 dst_port = OMAP_DMA_PORT_EMIFF;
656 if (cpu_is_omap24xx())
657 sync_dev = OMAP24XX_DMA_MMC1_RX;
659 omap_set_dma_src_params(dma_ch, src_port,
660 OMAP_DMA_AMODE_CONSTANT,
662 omap_set_dma_dest_params(dma_ch, dst_port,
663 OMAP_DMA_AMODE_POST_INC,
664 sg_dma_address(sg), 0, 0);
665 omap_set_dma_dest_data_pack(dma_ch, 1);
666 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
668 buf = 0x0f80 | ((frame - 1) << 0);
670 if (cpu_class_is_omap1()) {
671 src_port = OMAP_DMA_PORT_EMIFF;
672 dst_port = OMAP_DMA_PORT_TIPB;
674 if (cpu_is_omap24xx())
675 sync_dev = OMAP24XX_DMA_MMC1_TX;
677 omap_set_dma_dest_params(dma_ch, dst_port,
678 OMAP_DMA_AMODE_CONSTANT,
680 omap_set_dma_src_params(dma_ch, src_port,
681 OMAP_DMA_AMODE_POST_INC,
682 sg_dma_address(sg), 0, 0);
683 omap_set_dma_src_data_pack(dma_ch, 1);
684 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
687 /* Max limit for DMA frame count is 0xffff */
688 BUG_ON(count > 0xffff);
690 OMAP_MMC_WRITE(host, BUF, buf);
691 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
692 frame, count, OMAP_DMA_SYNC_FRAME,
696 /* A scatterlist segment completed */
697 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
699 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
700 struct mmc_data *mmcdat = host->data;
702 if (unlikely(host->dma_ch < 0)) {
703 dev_err(mmc_dev(host->mmc),
704 "DMA callback while DMA not enabled\n");
707 /* FIXME: We really should do something to _handle_ the errors */
708 if (ch_status & OMAP1_DMA_TOUT_IRQ) {
709 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
712 if (ch_status & OMAP_DMA_DROP_IRQ) {
713 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
716 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
719 mmcdat->bytes_xfered += host->dma_len;
721 if (host->sg_idx < host->sg_len) {
722 mmc_omap_prepare_dma(host, host->data);
723 omap_start_dma(host->dma_ch);
725 mmc_omap_dma_done(host, host->data);
728 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
730 const char *dev_name;
731 int sync_dev, dma_ch, is_read, r;
733 is_read = !(data->flags & MMC_DATA_WRITE);
734 del_timer_sync(&host->dma_timer);
735 if (host->dma_ch >= 0) {
736 if (is_read == host->dma_is_read)
738 omap_free_dma(host->dma_ch);
744 sync_dev = OMAP_DMA_MMC_RX;
745 dev_name = "MMC1 read";
747 sync_dev = OMAP_DMA_MMC2_RX;
748 dev_name = "MMC2 read";
752 sync_dev = OMAP_DMA_MMC_TX;
753 dev_name = "MMC1 write";
755 sync_dev = OMAP_DMA_MMC2_TX;
756 dev_name = "MMC2 write";
759 r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
762 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
765 host->dma_ch = dma_ch;
766 host->dma_is_read = is_read;
771 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
775 reg = OMAP_MMC_READ(host, SDIO);
777 OMAP_MMC_WRITE(host, SDIO, reg);
778 /* Set maximum timeout */
779 OMAP_MMC_WRITE(host, CTO, 0xff);
782 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
787 /* Convert ns to clock cycles by assuming 20MHz frequency
788 * 1 cycle at 20MHz = 500 ns
790 timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
792 /* Check if we need to use timeout multiplier register */
793 reg = OMAP_MMC_READ(host, SDIO);
794 if (timeout > 0xffff) {
799 OMAP_MMC_WRITE(host, SDIO, reg);
800 OMAP_MMC_WRITE(host, DTO, timeout);
804 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
806 struct mmc_data *data = req->data;
807 int i, use_dma, block_size;
812 OMAP_MMC_WRITE(host, BLEN, 0);
813 OMAP_MMC_WRITE(host, NBLK, 0);
814 OMAP_MMC_WRITE(host, BUF, 0);
815 host->dma_in_use = 0;
816 set_cmd_timeout(host, req);
820 block_size = data->blksz;
822 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
823 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
824 set_data_timeout(host, req);
826 /* cope with calling layer confusion; it issues "single
827 * block" writes using multi-block scatterlists.
829 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
831 /* Only do DMA for entire blocks */
832 use_dma = host->use_dma;
834 for (i = 0; i < sg_len; i++) {
835 if ((data->sg[i].length % block_size) != 0) {
844 if (mmc_omap_get_dma_channel(host, data) == 0) {
845 enum dma_data_direction dma_data_dir;
847 if (data->flags & MMC_DATA_WRITE)
848 dma_data_dir = DMA_TO_DEVICE;
850 dma_data_dir = DMA_FROM_DEVICE;
852 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
853 sg_len, dma_data_dir);
854 host->total_bytes_left = 0;
855 mmc_omap_prepare_dma(host, req->data);
856 host->brs_received = 0;
858 host->dma_in_use = 1;
865 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
866 host->total_bytes_left = data->blocks * block_size;
867 host->sg_len = sg_len;
868 mmc_omap_sg_to_buf(host);
869 host->dma_in_use = 0;
873 static void mmc_omap_start_request(struct mmc_omap_host *host,
874 struct mmc_request *req)
876 BUG_ON(host->mrq != NULL);
880 /* only touch fifo AFTER the controller readies it */
881 mmc_omap_prepare_data(host, req);
882 mmc_omap_start_command(host, req->cmd);
883 if (host->dma_in_use)
884 omap_start_dma(host->dma_ch);
885 BUG_ON(irqs_disabled());
888 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
890 struct mmc_omap_slot *slot = mmc_priv(mmc);
891 struct mmc_omap_host *host = slot->host;
894 spin_lock_irqsave(&host->slot_lock, flags);
895 if (host->mmc != NULL) {
896 BUG_ON(slot->mrq != NULL);
898 spin_unlock_irqrestore(&host->slot_lock, flags);
902 spin_unlock_irqrestore(&host->slot_lock, flags);
903 mmc_omap_select_slot(slot, 1);
904 mmc_omap_start_request(host, req);
907 static void innovator_fpga_socket_power(int on)
909 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
911 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
912 OMAP1510_FPGA_POWER);
914 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
915 OMAP1510_FPGA_POWER);
921 * Turn the socket power on/off. Innovator uses FPGA, most boards
924 static void mmc_omap_power(struct mmc_omap_host *host, int on)
926 if (machine_is_sx1())
929 if (machine_is_omap_innovator())
930 innovator_fpga_socket_power(1);
931 else if (machine_is_omap_h2())
932 tps65010_set_gpio_out_value(GPIO3, HIGH);
933 else if (machine_is_omap_h3())
934 /* GPIO 4 of TPS65010 sends SD_EN signal */
935 tps65010_set_gpio_out_value(GPIO4, HIGH);
936 else if (cpu_is_omap24xx()) {
937 u16 reg = OMAP_MMC_READ(host, CON);
938 OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
940 if (host->power_pin >= 0)
941 omap_set_gpio_dataout(host->power_pin, 1);
943 if (machine_is_omap_innovator())
944 innovator_fpga_socket_power(0);
945 else if (machine_is_omap_h2())
946 tps65010_set_gpio_out_value(GPIO3, LOW);
947 else if (machine_is_omap_h3())
948 tps65010_set_gpio_out_value(GPIO4, LOW);
949 else if (cpu_is_omap24xx()) {
950 u16 reg = OMAP_MMC_READ(host, CON);
951 OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
953 if (host->power_pin >= 0)
954 omap_set_gpio_dataout(host->power_pin, 0);
958 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
960 struct mmc_omap_slot *slot = mmc_priv(mmc);
961 struct mmc_omap_host *host = slot->host;
962 int func_clk_rate = clk_get_rate(host->fclk);
968 dsor = func_clk_rate / ios->clock;
972 if (func_clk_rate / dsor > ios->clock)
978 slot->fclk_freq = func_clk_rate / dsor;
980 if (ios->bus_width == MMC_BUS_WIDTH_4)
986 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
988 struct mmc_omap_slot *slot = mmc_priv(mmc);
989 struct mmc_omap_host *host = slot->host;
992 dsor = mmc_omap_calc_divisor(mmc, ios);
993 host->bus_mode = ios->bus_mode;
994 host->hw_bus_mode = host->bus_mode;
996 switch (ios->power_mode) {
998 mmc_omap_power(host, 0);
1001 /* Cannot touch dsor yet, just power up MMC */
1002 mmc_omap_power(host, 1);
1009 clk_enable(host->fclk);
1011 /* On insanely high arm_per frequencies something sometimes
1012 * goes somehow out of sync, and the POW bit is not being set,
1013 * which results in the while loop below getting stuck.
1014 * Writing to the CON register twice seems to do the trick. */
1015 for (i = 0; i < 2; i++)
1016 OMAP_MMC_WRITE(host, CON, dsor);
1017 if (ios->power_mode == MMC_POWER_ON) {
1018 /* Send clock cycles, poll completion */
1019 OMAP_MMC_WRITE(host, IE, 0);
1020 OMAP_MMC_WRITE(host, STAT, 0xffff);
1021 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1022 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1023 OMAP_MMC_WRITE(host, STAT, 1);
1025 clk_disable(host->fclk);
1028 static int mmc_omap_get_ro(struct mmc_host *mmc)
1030 struct mmc_omap_slot *slot = mmc_priv(mmc);
1032 if (slot->pdata->get_ro != NULL)
1033 return slot->pdata->get_ro(mmc_dev(mmc), slot->id);
1037 static const struct mmc_host_ops mmc_omap_ops = {
1038 .request = mmc_omap_request,
1039 .set_ios = mmc_omap_set_ios,
1040 .get_ro = mmc_omap_get_ro,
1043 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1045 struct mmc_omap_slot *slot = NULL;
1046 struct mmc_host *mmc;
1049 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1053 slot = mmc_priv(mmc);
1057 slot->pdata = &host->pdata->slots[id];
1059 host->slots[id] = slot;
1061 mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
1062 MMC_CAP_SD_HIGHSPEED;
1063 if (host->pdata->conf.wire4)
1064 mmc->caps |= MMC_CAP_4_BIT_DATA;
1066 mmc->ops = &mmc_omap_ops;
1067 mmc->f_min = 400000;
1069 if (cpu_class_is_omap2())
1070 mmc->f_max = 48000000;
1072 mmc->f_max = 24000000;
1073 if (host->pdata->max_freq)
1074 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1075 mmc->ocr_avail = slot->pdata->ocr_mask;
1077 /* Use scatterlist DMA to reduce per-transfer costs.
1078 * NOTE max_seg_size assumption that small blocks aren't
1079 * normally used (except e.g. for reading SD registers).
1081 mmc->max_phys_segs = 32;
1082 mmc->max_hw_segs = 32;
1083 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1084 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1085 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1086 mmc->max_seg_size = mmc->max_req_size;
1088 r = mmc_add_host(mmc);
1092 if (slot->pdata->name != NULL) {
1093 r = device_create_file(&mmc->class_dev,
1094 &dev_attr_slot_name);
1096 goto err_remove_host;
1099 if (slot->pdata->get_ro != NULL) {
1100 r = device_create_file(&mmc->class_dev,
1106 err_remove_slot_name:
1107 if (slot->pdata->name != NULL)
1108 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1110 mmc_remove_host(mmc);
1114 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1116 struct mmc_host *mmc = slot->mmc;
1118 if (slot->pdata->name != NULL)
1119 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1120 if (slot->pdata->get_ro != NULL)
1121 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1123 mmc_remove_host(mmc);
1127 static int __init mmc_omap_probe(struct platform_device *pdev)
1129 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1130 struct mmc_omap_host *host = NULL;
1131 struct resource *res;
1135 if (pdata == NULL) {
1136 dev_err(&pdev->dev, "platform data missing\n");
1139 if (pdata->nr_slots == 0) {
1140 dev_err(&pdev->dev, "no slots\n");
1144 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1145 irq = platform_get_irq(pdev, 0);
1146 if (res == NULL || irq < 0)
1149 res = request_mem_region(res->start, res->end - res->start + 1,
1154 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1157 goto err_free_mem_region;
1160 spin_lock_init(&host->dma_lock);
1161 init_timer(&host->dma_timer);
1162 spin_lock_init(&host->slot_lock);
1163 init_waitqueue_head(&host->slot_wq);
1165 host->dma_timer.function = mmc_omap_dma_timer;
1166 host->dma_timer.data = (unsigned long) host;
1168 host->pdata = pdata;
1169 host->dev = &pdev->dev;
1170 platform_set_drvdata(pdev, host);
1172 host->id = pdev->id;
1173 host->mem_res = res;
1180 host->phys_base = host->mem_res->start;
1181 host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1183 if (cpu_is_omap24xx()) {
1184 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1185 if (IS_ERR(host->iclk))
1186 goto err_free_mmc_host;
1187 clk_enable(host->iclk);
1190 if (!cpu_is_omap24xx())
1191 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1193 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1195 if (IS_ERR(host->fclk)) {
1196 ret = PTR_ERR(host->fclk);
1200 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1204 if (pdata->init != NULL) {
1205 ret = pdata->init(&pdev->dev);
1210 host->nr_slots = pdata->nr_slots;
1211 for (i = 0; i < pdata->nr_slots; i++) {
1212 ret = mmc_omap_new_slot(host, i);
1215 mmc_omap_remove_slot(host->slots[i]);
1217 goto err_plat_cleanup;
1225 pdata->cleanup(&pdev->dev);
1227 free_irq(host->irq, host);
1229 clk_put(host->fclk);
1231 if (host->iclk != NULL) {
1232 clk_disable(host->iclk);
1233 clk_put(host->iclk);
1237 err_free_mem_region:
1238 release_mem_region(res->start, res->end - res->start + 1);
1242 static int mmc_omap_remove(struct platform_device *pdev)
1244 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1247 platform_set_drvdata(pdev, NULL);
1249 BUG_ON(host == NULL);
1251 for (i = 0; i < host->nr_slots; i++)
1252 mmc_omap_remove_slot(host->slots[i]);
1254 if (host->pdata->cleanup)
1255 host->pdata->cleanup(&pdev->dev);
1257 if (host->iclk && !IS_ERR(host->iclk))
1258 clk_put(host->iclk);
1259 if (host->fclk && !IS_ERR(host->fclk))
1260 clk_put(host->fclk);
1262 release_mem_region(pdev->resource[0].start,
1263 pdev->resource[0].end - pdev->resource[0].start + 1);
1271 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1274 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1276 if (host == NULL || host->suspended)
1279 for (i = 0; i < host->nr_slots; i++) {
1280 struct mmc_omap_slot *slot;
1282 slot = host->slots[i];
1283 ret = mmc_suspend_host(slot->mmc, mesg);
1286 slot = host->slots[i];
1287 mmc_resume_host(slot->mmc);
1292 host->suspended = 1;
1296 static int mmc_omap_resume(struct platform_device *pdev)
1299 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1301 if (host == NULL || !host->suspended)
1304 for (i = 0; i < host->nr_slots; i++) {
1305 struct mmc_omap_slot *slot;
1306 slot = host->slots[i];
1307 ret = mmc_resume_host(slot->mmc);
1311 host->suspended = 0;
1316 #define mmc_omap_suspend NULL
1317 #define mmc_omap_resume NULL
1320 static struct platform_driver mmc_omap_driver = {
1321 .probe = mmc_omap_probe,
1322 .remove = mmc_omap_remove,
1323 .suspend = mmc_omap_suspend,
1324 .resume = mmc_omap_resume,
1326 .name = DRIVER_NAME,
1330 static int __init mmc_omap_init(void)
1332 return platform_driver_register(&mmc_omap_driver);
1335 static void __exit mmc_omap_exit(void)
1337 platform_driver_unregister(&mmc_omap_driver);
1340 module_init(mmc_omap_init);
1341 module_exit(mmc_omap_exit);
1343 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1344 MODULE_LICENSE("GPL");
1345 MODULE_ALIAS(DRIVER_NAME);
1346 MODULE_AUTHOR("Juha Yrjölä");