drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/mmc.h>
  25 #include <linux/mmc/host.h>
  26 #include <linux/mmc/card.h>
  27 #include <linux/clk.h>
  28 #include <linux/scatterlist.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/mmc.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/dma.h>
  38 #include <asm/arch/mux.h>
  39 #include <asm/arch/fpga.h>
  40 #include <asm/arch/tps65010.h>
  41 #include <asm/arch/board-sx1.h>
  42
  43 #define OMAP_MMC_REG_CMD        0x00
  44 #define OMAP_MMC_REG_ARGL       0x04
  45 #define OMAP_MMC_REG_ARGH       0x08
  46 #define OMAP_MMC_REG_CON        0x0c
  47 #define OMAP_MMC_REG_STAT       0x10
  48 #define OMAP_MMC_REG_IE         0x14
  49 #define OMAP_MMC_REG_CTO        0x18
  50 #define OMAP_MMC_REG_DTO        0x1c
  51 #define OMAP_MMC_REG_DATA       0x20
  52 #define OMAP_MMC_REG_BLEN       0x24
  53 #define OMAP_MMC_REG_NBLK       0x28
  54 #define OMAP_MMC_REG_BUF        0x2c
  55 #define OMAP_MMC_REG_SDIO       0x34
  56 #define OMAP_MMC_REG_REV        0x3c
  57 #define OMAP_MMC_REG_RSP0       0x40
  58 #define OMAP_MMC_REG_RSP1       0x44
  59 #define OMAP_MMC_REG_RSP2       0x48
  60 #define OMAP_MMC_REG_RSP3       0x4c
  61 #define OMAP_MMC_REG_RSP4       0x50
  62 #define OMAP_MMC_REG_RSP5       0x54
  63 #define OMAP_MMC_REG_RSP6       0x58
  64 #define OMAP_MMC_REG_RSP7       0x5c
  65 #define OMAP_MMC_REG_IOSR       0x60
  66 #define OMAP_MMC_REG_SYSC       0x64
  67 #define OMAP_MMC_REG_SYSS       0x68
  68
  69 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  70 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  71 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  72 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  73 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  74 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  75 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  76 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  77 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  78 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  79 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  80 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  81 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  82
  83 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  84 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  85
  86 /*
  87  * Command types
  88  */
  89 #define OMAP_MMC_CMDTYPE_BC     0
  90 #define OMAP_MMC_CMDTYPE_BCR    1
  91 #define OMAP_MMC_CMDTYPE_AC     2
  92 #define OMAP_MMC_CMDTYPE_ADTC   3
  93
  94
  95 #define DRIVER_NAME "mmci-omap"
  96
  97 /* Specifies how often in millisecs to poll for card status changes
  98  * when the cover switch is open */
  99 #define OMAP_MMC_SWITCH_POLL_DELAY      500
 100
 101 struct mmc_omap_host;
 102
 103 struct mmc_omap_slot {
 104         int                     id;
 105         unsigned int            vdd;
 106         u16                     saved_con;
 107         u16                     bus_mode;
 108         unsigned int            fclk_freq;
 109         unsigned                powered:1;
 110
 111         struct mmc_request      *mrq;
 112         struct mmc_omap_host    *host;
 113         struct mmc_host         *mmc;
 114         struct omap_mmc_slot_data *pdata;
 115 };
 116
 117 struct mmc_omap_host {
 118         int                     initialized;
 119         int                     suspended;
 120         struct mmc_request *    mrq;
 121         struct mmc_command *    cmd;
 122         struct mmc_data *       data;
 123         struct mmc_host *       mmc;
 124         struct device *         dev;
 125         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 126         struct clk *            iclk;
 127         struct clk *            fclk;
 128         struct resource         *mem_res;
 129         void __iomem            *virt_base;
 130         unsigned int            phys_base;
 131         int                     irq;
 132         unsigned char           bus_mode;
 133         unsigned char           hw_bus_mode;
 134
 135         unsigned int            sg_len;
 136         int                     sg_idx;
 137         u16 *                   buffer;
 138         u32                     buffer_bytes_left;
 139         u32                     total_bytes_left;
 140
 141         unsigned                use_dma:1;
 142         unsigned                brs_received:1, dma_done:1;
 143         unsigned                dma_is_read:1;
 144         unsigned                dma_in_use:1;
 145         int                     dma_ch;
 146         spinlock_t              dma_lock;
 147         struct timer_list       dma_timer;
 148         unsigned                dma_len;
 149
 150         short                   power_pin;
 151
 152         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 153         struct mmc_omap_slot    *current_slot;
 154         spinlock_t              slot_lock;
 155         wait_queue_head_t       slot_wq;
 156         int                     nr_slots;
 157
 158         struct omap_mmc_platform_data *pdata;
 159 };
 160
 161 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 162 {
 163         struct mmc_omap_host *host = slot->host;
 164         unsigned long flags;
 165
 166         if (claimed)
 167                 goto no_claim;
 168         spin_lock_irqsave(&host->slot_lock, flags);
 169         while (host->mmc != NULL) {
 170                 spin_unlock_irqrestore(&host->slot_lock, flags);
 171                 wait_event(host->slot_wq, host->mmc == NULL);
 172                 spin_lock_irqsave(&host->slot_lock, flags);
 173         }
 174         host->mmc = slot->mmc;
 175         spin_unlock_irqrestore(&host->slot_lock, flags);
 176 no_claim:
 177         clk_enable(host->fclk);
 178         if (host->current_slot != slot) {
 179                 if (host->pdata->switch_slot != NULL)
 180                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 181                 host->current_slot = slot;
 182         }
 183
 184         /* Doing the dummy read here seems to work around some bug
 185          * at least in OMAP24xx silicon where the command would not
 186          * start after writing the CMD register. Sigh. */
 187         OMAP_MMC_READ(host, CON);
 188
 189         OMAP_MMC_WRITE(host, CON, slot->saved_con);
 190 }
 191
 192 static void mmc_omap_start_request(struct mmc_omap_host *host,
 193                                    struct mmc_request *req);
 194
 195 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
 196 {
 197         struct mmc_omap_host *host = slot->host;
 198         unsigned long flags;
 199         int i;
 200
 201         BUG_ON(slot == NULL || host->mmc == NULL);
 202         clk_disable(host->fclk);
 203
 204         spin_lock_irqsave(&host->slot_lock, flags);
 205         /* Check for any pending requests */
 206         for (i = 0; i < host->nr_slots; i++) {
 207                 struct mmc_omap_slot *new_slot;
 208                 struct mmc_request *rq;
 209
 210                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 211                         continue;
 212
 213                 new_slot = host->slots[i];
 214                 /* The current slot should not have a request in queue */
 215                 BUG_ON(new_slot == host->current_slot);
 216
 217                 host->mmc = new_slot->mmc;
 218                 spin_unlock_irqrestore(&host->slot_lock, flags);
 219                 mmc_omap_select_slot(new_slot, 1);
 220                 rq = new_slot->mrq;
 221                 new_slot->mrq = NULL;
 222                 mmc_omap_start_request(host, rq);
 223                 return;
 224         }
 225
 226         host->mmc = NULL;
 227         wake_up(&host->slot_wq);
 228         spin_unlock_irqrestore(&host->slot_lock, flags);
 229 }
 230
 231 /* Access to the R/O switch is required for production testing
 232  * purposes. */
 233 static ssize_t
 234 mmc_omap_show_ro(struct device *dev, struct device_attribute *attr, char *buf)
 235 {
 236         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 237         struct mmc_omap_slot *slot = mmc_priv(mmc);
 238
 239         return sprintf(buf, "%d\n", slot->pdata->get_ro(mmc_dev(mmc),
 240                                                         slot->id));
 241 }
 242
 243 static DEVICE_ATTR(ro, S_IRUGO, mmc_omap_show_ro, NULL);
 244
 245 static ssize_t
 246 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 247                         char *buf)
 248 {
 249         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 250         struct mmc_omap_slot *slot = mmc_priv(mmc);
 251
 252         return sprintf(buf, "%s\n", slot->pdata->name);
 253 }
 254
 255 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 256
 257 static void
 258 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 259 {
 260         u32 cmdreg;
 261         u32 resptype;
 262         u32 cmdtype;
 263
 264         host->cmd = cmd;
 265
 266         resptype = 0;
 267         cmdtype = 0;
 268
 269         /* Our hardware needs to know exact type */
 270         switch (mmc_resp_type(cmd)) {
 271         case MMC_RSP_NONE:
 272                 break;
 273         case MMC_RSP_R1:
 274         case MMC_RSP_R1B:
 275                 /* resp 1, 1b, 6, 7 */
 276                 resptype = 1;
 277                 break;
 278         case MMC_RSP_R2:
 279                 resptype = 2;
 280                 break;
 281         case MMC_RSP_R3:
 282                 resptype = 3;
 283                 break;
 284         default:
 285                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 286                 break;
 287         }
 288
 289         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 290                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 291         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 292                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 293         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 294                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 295         } else {
 296                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 297         }
 298
 299         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 300
 301         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 302                 cmdreg |= 1 << 6;
 303
 304         if (cmd->flags & MMC_RSP_BUSY)
 305                 cmdreg |= 1 << 11;
 306
 307         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 308                 cmdreg |= 1 << 15;
 309
 310         OMAP_MMC_WRITE(host, CTO, 200);
 311         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 312         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 313         OMAP_MMC_WRITE(host, IE,
 314                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 315                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 316                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 317                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 318                        OMAP_MMC_STAT_END_OF_DATA);
 319         OMAP_MMC_WRITE(host, CMD, cmdreg);
 320 }
 321
 322 static void
 323 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 324 {
 325         if (host->dma_in_use) {
 326                 enum dma_data_direction dma_data_dir;
 327
 328                 BUG_ON(host->dma_ch < 0);
 329                 if (data->error)
 330                         omap_stop_dma(host->dma_ch);
 331                 /* Release DMA channel lazily */
 332                 mod_timer(&host->dma_timer, jiffies + HZ);
 333                 if (data->flags & MMC_DATA_WRITE)
 334                         dma_data_dir = DMA_TO_DEVICE;
 335                 else
 336                         dma_data_dir = DMA_FROM_DEVICE;
 337                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 338                              dma_data_dir);
 339         }
 340         host->data = NULL;
 341         host->sg_len = 0;
 342         clk_disable(host->fclk);
 343
 344         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 345          * dozens of requests until the card finishes writing data.
 346          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 347          */
 348
 349         if (!data->stop) {
 350                 host->mrq = NULL;
 351                 mmc_request_done(host->mmc, data->mrq);
 352                 return;
 353         }
 354
 355         mmc_omap_start_command(host, data->stop);
 356 }
 357
 358 static void
 359 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 360 {
 361         unsigned long flags;
 362         int done;
 363
 364         if (!host->dma_in_use) {
 365                 mmc_omap_xfer_done(host, data);
 366                 return;
 367         }
 368         done = 0;
 369         spin_lock_irqsave(&host->dma_lock, flags);
 370         if (host->dma_done)
 371                 done = 1;
 372         else
 373                 host->brs_received = 1;
 374         spin_unlock_irqrestore(&host->dma_lock, flags);
 375         if (done)
 376                 mmc_omap_xfer_done(host, data);
 377 }
 378
 379 static void
 380 mmc_omap_dma_timer(unsigned long data)
 381 {
 382         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 383
 384         BUG_ON(host->dma_ch < 0);
 385         omap_free_dma(host->dma_ch);
 386         host->dma_ch = -1;
 387 }
 388
 389 static void
 390 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 391 {
 392         unsigned long flags;
 393         int done;
 394
 395         done = 0;
 396         spin_lock_irqsave(&host->dma_lock, flags);
 397         if (host->brs_received)
 398                 done = 1;
 399         else
 400                 host->dma_done = 1;
 401         spin_unlock_irqrestore(&host->dma_lock, flags);
 402         if (done)
 403                 mmc_omap_xfer_done(host, data);
 404 }
 405
 406 static void
 407 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 408 {
 409         host->cmd = NULL;
 410
 411         if (cmd->flags & MMC_RSP_PRESENT) {
 412                 if (cmd->flags & MMC_RSP_136) {
 413                         /* response type 2 */
 414                         cmd->resp[3] =
 415                                 OMAP_MMC_READ(host, RSP0) |
 416                                 (OMAP_MMC_READ(host, RSP1) << 16);
 417                         cmd->resp[2] =
 418                                 OMAP_MMC_READ(host, RSP2) |
 419                                 (OMAP_MMC_READ(host, RSP3) << 16);
 420                         cmd->resp[1] =
 421                                 OMAP_MMC_READ(host, RSP4) |
 422                                 (OMAP_MMC_READ(host, RSP5) << 16);
 423                         cmd->resp[0] =
 424                                 OMAP_MMC_READ(host, RSP6) |
 425                                 (OMAP_MMC_READ(host, RSP7) << 16);
 426                 } else {
 427                         /* response types 1, 1b, 3, 4, 5, 6 */
 428                         cmd->resp[0] =
 429                                 OMAP_MMC_READ(host, RSP6) |
 430                                 (OMAP_MMC_READ(host, RSP7) << 16);
 431                 }
 432         }
 433
 434         if (host->data == NULL || cmd->error) {
 435                 host->mrq = NULL;
 436                 clk_disable(host->fclk);
 437                 mmc_request_done(host->mmc, cmd->mrq);
 438         }
 439 }
 440
 441 /* PIO only */
 442 static void
 443 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 444 {
 445         struct scatterlist *sg;
 446
 447         sg = host->data->sg + host->sg_idx;
 448         host->buffer_bytes_left = sg->length;
 449         host->buffer = sg_virt(sg);
 450         if (host->buffer_bytes_left > host->total_bytes_left)
 451                 host->buffer_bytes_left = host->total_bytes_left;
 452 }
 453
 454 /* PIO only */
 455 static void
 456 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 457 {
 458         int n;
 459
 460         if (host->buffer_bytes_left == 0) {
 461                 host->sg_idx++;
 462                 BUG_ON(host->sg_idx == host->sg_len);
 463                 mmc_omap_sg_to_buf(host);
 464         }
 465         n = 64;
 466         if (n > host->buffer_bytes_left)
 467                 n = host->buffer_bytes_left;
 468         host->buffer_bytes_left -= n;
 469         host->total_bytes_left -= n;
 470         host->data->bytes_xfered += n;
 471
 472         if (write) {
 473                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 474         } else {
 475                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 476         }
 477 }
 478
 479 static inline void mmc_omap_report_irq(u16 status)
 480 {
 481         static const char *mmc_omap_status_bits[] = {
 482                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 483                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 484         };
 485         int i, c = 0;
 486
 487         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 488                 if (status & (1 << i)) {
 489                         if (c)
 490                                 printk(" ");
 491                         printk("%s", mmc_omap_status_bits[i]);
 492                         c++;
 493                 }
 494 }
 495
 496 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 497 {
 498         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 499         u16 status;
 500         int end_command;
 501         int end_transfer;
 502         int transfer_error;
 503
 504         if (host->cmd == NULL && host->data == NULL) {
 505                 status = OMAP_MMC_READ(host, STAT);
 506                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 507                 if (status != 0) {
 508                         OMAP_MMC_WRITE(host, STAT, status);
 509                         OMAP_MMC_WRITE(host, IE, 0);
 510                 }
 511                 return IRQ_HANDLED;
 512         }
 513
 514         end_command = 0;
 515         end_transfer = 0;
 516         transfer_error = 0;
 517
 518         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 519                 OMAP_MMC_WRITE(host, STAT, status);
 520 #ifdef CONFIG_MMC_DEBUG
 521                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 522                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 523                 mmc_omap_report_irq(status);
 524                 printk("\n");
 525 #endif
 526                 if (host->total_bytes_left) {
 527                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 528                             (status & OMAP_MMC_STAT_END_OF_DATA))
 529                                 mmc_omap_xfer_data(host, 0);
 530                         if (status & OMAP_MMC_STAT_A_EMPTY)
 531                                 mmc_omap_xfer_data(host, 1);
 532                 }
 533
 534                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 535                         end_transfer = 1;
 536                 }
 537
 538                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 539                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 540                         if (host->data) {
 541                                 host->data->error = -ETIMEDOUT;
 542                                 transfer_error = 1;
 543                         }
 544                 }
 545
 546                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 547                         if (host->data) {
 548                                 host->data->error = -EILSEQ;
 549                                 dev_dbg(mmc_dev(host->mmc),
 550                                          "data CRC error, bytes left %d\n",
 551                                         host->total_bytes_left);
 552                                 transfer_error = 1;
 553                         } else {
 554                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 555                         }
 556                 }
 557
 558                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 559                         /* Timeouts are routine with some commands */
 560                         if (host->cmd) {
 561                                 struct mmc_omap_slot *slot =
 562                                         host->current_slot;
 563                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 564                                                 host->cmd->opcode !=
 565                                                 MMC_SEND_OP_COND &&
 566                                                 host->cmd->opcode !=
 567                                                 MMC_APP_CMD)
 568                                         dev_err(mmc_dev(host->mmc),
 569                                                 "command timeout, CMD %d\n",
 570                                                 host->cmd->opcode);
 571                                 host->cmd->error = -ETIMEDOUT;
 572                                 end_command = 1;
 573                         }
 574                 }
 575
 576                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 577                         if (host->cmd) {
 578                                 dev_err(mmc_dev(host->mmc),
 579                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 580                                         host->cmd->opcode, host->cmd->arg);
 581                                 host->cmd->error = -EILSEQ;
 582                                 end_command = 1;
 583                         } else
 584                                 dev_err(mmc_dev(host->mmc),
 585                                         "command CRC error without cmd?\n");
 586                 }
 587
 588                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 589                         dev_dbg(mmc_dev(host->mmc),
 590                                 "ignoring card status error (CMD%d)\n",
 591                                 host->cmd->opcode);
 592                         end_command = 1;
 593                 }
 594
 595                 /*
 596                  * NOTE: On 1610 the END_OF_CMD may come too early when
 597                  * starting a write
 598                  */
 599                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 600                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 601                         end_command = 1;
 602                 }
 603         }
 604
 605         if (end_command) {
 606                 mmc_omap_cmd_done(host, host->cmd);
 607         }
 608         if (transfer_error)
 609                 mmc_omap_xfer_done(host, host->data);
 610         else if (end_transfer)
 611                 mmc_omap_end_of_data(host, host->data);
 612
 613         return IRQ_HANDLED;
 614 }
 615
 616 /* Prepare to transfer the next segment of a scatterlist */
 617 static void
 618 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 619 {
 620         int dma_ch = host->dma_ch;
 621         unsigned long data_addr;
 622         u16 buf, frame;
 623         u32 count;
 624         struct scatterlist *sg = &data->sg[host->sg_idx];
 625         int src_port = 0;
 626         int dst_port = 0;
 627         int sync_dev = 0;
 628
 629         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 630         frame = data->blksz;
 631         count = sg_dma_len(sg);
 632
 633         if ((data->blocks == 1) && (count > data->blksz))
 634                 count = frame;
 635
 636         host->dma_len = count;
 637
 638         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 639          * Use 16 or 32 word frames when the blocksize is at least that large.
 640          * Blocksize is usually 512 bytes; but not for some SD reads.
 641          */
 642         if (cpu_is_omap15xx() && frame > 32)
 643                 frame = 32;
 644         else if (frame > 64)
 645                 frame = 64;
 646         count /= frame;
 647         frame >>= 1;
 648
 649         if (!(data->flags & MMC_DATA_WRITE)) {
 650                 buf = 0x800f | ((frame - 1) << 8);
 651
 652                 if (cpu_class_is_omap1()) {
 653                         src_port = OMAP_DMA_PORT_TIPB;
 654                         dst_port = OMAP_DMA_PORT_EMIFF;
 655                 }
 656                 if (cpu_is_omap24xx())
 657                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 658
 659                 omap_set_dma_src_params(dma_ch, src_port,
 660                                         OMAP_DMA_AMODE_CONSTANT,
 661                                         data_addr, 0, 0);
 662                 omap_set_dma_dest_params(dma_ch, dst_port,
 663                                          OMAP_DMA_AMODE_POST_INC,
 664                                          sg_dma_address(sg), 0, 0);
 665                 omap_set_dma_dest_data_pack(dma_ch, 1);
 666                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 667         } else {
 668                 buf = 0x0f80 | ((frame - 1) << 0);
 669
 670                 if (cpu_class_is_omap1()) {
 671                         src_port = OMAP_DMA_PORT_EMIFF;
 672                         dst_port = OMAP_DMA_PORT_TIPB;
 673                 }
 674                 if (cpu_is_omap24xx())
 675                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 676
 677                 omap_set_dma_dest_params(dma_ch, dst_port,
 678                                          OMAP_DMA_AMODE_CONSTANT,
 679                                          data_addr, 0, 0);
 680                 omap_set_dma_src_params(dma_ch, src_port,
 681                                         OMAP_DMA_AMODE_POST_INC,
 682                                         sg_dma_address(sg), 0, 0);
 683                 omap_set_dma_src_data_pack(dma_ch, 1);
 684                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 685         }
 686
 687         /* Max limit for DMA frame count is 0xffff */
 688         BUG_ON(count > 0xffff);
 689
 690         OMAP_MMC_WRITE(host, BUF, buf);
 691         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 692                                      frame, count, OMAP_DMA_SYNC_FRAME,
 693                                      sync_dev, 0);
 694 }
 695
 696 /* A scatterlist segment completed */
 697 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 698 {
 699         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 700         struct mmc_data *mmcdat = host->data;
 701
 702         if (unlikely(host->dma_ch < 0)) {
 703                 dev_err(mmc_dev(host->mmc),
 704                         "DMA callback while DMA not enabled\n");
 705                 return;
 706         }
 707         /* FIXME: We really should do something to _handle_ the errors */
 708         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 709                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 710                 return;
 711         }
 712         if (ch_status & OMAP_DMA_DROP_IRQ) {
 713                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 714                 return;
 715         }
 716         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 717                 return;
 718         }
 719         mmcdat->bytes_xfered += host->dma_len;
 720         host->sg_idx++;
 721         if (host->sg_idx < host->sg_len) {
 722                 mmc_omap_prepare_dma(host, host->data);
 723                 omap_start_dma(host->dma_ch);
 724         } else
 725                 mmc_omap_dma_done(host, host->data);
 726 }
 727
 728 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 729 {
 730         const char *dev_name;
 731         int sync_dev, dma_ch, is_read, r;
 732
 733         is_read = !(data->flags & MMC_DATA_WRITE);
 734         del_timer_sync(&host->dma_timer);
 735         if (host->dma_ch >= 0) {
 736                 if (is_read == host->dma_is_read)
 737                         return 0;
 738                 omap_free_dma(host->dma_ch);
 739                 host->dma_ch = -1;
 740         }
 741
 742         if (is_read) {
 743                 if (host->id == 1) {
 744                         sync_dev = OMAP_DMA_MMC_RX;
 745                         dev_name = "MMC1 read";
 746                 } else {
 747                         sync_dev = OMAP_DMA_MMC2_RX;
 748                         dev_name = "MMC2 read";
 749                 }
 750         } else {
 751                 if (host->id == 1) {
 752                         sync_dev = OMAP_DMA_MMC_TX;
 753                         dev_name = "MMC1 write";
 754                 } else {
 755                         sync_dev = OMAP_DMA_MMC2_TX;
 756                         dev_name = "MMC2 write";
 757                 }
 758         }
 759         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 760                              host, &dma_ch);
 761         if (r != 0) {
 762                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 763                 return r;
 764         }
 765         host->dma_ch = dma_ch;
 766         host->dma_is_read = is_read;
 767
 768         return 0;
 769 }
 770
 771 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 772 {
 773         u16 reg;
 774
 775         reg = OMAP_MMC_READ(host, SDIO);
 776         reg &= ~(1 << 5);
 777         OMAP_MMC_WRITE(host, SDIO, reg);
 778         /* Set maximum timeout */
 779         OMAP_MMC_WRITE(host, CTO, 0xff);
 780 }
 781
 782 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 783 {
 784         int timeout;
 785         u16 reg;
 786
 787         /* Convert ns to clock cycles by assuming 20MHz frequency
 788          * 1 cycle at 20MHz = 500 ns
 789          */
 790         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 791
 792         /* Check if we need to use timeout multiplier register */
 793         reg = OMAP_MMC_READ(host, SDIO);
 794         if (timeout > 0xffff) {
 795                 reg |= (1 << 5);
 796                 timeout /= 1024;
 797         } else
 798                 reg &= ~(1 << 5);
 799         OMAP_MMC_WRITE(host, SDIO, reg);
 800         OMAP_MMC_WRITE(host, DTO, timeout);
 801 }
 802
 803 static void
 804 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 805 {
 806         struct mmc_data *data = req->data;
 807         int i, use_dma, block_size;
 808         unsigned sg_len;
 809
 810         host->data = data;
 811         if (data == NULL) {
 812                 OMAP_MMC_WRITE(host, BLEN, 0);
 813                 OMAP_MMC_WRITE(host, NBLK, 0);
 814                 OMAP_MMC_WRITE(host, BUF, 0);
 815                 host->dma_in_use = 0;
 816                 set_cmd_timeout(host, req);
 817                 return;
 818         }
 819
 820         block_size = data->blksz;
 821
 822         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 823         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 824         set_data_timeout(host, req);
 825
 826         /* cope with calling layer confusion; it issues "single
 827          * block" writes using multi-block scatterlists.
 828          */
 829         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 830
 831         /* Only do DMA for entire blocks */
 832         use_dma = host->use_dma;
 833         if (use_dma) {
 834                 for (i = 0; i < sg_len; i++) {
 835                         if ((data->sg[i].length % block_size) != 0) {
 836                                 use_dma = 0;
 837                                 break;
 838                         }
 839                 }
 840         }
 841
 842         host->sg_idx = 0;
 843         if (use_dma) {
 844                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 845                         enum dma_data_direction dma_data_dir;
 846
 847                         if (data->flags & MMC_DATA_WRITE)
 848                                 dma_data_dir = DMA_TO_DEVICE;
 849                         else
 850                                 dma_data_dir = DMA_FROM_DEVICE;
 851
 852                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 853                                                 sg_len, dma_data_dir);
 854                         host->total_bytes_left = 0;
 855                         mmc_omap_prepare_dma(host, req->data);
 856                         host->brs_received = 0;
 857                         host->dma_done = 0;
 858                         host->dma_in_use = 1;
 859                 } else
 860                         use_dma = 0;
 861         }
 862
 863         /* Revert to PIO? */
 864         if (!use_dma) {
 865                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 866                 host->total_bytes_left = data->blocks * block_size;
 867                 host->sg_len = sg_len;
 868                 mmc_omap_sg_to_buf(host);
 869                 host->dma_in_use = 0;
 870         }
 871 }
 872
 873 static void mmc_omap_start_request(struct mmc_omap_host *host,
 874                                    struct mmc_request *req)
 875 {
 876         BUG_ON(host->mrq != NULL);
 877
 878         host->mrq = req;
 879
 880         /* only touch fifo AFTER the controller readies it */
 881         mmc_omap_prepare_data(host, req);
 882         mmc_omap_start_command(host, req->cmd);
 883         if (host->dma_in_use)
 884                 omap_start_dma(host->dma_ch);
 885         BUG_ON(irqs_disabled());
 886 }
 887
 888 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 889 {
 890         struct mmc_omap_slot *slot = mmc_priv(mmc);
 891         struct mmc_omap_host *host = slot->host;
 892         unsigned long flags;
 893
 894         spin_lock_irqsave(&host->slot_lock, flags);
 895         if (host->mmc != NULL) {
 896                 BUG_ON(slot->mrq != NULL);
 897                 slot->mrq = req;
 898                 spin_unlock_irqrestore(&host->slot_lock, flags);
 899                 return;
 900         } else
 901                 host->mmc = mmc;
 902         spin_unlock_irqrestore(&host->slot_lock, flags);
 903         mmc_omap_select_slot(slot, 1);
 904         mmc_omap_start_request(host, req);
 905 }
 906
 907 static void innovator_fpga_socket_power(int on)
 908 {
 909 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 910         if (on) {
 911                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 912                      OMAP1510_FPGA_POWER);
 913         } else {
 914                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 915                      OMAP1510_FPGA_POWER);
 916         }
 917 #endif
 918 }
 919
 920 /*
 921  * Turn the socket power on/off. Innovator uses FPGA, most boards
 922  * probably use GPIO.
 923  */
 924 static void mmc_omap_power(struct mmc_omap_host *host, int on)
 925 {
 926         if (machine_is_sx1())
 927                 sx1_setmmcpower(on);
 928         else if (on) {
 929                 if (machine_is_omap_innovator())
 930                         innovator_fpga_socket_power(1);
 931                 else if (machine_is_omap_h2())
 932                         tps65010_set_gpio_out_value(GPIO3, HIGH);
 933                 else if (machine_is_omap_h3())
 934                         /* GPIO 4 of TPS65010 sends SD_EN signal */
 935                         tps65010_set_gpio_out_value(GPIO4, HIGH);
 936                 else if (cpu_is_omap24xx()) {
 937                         u16 reg = OMAP_MMC_READ(host, CON);
 938                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
 939                 } else
 940                         if (host->power_pin >= 0)
 941                                 omap_set_gpio_dataout(host->power_pin, 1);
 942         } else {
 943                 if (machine_is_omap_innovator())
 944                         innovator_fpga_socket_power(0);
 945                 else if (machine_is_omap_h2())
 946                         tps65010_set_gpio_out_value(GPIO3, LOW);
 947                 else if (machine_is_omap_h3())
 948                         tps65010_set_gpio_out_value(GPIO4, LOW);
 949                 else if (cpu_is_omap24xx()) {
 950                         u16 reg = OMAP_MMC_READ(host, CON);
 951                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
 952                 } else
 953                         if (host->power_pin >= 0)
 954                                 omap_set_gpio_dataout(host->power_pin, 0);
 955         }
 956 }
 957
 958 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
 959 {
 960         struct mmc_omap_slot *slot = mmc_priv(mmc);
 961         struct mmc_omap_host *host = slot->host;
 962         int func_clk_rate = clk_get_rate(host->fclk);
 963         int dsor;
 964
 965         if (ios->clock == 0)
 966                 return 0;
 967
 968         dsor = func_clk_rate / ios->clock;
 969         if (dsor < 1)
 970                 dsor = 1;
 971
 972         if (func_clk_rate / dsor > ios->clock)
 973                 dsor++;
 974
 975         if (dsor > 250)
 976                 dsor = 250;
 977
 978         slot->fclk_freq = func_clk_rate / dsor;
 979
 980         if (ios->bus_width == MMC_BUS_WIDTH_4)
 981                 dsor |= 1 << 15;
 982
 983         return dsor;
 984 }
 985
 986 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 987 {
 988         struct mmc_omap_slot *slot = mmc_priv(mmc);
 989         struct mmc_omap_host *host = slot->host;
 990         int i, dsor;
 991
 992         dsor = mmc_omap_calc_divisor(mmc, ios);
 993         host->bus_mode = ios->bus_mode;
 994         host->hw_bus_mode = host->bus_mode;
 995
 996         switch (ios->power_mode) {
 997         case MMC_POWER_OFF:
 998                 mmc_omap_power(host, 0);
 999                 break;
1000         case MMC_POWER_UP:
1001                 /* Cannot touch dsor yet, just power up MMC */
1002                 mmc_omap_power(host, 1);
1003                 return;
1004         case MMC_POWER_ON:
1005                 dsor |= 1 << 11;
1006                 break;
1007         }
1008
1009         clk_enable(host->fclk);
1010
1011         /* On insanely high arm_per frequencies something sometimes
1012          * goes somehow out of sync, and the POW bit is not being set,
1013          * which results in the while loop below getting stuck.
1014          * Writing to the CON register twice seems to do the trick. */
1015         for (i = 0; i < 2; i++)
1016                 OMAP_MMC_WRITE(host, CON, dsor);
1017         if (ios->power_mode == MMC_POWER_ON) {
1018                 /* Send clock cycles, poll completion */
1019                 OMAP_MMC_WRITE(host, IE, 0);
1020                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1021                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1022                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1023                 OMAP_MMC_WRITE(host, STAT, 1);
1024         }
1025         clk_disable(host->fclk);
1026 }
1027
1028 static int mmc_omap_get_ro(struct mmc_host *mmc)
1029 {
1030         struct mmc_omap_slot *slot = mmc_priv(mmc);
1031
1032         if (slot->pdata->get_ro != NULL)
1033                 return slot->pdata->get_ro(mmc_dev(mmc), slot->id);
1034         return 0;
1035 }
1036
1037 static const struct mmc_host_ops mmc_omap_ops = {
1038         .request        = mmc_omap_request,
1039         .set_ios        = mmc_omap_set_ios,
1040         .get_ro         = mmc_omap_get_ro,
1041 };
1042
1043 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1044 {
1045         struct mmc_omap_slot *slot = NULL;
1046         struct mmc_host *mmc;
1047         int r;
1048
1049         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1050         if (mmc == NULL)
1051                 return -ENOMEM;
1052
1053         slot = mmc_priv(mmc);
1054         slot->host = host;
1055         slot->mmc = mmc;
1056         slot->id = id;
1057         slot->pdata = &host->pdata->slots[id];
1058
1059         host->slots[id] = slot;
1060
1061         mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
1062                     MMC_CAP_SD_HIGHSPEED;
1063         if (host->pdata->conf.wire4)
1064                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1065
1066         mmc->ops = &mmc_omap_ops;
1067         mmc->f_min = 400000;
1068
1069         if (cpu_class_is_omap2())
1070                 mmc->f_max = 48000000;
1071         else
1072                 mmc->f_max = 24000000;
1073         if (host->pdata->max_freq)
1074                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1075         mmc->ocr_avail = slot->pdata->ocr_mask;
1076
1077         /* Use scatterlist DMA to reduce per-transfer costs.
1078          * NOTE max_seg_size assumption that small blocks aren't
1079          * normally used (except e.g. for reading SD registers).
1080          */
1081         mmc->max_phys_segs = 32;
1082         mmc->max_hw_segs = 32;
1083         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1084         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1085         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1086         mmc->max_seg_size = mmc->max_req_size;
1087
1088         r = mmc_add_host(mmc);
1089         if (r < 0)
1090                 return r;
1091
1092         if (slot->pdata->name != NULL) {
1093                 r = device_create_file(&mmc->class_dev,
1094                                         &dev_attr_slot_name);
1095                 if (r < 0)
1096                         goto err_remove_host;
1097         }
1098
1099         if (slot->pdata->get_ro != NULL) {
1100                 r = device_create_file(&mmc->class_dev,
1101                                         &dev_attr_ro);
1102         }
1103
1104         return 0;
1105
1106 err_remove_slot_name:
1107         if (slot->pdata->name != NULL)
1108                 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1109 err_remove_host:
1110         mmc_remove_host(mmc);
1111         return r;
1112 }
1113
1114 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1115 {
1116         struct mmc_host *mmc = slot->mmc;
1117
1118         if (slot->pdata->name != NULL)
1119                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1120         if (slot->pdata->get_ro != NULL)
1121                 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1122
1123         mmc_remove_host(mmc);
1124         mmc_free_host(mmc);
1125 }
1126
1127 static int __init mmc_omap_probe(struct platform_device *pdev)
1128 {
1129         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1130         struct mmc_omap_host *host = NULL;
1131         struct resource *res;
1132         int i, ret = 0;
1133         int irq;
1134
1135         if (pdata == NULL) {
1136                 dev_err(&pdev->dev, "platform data missing\n");
1137                 return -ENXIO;
1138         }
1139         if (pdata->nr_slots == 0) {
1140                 dev_err(&pdev->dev, "no slots\n");
1141                 return -ENXIO;
1142         }
1143
1144         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1145         irq = platform_get_irq(pdev, 0);
1146         if (res == NULL || irq < 0)
1147                 return -ENXIO;
1148
1149         res = request_mem_region(res->start, res->end - res->start + 1,
1150                                  pdev->name);
1151         if (res == NULL)
1152                 return -EBUSY;
1153
1154         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1155         if (host == NULL) {
1156                 ret = -ENOMEM;
1157                 goto err_free_mem_region;
1158         }
1159
1160         spin_lock_init(&host->dma_lock);
1161         init_timer(&host->dma_timer);
1162         spin_lock_init(&host->slot_lock);
1163         init_waitqueue_head(&host->slot_wq);
1164
1165         host->dma_timer.function = mmc_omap_dma_timer;
1166         host->dma_timer.data = (unsigned long) host;
1167
1168         host->pdata = pdata;
1169         host->dev = &pdev->dev;
1170         platform_set_drvdata(pdev, host);
1171
1172         host->id = pdev->id;
1173         host->mem_res = res;
1174         host->irq = irq;
1175
1176         host->use_dma = 1;
1177         host->dma_ch = -1;
1178
1179         host->irq = irq;
1180         host->phys_base = host->mem_res->start;
1181         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1182
1183         if (cpu_is_omap24xx()) {
1184                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1185                 if (IS_ERR(host->iclk))
1186                         goto err_free_mmc_host;
1187                 clk_enable(host->iclk);
1188         }
1189
1190         if (!cpu_is_omap24xx())
1191                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1192         else
1193                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1194
1195         if (IS_ERR(host->fclk)) {
1196                 ret = PTR_ERR(host->fclk);
1197                 goto err_free_iclk;
1198         }
1199
1200         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1201         if (ret)
1202                 goto err_free_fclk;
1203
1204         if (pdata->init != NULL) {
1205                 ret = pdata->init(&pdev->dev);
1206                 if (ret < 0)
1207                         goto err_free_irq;
1208         }
1209
1210         host->nr_slots = pdata->nr_slots;
1211         for (i = 0; i < pdata->nr_slots; i++) {
1212                 ret = mmc_omap_new_slot(host, i);
1213                 if (ret < 0) {
1214                         while (--i >= 0)
1215                                 mmc_omap_remove_slot(host->slots[i]);
1216
1217                         goto err_plat_cleanup;
1218                 }
1219         }
1220
1221         return 0;
1222
1223 err_plat_cleanup:
1224         if (pdata->cleanup)
1225                 pdata->cleanup(&pdev->dev);
1226 err_free_irq:
1227         free_irq(host->irq, host);
1228 err_free_fclk:
1229         clk_put(host->fclk);
1230 err_free_iclk:
1231         if (host->iclk != NULL) {
1232                 clk_disable(host->iclk);
1233                 clk_put(host->iclk);
1234         }
1235 err_free_mmc_host:
1236         kfree(host);
1237 err_free_mem_region:
1238         release_mem_region(res->start, res->end - res->start + 1);
1239         return ret;
1240 }
1241
1242 static int mmc_omap_remove(struct platform_device *pdev)
1243 {
1244         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1245         int i;
1246
1247         platform_set_drvdata(pdev, NULL);
1248
1249         BUG_ON(host == NULL);
1250
1251         for (i = 0; i < host->nr_slots; i++)
1252                 mmc_omap_remove_slot(host->slots[i]);
1253
1254         if (host->pdata->cleanup)
1255                 host->pdata->cleanup(&pdev->dev);
1256
1257         if (host->iclk && !IS_ERR(host->iclk))
1258                 clk_put(host->iclk);
1259         if (host->fclk && !IS_ERR(host->fclk))
1260                 clk_put(host->fclk);
1261
1262         release_mem_region(pdev->resource[0].start,
1263                            pdev->resource[0].end - pdev->resource[0].start + 1);
1264
1265         kfree(host);
1266
1267         return 0;
1268 }
1269
1270 #ifdef CONFIG_PM
1271 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1272 {
1273         int i, ret = 0;
1274         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1275
1276         if (host == NULL || host->suspended)
1277                 return 0;
1278
1279         for (i = 0; i < host->nr_slots; i++) {
1280                 struct mmc_omap_slot *slot;
1281
1282                 slot = host->slots[i];
1283                 ret = mmc_suspend_host(slot->mmc, mesg);
1284                 if (ret < 0) {
1285                         while (--i >= 0) {
1286                                 slot = host->slots[i];
1287                                 mmc_resume_host(slot->mmc);
1288                         }
1289                         return ret;
1290                 }
1291         }
1292         host->suspended = 1;
1293         return 0;
1294 }
1295
1296 static int mmc_omap_resume(struct platform_device *pdev)
1297 {
1298         int i, ret = 0;
1299         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1300
1301         if (host == NULL || !host->suspended)
1302                 return 0;
1303
1304         for (i = 0; i < host->nr_slots; i++) {
1305                 struct mmc_omap_slot *slot;
1306                 slot = host->slots[i];
1307                 ret = mmc_resume_host(slot->mmc);
1308                 if (ret < 0)
1309                         return ret;
1310
1311                 host->suspended = 0;
1312         }
1313         return 0;
1314 }
1315 #else
1316 #define mmc_omap_suspend        NULL
1317 #define mmc_omap_resume         NULL
1318 #endif
1319
1320 static struct platform_driver mmc_omap_driver = {
1321         .probe          = mmc_omap_probe,
1322         .remove         = mmc_omap_remove,
1323         .suspend        = mmc_omap_suspend,
1324         .resume         = mmc_omap_resume,
1325         .driver         = {
1326                 .name   = DRIVER_NAME,
1327         },
1328 };
1329
1330 static int __init mmc_omap_init(void)
1331 {
1332         return platform_driver_register(&mmc_omap_driver);
1333 }
1334
1335 static void __exit mmc_omap_exit(void)
1336 {
1337         platform_driver_unregister(&mmc_omap_driver);
1338 }
1339
1340 module_init(mmc_omap_init);
1341 module_exit(mmc_omap_exit);
1342
1343 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1344 MODULE_LICENSE("GPL");
1345 MODULE_ALIAS(DRIVER_NAME);
1346 MODULE_AUTHOR("Juha Yrjölä");