drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/clk.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/i2c/tps65010.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/mmc.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/dma.h>
  38 #include <asm/arch/mux.h>
  39 #include <asm/arch/fpga.h>
  40
  41 #define OMAP_MMC_REG_CMD        0x00
  42 #define OMAP_MMC_REG_ARGL       0x04
  43 #define OMAP_MMC_REG_ARGH       0x08
  44 #define OMAP_MMC_REG_CON        0x0c
  45 #define OMAP_MMC_REG_STAT       0x10
  46 #define OMAP_MMC_REG_IE         0x14
  47 #define OMAP_MMC_REG_CTO        0x18
  48 #define OMAP_MMC_REG_DTO        0x1c
  49 #define OMAP_MMC_REG_DATA       0x20
  50 #define OMAP_MMC_REG_BLEN       0x24
  51 #define OMAP_MMC_REG_NBLK       0x28
  52 #define OMAP_MMC_REG_BUF        0x2c
  53 #define OMAP_MMC_REG_SDIO       0x34
  54 #define OMAP_MMC_REG_REV        0x3c
  55 #define OMAP_MMC_REG_RSP0       0x40
  56 #define OMAP_MMC_REG_RSP1       0x44
  57 #define OMAP_MMC_REG_RSP2       0x48
  58 #define OMAP_MMC_REG_RSP3       0x4c
  59 #define OMAP_MMC_REG_RSP4       0x50
  60 #define OMAP_MMC_REG_RSP5       0x54
  61 #define OMAP_MMC_REG_RSP6       0x58
  62 #define OMAP_MMC_REG_RSP7       0x5c
  63 #define OMAP_MMC_REG_IOSR       0x60
  64 #define OMAP_MMC_REG_SYSC       0x64
  65 #define OMAP_MMC_REG_SYSS       0x68
  66
  67 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  68 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  69 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  70 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  71 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  72 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  73 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  74 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  75 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  76 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  77 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  78 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  79 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  80
  81 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  82 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  83
  84 /*
  85  * Command types
  86  */
  87 #define OMAP_MMC_CMDTYPE_BC     0
  88 #define OMAP_MMC_CMDTYPE_BCR    1
  89 #define OMAP_MMC_CMDTYPE_AC     2
  90 #define OMAP_MMC_CMDTYPE_ADTC   3
  91
  92
  93 #define DRIVER_NAME "mmci-omap"
  94
  95 /* Specifies how often in millisecs to poll for card status changes
  96  * when the cover switch is open */
  97 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  98
  99 struct mmc_omap_host;
 100
 101 struct mmc_omap_slot {
 102         int                     id;
 103         unsigned int            vdd;
 104         u16                     saved_con;
 105         u16                     bus_mode;
 106         unsigned int            fclk_freq;
 107         unsigned                powered:1;
 108
 109         struct work_struct      switch_work;
 110         struct timer_list       switch_timer;
 111         unsigned                cover_open;
 112
 113         struct mmc_request      *mrq;
 114         struct mmc_omap_host    *host;
 115         struct mmc_host         *mmc;
 116         struct omap_mmc_slot_data *pdata;
 117 };
 118
 119 struct mmc_omap_host {
 120         int                     initialized;
 121         int                     suspended;
 122         struct mmc_request *    mrq;
 123         struct mmc_command *    cmd;
 124         struct mmc_data *       data;
 125         struct mmc_host *       mmc;
 126         struct device *         dev;
 127         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 128         struct clk *            iclk;
 129         struct clk *            fclk;
 130         struct resource         *mem_res;
 131         void __iomem            *virt_base;
 132         unsigned int            phys_base;
 133         int                     irq;
 134         unsigned char           bus_mode;
 135         unsigned char           hw_bus_mode;
 136
 137         unsigned int            sg_len;
 138         int                     sg_idx;
 139         u16 *                   buffer;
 140         u32                     buffer_bytes_left;
 141         u32                     total_bytes_left;
 142
 143         unsigned                use_dma:1;
 144         unsigned                brs_received:1, dma_done:1;
 145         unsigned                dma_is_read:1;
 146         unsigned                dma_in_use:1;
 147         int                     dma_ch;
 148         spinlock_t              dma_lock;
 149         struct timer_list       dma_timer;
 150         unsigned                dma_len;
 151
 152         short                   power_pin;
 153
 154         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 155         struct mmc_omap_slot    *current_slot;
 156         spinlock_t              slot_lock;
 157         wait_queue_head_t       slot_wq;
 158         int                     nr_slots;
 159
 160         struct omap_mmc_platform_data *pdata;
 161 };
 162
 163 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 164 {
 165         struct mmc_omap_host *host = slot->host;
 166         unsigned long flags;
 167
 168         if (claimed)
 169                 goto no_claim;
 170         spin_lock_irqsave(&host->slot_lock, flags);
 171         while (host->mmc != NULL) {
 172                 spin_unlock_irqrestore(&host->slot_lock, flags);
 173                 wait_event(host->slot_wq, host->mmc == NULL);
 174                 spin_lock_irqsave(&host->slot_lock, flags);
 175         }
 176         host->mmc = slot->mmc;
 177         spin_unlock_irqrestore(&host->slot_lock, flags);
 178 no_claim:
 179         clk_enable(host->fclk);
 180         if (host->current_slot != slot) {
 181                 if (host->pdata->switch_slot != NULL)
 182                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 183                 host->current_slot = slot;
 184         }
 185
 186         /* Doing the dummy read here seems to work around some bug
 187          * at least in OMAP24xx silicon where the command would not
 188          * start after writing the CMD register. Sigh. */
 189         OMAP_MMC_READ(host, CON);
 190
 191         OMAP_MMC_WRITE(host, CON, slot->saved_con);
 192 }
 193
 194 static void mmc_omap_start_request(struct mmc_omap_host *host,
 195                                    struct mmc_request *req);
 196
 197 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
 198 {
 199         struct mmc_omap_host *host = slot->host;
 200         unsigned long flags;
 201         int i;
 202
 203         BUG_ON(slot == NULL || host->mmc == NULL);
 204         clk_disable(host->fclk);
 205
 206         spin_lock_irqsave(&host->slot_lock, flags);
 207         /* Check for any pending requests */
 208         for (i = 0; i < host->nr_slots; i++) {
 209                 struct mmc_omap_slot *new_slot;
 210                 struct mmc_request *rq;
 211
 212                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 213                         continue;
 214
 215                 new_slot = host->slots[i];
 216                 /* The current slot should not have a request in queue */
 217                 BUG_ON(new_slot == host->current_slot);
 218
 219                 host->mmc = new_slot->mmc;
 220                 spin_unlock_irqrestore(&host->slot_lock, flags);
 221                 mmc_omap_select_slot(new_slot, 1);
 222                 rq = new_slot->mrq;
 223                 new_slot->mrq = NULL;
 224                 mmc_omap_start_request(host, rq);
 225                 return;
 226         }
 227
 228         host->mmc = NULL;
 229         wake_up(&host->slot_wq);
 230         spin_unlock_irqrestore(&host->slot_lock, flags);
 231 }
 232
 233 static inline
 234 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 235 {
 236         return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
 237 }
 238
 239 static ssize_t
 240 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 241                            char *buf)
 242 {
 243         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 244         struct mmc_omap_slot *slot = mmc_priv(mmc);
 245
 246         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 247                        "closed");
 248 }
 249
 250 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 251
 252 static ssize_t
 253 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 254                         char *buf)
 255 {
 256         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 257         struct mmc_omap_slot *slot = mmc_priv(mmc);
 258
 259         return sprintf(buf, "%s\n", slot->pdata->name);
 260 }
 261
 262 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 263
 264 static void
 265 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 266 {
 267         u32 cmdreg;
 268         u32 resptype;
 269         u32 cmdtype;
 270
 271         host->cmd = cmd;
 272
 273         resptype = 0;
 274         cmdtype = 0;
 275
 276         /* Our hardware needs to know exact type */
 277         switch (mmc_resp_type(cmd)) {
 278         case MMC_RSP_NONE:
 279                 break;
 280         case MMC_RSP_R1:
 281         case MMC_RSP_R1B:
 282                 /* resp 1, 1b, 6, 7 */
 283                 resptype = 1;
 284                 break;
 285         case MMC_RSP_R2:
 286                 resptype = 2;
 287                 break;
 288         case MMC_RSP_R3:
 289                 resptype = 3;
 290                 break;
 291         default:
 292                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 293                 break;
 294         }
 295
 296         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 297                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 298         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 299                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 300         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 301                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 302         } else {
 303                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 304         }
 305
 306         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 307
 308         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 309                 cmdreg |= 1 << 6;
 310
 311         if (cmd->flags & MMC_RSP_BUSY)
 312                 cmdreg |= 1 << 11;
 313
 314         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 315                 cmdreg |= 1 << 15;
 316
 317         OMAP_MMC_WRITE(host, CTO, 200);
 318         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 319         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 320         OMAP_MMC_WRITE(host, IE,
 321                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 322                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 323                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 324                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 325                        OMAP_MMC_STAT_END_OF_DATA);
 326         OMAP_MMC_WRITE(host, CMD, cmdreg);
 327 }
 328
 329 static void
 330 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 331                      int abort)
 332 {
 333         enum dma_data_direction dma_data_dir;
 334
 335         BUG_ON(host->dma_ch < 0);
 336         if (data->error)
 337                 omap_stop_dma(host->dma_ch);
 338         /* Release DMA channel lazily */
 339         mod_timer(&host->dma_timer, jiffies + HZ);
 340         if (data->flags & MMC_DATA_WRITE)
 341                 dma_data_dir = DMA_TO_DEVICE;
 342         else
 343                 dma_data_dir = DMA_FROM_DEVICE;
 344         dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 345                      dma_data_dir);
 346 }
 347
 348 static void
 349 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 350 {
 351         if (host->dma_in_use)
 352                 mmc_omap_release_dma(host, data, data->error);
 353
 354         host->data = NULL;
 355         host->sg_len = 0;
 356
 357         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 358          * dozens of requests until the card finishes writing data.
 359          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 360          */
 361
 362         if (!data->stop) {
 363                 struct mmc_host *mmc;
 364
 365                 host->mrq = NULL;
 366                 mmc = host->mmc;
 367                 mmc_omap_release_slot(host->current_slot);
 368                 mmc_request_done(mmc, data->mrq);
 369                 return;
 370         }
 371
 372         mmc_omap_start_command(host, data->stop);
 373 }
 374
 375 static void
 376 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 377 {
 378         int loops;
 379         u16 ie;
 380
 381         if (host->dma_in_use)
 382                 mmc_omap_release_dma(host, data, 1);
 383
 384         host->data = NULL;
 385         host->sg_len = 0;
 386
 387         ie = OMAP_MMC_READ(host, IE);
 388         OMAP_MMC_WRITE(host, IE, 0);
 389         OMAP_MMC_WRITE(host, CMD, 1 << 7);
 390         loops = 0;
 391         while (!(OMAP_MMC_READ(host, STAT) & OMAP_MMC_STAT_END_OF_CMD)) {
 392                 udelay(1);
 393                 loops++;
 394                 if (loops == 100000)
 395                         break;
 396         }
 397         OMAP_MMC_WRITE(host, STAT, OMAP_MMC_STAT_END_OF_CMD);
 398         OMAP_MMC_WRITE(host, IE, ie);
 399 }
 400
 401 static void
 402 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 403 {
 404         unsigned long flags;
 405         int done;
 406
 407         if (!host->dma_in_use) {
 408                 mmc_omap_xfer_done(host, data);
 409                 return;
 410         }
 411         done = 0;
 412         spin_lock_irqsave(&host->dma_lock, flags);
 413         if (host->dma_done)
 414                 done = 1;
 415         else
 416                 host->brs_received = 1;
 417         spin_unlock_irqrestore(&host->dma_lock, flags);
 418         if (done)
 419                 mmc_omap_xfer_done(host, data);
 420 }
 421
 422 static void
 423 mmc_omap_dma_timer(unsigned long data)
 424 {
 425         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 426
 427         BUG_ON(host->dma_ch < 0);
 428         omap_free_dma(host->dma_ch);
 429         host->dma_ch = -1;
 430 }
 431
 432 static void
 433 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 434 {
 435         unsigned long flags;
 436         int done;
 437
 438         done = 0;
 439         spin_lock_irqsave(&host->dma_lock, flags);
 440         if (host->brs_received)
 441                 done = 1;
 442         else
 443                 host->dma_done = 1;
 444         spin_unlock_irqrestore(&host->dma_lock, flags);
 445         if (done)
 446                 mmc_omap_xfer_done(host, data);
 447 }
 448
 449 static void
 450 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 451 {
 452         host->cmd = NULL;
 453
 454         if (cmd->flags & MMC_RSP_PRESENT) {
 455                 if (cmd->flags & MMC_RSP_136) {
 456                         /* response type 2 */
 457                         cmd->resp[3] =
 458                                 OMAP_MMC_READ(host, RSP0) |
 459                                 (OMAP_MMC_READ(host, RSP1) << 16);
 460                         cmd->resp[2] =
 461                                 OMAP_MMC_READ(host, RSP2) |
 462                                 (OMAP_MMC_READ(host, RSP3) << 16);
 463                         cmd->resp[1] =
 464                                 OMAP_MMC_READ(host, RSP4) |
 465                                 (OMAP_MMC_READ(host, RSP5) << 16);
 466                         cmd->resp[0] =
 467                                 OMAP_MMC_READ(host, RSP6) |
 468                                 (OMAP_MMC_READ(host, RSP7) << 16);
 469                 } else {
 470                         /* response types 1, 1b, 3, 4, 5, 6 */
 471                         cmd->resp[0] =
 472                                 OMAP_MMC_READ(host, RSP6) |
 473                                 (OMAP_MMC_READ(host, RSP7) << 16);
 474                 }
 475         }
 476
 477         if (host->data == NULL || cmd->error) {
 478                 struct mmc_host *mmc;
 479
 480                 if (host->data != NULL)
 481                         mmc_omap_abort_xfer(host, host->data);
 482                 host->mrq = NULL;
 483                 mmc = host->mmc;
 484                 mmc_omap_release_slot(host->current_slot);
 485                 mmc_request_done(mmc, cmd->mrq);
 486         }
 487 }
 488
 489 /* PIO only */
 490 static void
 491 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 492 {
 493         struct scatterlist *sg;
 494
 495         sg = host->data->sg + host->sg_idx;
 496         host->buffer_bytes_left = sg->length;
 497         host->buffer = sg_virt(sg);
 498         if (host->buffer_bytes_left > host->total_bytes_left)
 499                 host->buffer_bytes_left = host->total_bytes_left;
 500 }
 501
 502 /* PIO only */
 503 static void
 504 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 505 {
 506         int n;
 507
 508         if (host->buffer_bytes_left == 0) {
 509                 host->sg_idx++;
 510                 BUG_ON(host->sg_idx == host->sg_len);
 511                 mmc_omap_sg_to_buf(host);
 512         }
 513         n = 64;
 514         if (n > host->buffer_bytes_left)
 515                 n = host->buffer_bytes_left;
 516         host->buffer_bytes_left -= n;
 517         host->total_bytes_left -= n;
 518         host->data->bytes_xfered += n;
 519
 520         if (write) {
 521                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 522         } else {
 523                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 524         }
 525 }
 526
 527 static inline void mmc_omap_report_irq(u16 status)
 528 {
 529         static const char *mmc_omap_status_bits[] = {
 530                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 531                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 532         };
 533         int i, c = 0;
 534
 535         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 536                 if (status & (1 << i)) {
 537                         if (c)
 538                                 printk(" ");
 539                         printk("%s", mmc_omap_status_bits[i]);
 540                         c++;
 541                 }
 542 }
 543
 544 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 545 {
 546         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 547         u16 status;
 548         int end_command;
 549         int end_transfer;
 550         int transfer_error;
 551
 552         if (host->cmd == NULL && host->data == NULL) {
 553                 status = OMAP_MMC_READ(host, STAT);
 554                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 555                 if (status != 0) {
 556                         OMAP_MMC_WRITE(host, STAT, status);
 557                         OMAP_MMC_WRITE(host, IE, 0);
 558                 }
 559                 return IRQ_HANDLED;
 560         }
 561
 562         end_command = 0;
 563         end_transfer = 0;
 564         transfer_error = 0;
 565
 566         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 567                 OMAP_MMC_WRITE(host, STAT, status);
 568 #ifdef CONFIG_MMC_DEBUG
 569                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 570                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 571                 mmc_omap_report_irq(status);
 572                 printk("\n");
 573 #endif
 574                 if (host->total_bytes_left) {
 575                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 576                             (status & OMAP_MMC_STAT_END_OF_DATA))
 577                                 mmc_omap_xfer_data(host, 0);
 578                         if (status & OMAP_MMC_STAT_A_EMPTY)
 579                                 mmc_omap_xfer_data(host, 1);
 580                 }
 581
 582                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 583                         end_transfer = 1;
 584                 }
 585
 586                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 587                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 588                         if (host->data) {
 589                                 host->data->error = -ETIMEDOUT;
 590                                 transfer_error = 1;
 591                         }
 592                 }
 593
 594                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 595                         if (host->data) {
 596                                 host->data->error = -EILSEQ;
 597                                 dev_dbg(mmc_dev(host->mmc),
 598                                          "data CRC error, bytes left %d\n",
 599                                         host->total_bytes_left);
 600                                 transfer_error = 1;
 601                         } else {
 602                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 603                         }
 604                 }
 605
 606                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 607                         /* Timeouts are routine with some commands */
 608                         if (host->cmd) {
 609                                 struct mmc_omap_slot *slot =
 610                                         host->current_slot;
 611                                 if (!mmc_omap_cover_is_open(slot))
 612                                         dev_err(mmc_dev(host->mmc),
 613                                                 "command timeout, CMD %d\n",
 614                                                 host->cmd->opcode);
 615                                 host->cmd->error = -ETIMEDOUT;
 616                                 end_command = 1;
 617                         }
 618                 }
 619
 620                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 621                         if (host->cmd) {
 622                                 dev_err(mmc_dev(host->mmc),
 623                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 624                                         host->cmd->opcode, host->cmd->arg);
 625                                 host->cmd->error = -EILSEQ;
 626                                 end_command = 1;
 627                         } else
 628                                 dev_err(mmc_dev(host->mmc),
 629                                         "command CRC error without cmd?\n");
 630                 }
 631
 632                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 633                         dev_dbg(mmc_dev(host->mmc),
 634                                 "ignoring card status error (CMD%d)\n",
 635                                 host->cmd->opcode);
 636                         end_command = 1;
 637                 }
 638
 639                 /*
 640                  * NOTE: On 1610 the END_OF_CMD may come too early when
 641                  * starting a write
 642                  */
 643                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 644                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 645                         end_command = 1;
 646                 }
 647         }
 648
 649         if (end_command) {
 650                 mmc_omap_cmd_done(host, host->cmd);
 651         }
 652         if (transfer_error)
 653                 mmc_omap_xfer_done(host, host->data);
 654         else if (end_transfer)
 655                 mmc_omap_end_of_data(host, host->data);
 656
 657         return IRQ_HANDLED;
 658 }
 659
 660 void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed)
 661 {
 662         struct mmc_omap_host *host = dev_get_drvdata(dev);
 663
 664         BUG_ON(slot >= host->nr_slots);
 665
 666         /* Other subsystems can call in here before we're initialised. */
 667         if (host->nr_slots == 0 || !host->slots[slot])
 668                 return;
 669
 670         schedule_work(&host->slots[slot]->switch_work);
 671 }
 672
 673 static void mmc_omap_switch_timer(unsigned long arg)
 674 {
 675         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 676
 677         schedule_work(&slot->switch_work);
 678 }
 679
 680 static void mmc_omap_cover_handler(struct work_struct *work)
 681 {
 682         struct mmc_omap_slot *slot = container_of(work, struct mmc_omap_slot,
 683                                                   switch_work);
 684         int cover_open;
 685
 686         cover_open = mmc_omap_cover_is_open(slot);
 687         if (cover_open != slot->cover_open) {
 688                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 689                 slot->cover_open = cover_open;
 690                 dev_info(mmc_dev(slot->mmc), "cover is now %s\n",
 691                          cover_open ? "open" : "closed");
 692         }
 693         mmc_detect_change(slot->mmc, slot->id);
 694 }
 695
 696 /* Prepare to transfer the next segment of a scatterlist */
 697 static void
 698 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 699 {
 700         int dma_ch = host->dma_ch;
 701         unsigned long data_addr;
 702         u16 buf, frame;
 703         u32 count;
 704         struct scatterlist *sg = &data->sg[host->sg_idx];
 705         int src_port = 0;
 706         int dst_port = 0;
 707         int sync_dev = 0;
 708
 709         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 710         frame = data->blksz;
 711         count = sg_dma_len(sg);
 712
 713         if ((data->blocks == 1) && (count > data->blksz))
 714                 count = frame;
 715
 716         host->dma_len = count;
 717
 718         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 719          * Use 16 or 32 word frames when the blocksize is at least that large.
 720          * Blocksize is usually 512 bytes; but not for some SD reads.
 721          */
 722         if (cpu_is_omap15xx() && frame > 32)
 723                 frame = 32;
 724         else if (frame > 64)
 725                 frame = 64;
 726         count /= frame;
 727         frame >>= 1;
 728
 729         if (!(data->flags & MMC_DATA_WRITE)) {
 730                 buf = 0x800f | ((frame - 1) << 8);
 731
 732                 if (cpu_class_is_omap1()) {
 733                         src_port = OMAP_DMA_PORT_TIPB;
 734                         dst_port = OMAP_DMA_PORT_EMIFF;
 735                 }
 736                 if (cpu_is_omap24xx())
 737                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 738
 739                 omap_set_dma_src_params(dma_ch, src_port,
 740                                         OMAP_DMA_AMODE_CONSTANT,
 741                                         data_addr, 0, 0);
 742                 omap_set_dma_dest_params(dma_ch, dst_port,
 743                                          OMAP_DMA_AMODE_POST_INC,
 744                                          sg_dma_address(sg), 0, 0);
 745                 omap_set_dma_dest_data_pack(dma_ch, 1);
 746                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 747         } else {
 748                 buf = 0x0f80 | ((frame - 1) << 0);
 749
 750                 if (cpu_class_is_omap1()) {
 751                         src_port = OMAP_DMA_PORT_EMIFF;
 752                         dst_port = OMAP_DMA_PORT_TIPB;
 753                 }
 754                 if (cpu_is_omap24xx())
 755                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 756
 757                 omap_set_dma_dest_params(dma_ch, dst_port,
 758                                          OMAP_DMA_AMODE_CONSTANT,
 759                                          data_addr, 0, 0);
 760                 omap_set_dma_src_params(dma_ch, src_port,
 761                                         OMAP_DMA_AMODE_POST_INC,
 762                                         sg_dma_address(sg), 0, 0);
 763                 omap_set_dma_src_data_pack(dma_ch, 1);
 764                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 765         }
 766
 767         /* Max limit for DMA frame count is 0xffff */
 768         BUG_ON(count > 0xffff);
 769
 770         OMAP_MMC_WRITE(host, BUF, buf);
 771         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 772                                      frame, count, OMAP_DMA_SYNC_FRAME,
 773                                      sync_dev, 0);
 774 }
 775
 776 /* A scatterlist segment completed */
 777 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 778 {
 779         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 780         struct mmc_data *mmcdat = host->data;
 781
 782         if (unlikely(host->dma_ch < 0)) {
 783                 dev_err(mmc_dev(host->mmc),
 784                         "DMA callback while DMA not enabled\n");
 785                 return;
 786         }
 787         /* FIXME: We really should do something to _handle_ the errors */
 788         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 789                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 790                 return;
 791         }
 792         if (ch_status & OMAP_DMA_DROP_IRQ) {
 793                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 794                 return;
 795         }
 796         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 797                 return;
 798         }
 799         mmcdat->bytes_xfered += host->dma_len;
 800         host->sg_idx++;
 801         if (host->sg_idx < host->sg_len) {
 802                 mmc_omap_prepare_dma(host, host->data);
 803                 omap_start_dma(host->dma_ch);
 804         } else
 805                 mmc_omap_dma_done(host, host->data);
 806 }
 807
 808 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 809 {
 810         const char *dev_name;
 811         int sync_dev, dma_ch, is_read, r;
 812
 813         is_read = !(data->flags & MMC_DATA_WRITE);
 814         del_timer_sync(&host->dma_timer);
 815         if (host->dma_ch >= 0) {
 816                 if (is_read == host->dma_is_read)
 817                         return 0;
 818                 omap_free_dma(host->dma_ch);
 819                 host->dma_ch = -1;
 820         }
 821
 822         if (is_read) {
 823                 if (host->id == 1) {
 824                         sync_dev = OMAP_DMA_MMC_RX;
 825                         dev_name = "MMC1 read";
 826                 } else {
 827                         sync_dev = OMAP_DMA_MMC2_RX;
 828                         dev_name = "MMC2 read";
 829                 }
 830         } else {
 831                 if (host->id == 1) {
 832                         sync_dev = OMAP_DMA_MMC_TX;
 833                         dev_name = "MMC1 write";
 834                 } else {
 835                         sync_dev = OMAP_DMA_MMC2_TX;
 836                         dev_name = "MMC2 write";
 837                 }
 838         }
 839         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 840                              host, &dma_ch);
 841         if (r != 0) {
 842                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 843                 return r;
 844         }
 845         host->dma_ch = dma_ch;
 846         host->dma_is_read = is_read;
 847
 848         return 0;
 849 }
 850
 851 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 852 {
 853         u16 reg;
 854
 855         reg = OMAP_MMC_READ(host, SDIO);
 856         reg &= ~(1 << 5);
 857         OMAP_MMC_WRITE(host, SDIO, reg);
 858         /* Set maximum timeout */
 859         OMAP_MMC_WRITE(host, CTO, 0xff);
 860 }
 861
 862 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 863 {
 864         unsigned int timeout, cycle_ns;
 865         u16 reg;
 866
 867         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
 868         timeout = req->data->timeout_ns / cycle_ns;
 869         timeout += req->data->timeout_clks;
 870
 871         /* Check if we need to use timeout multiplier register */
 872         reg = OMAP_MMC_READ(host, SDIO);
 873         if (timeout > 0xffff) {
 874                 reg |= (1 << 5);
 875                 timeout /= 1024;
 876         } else
 877                 reg &= ~(1 << 5);
 878         OMAP_MMC_WRITE(host, SDIO, reg);
 879         OMAP_MMC_WRITE(host, DTO, timeout);
 880 }
 881
 882 static void
 883 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 884 {
 885         struct mmc_data *data = req->data;
 886         int i, use_dma, block_size;
 887         unsigned sg_len;
 888
 889         host->data = data;
 890         if (data == NULL) {
 891                 OMAP_MMC_WRITE(host, BLEN, 0);
 892                 OMAP_MMC_WRITE(host, NBLK, 0);
 893                 OMAP_MMC_WRITE(host, BUF, 0);
 894                 host->dma_in_use = 0;
 895                 set_cmd_timeout(host, req);
 896                 return;
 897         }
 898
 899         block_size = data->blksz;
 900
 901         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 902         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 903         set_data_timeout(host, req);
 904
 905         /* cope with calling layer confusion; it issues "single
 906          * block" writes using multi-block scatterlists.
 907          */
 908         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 909
 910         /* Only do DMA for entire blocks */
 911         use_dma = host->use_dma;
 912         if (use_dma) {
 913                 for (i = 0; i < sg_len; i++) {
 914                         if ((data->sg[i].length % block_size) != 0) {
 915                                 use_dma = 0;
 916                                 break;
 917                         }
 918                 }
 919         }
 920
 921         host->sg_idx = 0;
 922         if (use_dma) {
 923                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 924                         enum dma_data_direction dma_data_dir;
 925
 926                         if (data->flags & MMC_DATA_WRITE)
 927                                 dma_data_dir = DMA_TO_DEVICE;
 928                         else
 929                                 dma_data_dir = DMA_FROM_DEVICE;
 930
 931                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 932                                                 sg_len, dma_data_dir);
 933                         host->total_bytes_left = 0;
 934                         mmc_omap_prepare_dma(host, req->data);
 935                         host->brs_received = 0;
 936                         host->dma_done = 0;
 937                         host->dma_in_use = 1;
 938                 } else
 939                         use_dma = 0;
 940         }
 941
 942         /* Revert to PIO? */
 943         if (!use_dma) {
 944                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 945                 host->total_bytes_left = data->blocks * block_size;
 946                 host->sg_len = sg_len;
 947                 mmc_omap_sg_to_buf(host);
 948                 host->dma_in_use = 0;
 949         }
 950 }
 951
 952 static void mmc_omap_start_request(struct mmc_omap_host *host,
 953                                    struct mmc_request *req)
 954 {
 955         BUG_ON(host->mrq != NULL);
 956
 957         host->mrq = req;
 958
 959         /* only touch fifo AFTER the controller readies it */
 960         mmc_omap_prepare_data(host, req);
 961         mmc_omap_start_command(host, req->cmd);
 962         if (host->dma_in_use)
 963                 omap_start_dma(host->dma_ch);
 964         BUG_ON(irqs_disabled());
 965 }
 966
 967 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 968 {
 969         struct mmc_omap_slot *slot = mmc_priv(mmc);
 970         struct mmc_omap_host *host = slot->host;
 971         unsigned long flags;
 972
 973         spin_lock_irqsave(&host->slot_lock, flags);
 974         if (host->mmc != NULL) {
 975                 BUG_ON(slot->mrq != NULL);
 976                 slot->mrq = req;
 977                 spin_unlock_irqrestore(&host->slot_lock, flags);
 978                 return;
 979         } else
 980                 host->mmc = mmc;
 981         spin_unlock_irqrestore(&host->slot_lock, flags);
 982         mmc_omap_select_slot(slot, 1);
 983         mmc_omap_start_request(host, req);
 984 }
 985
 986 static void innovator_fpga_socket_power(int on)
 987 {
 988 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 989         if (on) {
 990                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 991                      OMAP1510_FPGA_POWER);
 992         } else {
 993                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 994                      OMAP1510_FPGA_POWER);
 995         }
 996 #endif
 997 }
 998
 999 /*
1000  * Turn the socket power on/off. Innovator uses FPGA, most boards
1001  * probably use GPIO.
1002  */
1003 static void mmc_omap_power(struct mmc_omap_host *host, int on)
1004 {
1005         if (on) {
1006                 if (machine_is_omap_innovator())
1007                         innovator_fpga_socket_power(1);
1008                 else if (machine_is_omap_h2())
1009                         tps65010_set_gpio_out_value(GPIO3, HIGH);
1010                 else if (machine_is_omap_h3())
1011                         /* GPIO 4 of TPS65010 sends SD_EN signal */
1012                         tps65010_set_gpio_out_value(GPIO4, HIGH);
1013                 else if (cpu_is_omap24xx()) {
1014                         u16 reg = OMAP_MMC_READ(host, CON);
1015                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
1016                 } else
1017                         if (host->power_pin >= 0)
1018                                 omap_set_gpio_dataout(host->power_pin, 1);
1019         } else {
1020                 if (machine_is_omap_innovator())
1021                         innovator_fpga_socket_power(0);
1022                 else if (machine_is_omap_h2())
1023                         tps65010_set_gpio_out_value(GPIO3, LOW);
1024                 else if (machine_is_omap_h3())
1025                         tps65010_set_gpio_out_value(GPIO4, LOW);
1026                 else if (cpu_is_omap24xx()) {
1027                         u16 reg = OMAP_MMC_READ(host, CON);
1028                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
1029                 } else
1030                         if (host->power_pin >= 0)
1031                                 omap_set_gpio_dataout(host->power_pin, 0);
1032         }
1033 }
1034
1035 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1036 {
1037         struct mmc_omap_slot *slot = mmc_priv(mmc);
1038         struct mmc_omap_host *host = slot->host;
1039         int func_clk_rate = clk_get_rate(host->fclk);
1040         int dsor;
1041
1042         if (ios->clock == 0)
1043                 return 0;
1044
1045         dsor = func_clk_rate / ios->clock;
1046         if (dsor < 1)
1047                 dsor = 1;
1048
1049         if (func_clk_rate / dsor > ios->clock)
1050                 dsor++;
1051
1052         if (dsor > 250)
1053                 dsor = 250;
1054
1055         slot->fclk_freq = func_clk_rate / dsor;
1056
1057         if (ios->bus_width == MMC_BUS_WIDTH_4)
1058                 dsor |= 1 << 15;
1059
1060         return dsor;
1061 }
1062
1063 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1064 {
1065         struct mmc_omap_slot *slot = mmc_priv(mmc);
1066         struct mmc_omap_host *host = slot->host;
1067         int i, dsor;
1068
1069         dsor = mmc_omap_calc_divisor(mmc, ios);
1070         host->bus_mode = ios->bus_mode;
1071         host->hw_bus_mode = host->bus_mode;
1072
1073         switch (ios->power_mode) {
1074         case MMC_POWER_OFF:
1075                 mmc_omap_power(host, 0);
1076                 break;
1077         case MMC_POWER_UP:
1078                 /* Cannot touch dsor yet, just power up MMC */
1079                 mmc_omap_power(host, 1);
1080                 return;
1081         case MMC_POWER_ON:
1082                 dsor |= 1 << 11;
1083                 break;
1084         }
1085
1086         clk_enable(host->fclk);
1087
1088         /* On insanely high arm_per frequencies something sometimes
1089          * goes somehow out of sync, and the POW bit is not being set,
1090          * which results in the while loop below getting stuck.
1091          * Writing to the CON register twice seems to do the trick. */
1092         for (i = 0; i < 2; i++)
1093                 OMAP_MMC_WRITE(host, CON, dsor);
1094         if (ios->power_mode == MMC_POWER_ON) {
1095                 /* Send clock cycles, poll completion */
1096                 OMAP_MMC_WRITE(host, IE, 0);
1097                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1098                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1099                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1100                 OMAP_MMC_WRITE(host, STAT, 1);
1101         }
1102         clk_disable(host->fclk);
1103 }
1104
1105 static const struct mmc_host_ops mmc_omap_ops = {
1106         .request        = mmc_omap_request,
1107         .set_ios        = mmc_omap_set_ios,
1108 };
1109
1110 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1111 {
1112         struct mmc_omap_slot *slot = NULL;
1113         struct mmc_host *mmc;
1114         int r;
1115
1116         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1117         if (mmc == NULL)
1118                 return -ENOMEM;
1119
1120         slot = mmc_priv(mmc);
1121         slot->host = host;
1122         slot->mmc = mmc;
1123         slot->id = id;
1124         slot->pdata = &host->pdata->slots[id];
1125
1126         host->slots[id] = slot;
1127
1128         mmc->caps = MMC_CAP_MULTIWRITE;
1129         if (host->pdata->conf.wire4)
1130                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1131
1132         mmc->ops = &mmc_omap_ops;
1133         mmc->f_min = 400000;
1134
1135         if (cpu_class_is_omap2())
1136                 mmc->f_max = 48000000;
1137         else
1138                 mmc->f_max = 24000000;
1139         if (host->pdata->max_freq)
1140                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1141         mmc->ocr_avail = slot->pdata->ocr_mask;
1142
1143         /* Use scatterlist DMA to reduce per-transfer costs.
1144          * NOTE max_seg_size assumption that small blocks aren't
1145          * normally used (except e.g. for reading SD registers).
1146          */
1147         mmc->max_phys_segs = 32;
1148         mmc->max_hw_segs = 32;
1149         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1150         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1151         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1152         mmc->max_seg_size = mmc->max_req_size;
1153
1154         r = mmc_add_host(mmc);
1155         if (r < 0)
1156                 goto err_remove_host;
1157
1158         if (slot->pdata->name != NULL) {
1159                 r = device_create_file(&mmc->class_dev,
1160                                         &dev_attr_slot_name);
1161                 if (r < 0)
1162                         goto err_remove_host;
1163         }
1164
1165         if (slot->pdata->get_cover_state != NULL) {
1166                 r = device_create_file(&mmc->class_dev,
1167                                         &dev_attr_cover_switch);
1168                 if (r < 0)
1169                         goto err_remove_slot_name;
1170
1171                 INIT_WORK(&slot->switch_work, mmc_omap_cover_handler);
1172                 init_timer(&slot->switch_timer);
1173                 slot->switch_timer.function = mmc_omap_switch_timer;
1174                 slot->switch_timer.data = (unsigned long) slot;
1175                 schedule_work(&slot->switch_work);
1176         }
1177
1178         return 0;
1179
1180 err_remove_slot_name:
1181         if (slot->pdata->name != NULL)
1182                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1183 err_remove_host:
1184         mmc_remove_host(mmc);
1185         mmc_free_host(mmc);
1186         return r;
1187 }
1188
1189 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1190 {
1191         struct mmc_host *mmc = slot->mmc;
1192
1193         if (slot->pdata->name != NULL)
1194                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1195         if (slot->pdata->get_cover_state != NULL)
1196                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1197
1198         del_timer_sync(&slot->switch_timer);
1199         flush_scheduled_work();
1200
1201         mmc_remove_host(mmc);
1202         mmc_free_host(mmc);
1203 }
1204
1205 static int __init mmc_omap_probe(struct platform_device *pdev)
1206 {
1207         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1208         struct mmc_omap_host *host = NULL;
1209         struct resource *res;
1210         int i, ret = 0;
1211         int irq;
1212
1213         if (pdata == NULL) {
1214                 dev_err(&pdev->dev, "platform data missing\n");
1215                 return -ENXIO;
1216         }
1217         if (pdata->nr_slots == 0) {
1218                 dev_err(&pdev->dev, "no slots\n");
1219                 return -ENXIO;
1220         }
1221
1222         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1223         irq = platform_get_irq(pdev, 0);
1224         if (res == NULL || irq < 0)
1225                 return -ENXIO;
1226
1227         res = request_mem_region(res->start, res->end - res->start + 1,
1228                                  pdev->name);
1229         if (res == NULL)
1230                 return -EBUSY;
1231
1232         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1233         if (host == NULL) {
1234                 ret = -ENOMEM;
1235                 goto err_free_mem_region;
1236         }
1237
1238         spin_lock_init(&host->dma_lock);
1239         init_timer(&host->dma_timer);
1240         spin_lock_init(&host->slot_lock);
1241         init_waitqueue_head(&host->slot_wq);
1242
1243         host->dma_timer.function = mmc_omap_dma_timer;
1244         host->dma_timer.data = (unsigned long) host;
1245
1246         host->pdata = pdata;
1247         host->dev = &pdev->dev;
1248         platform_set_drvdata(pdev, host);
1249
1250         host->id = pdev->id;
1251         host->mem_res = res;
1252         host->irq = irq;
1253
1254         host->use_dma = 1;
1255         host->dma_ch = -1;
1256
1257         host->irq = irq;
1258         host->phys_base = host->mem_res->start;
1259         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1260
1261         if (cpu_is_omap24xx()) {
1262                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1263                 if (IS_ERR(host->iclk))
1264                         goto err_free_mmc_host;
1265                 clk_enable(host->iclk);
1266         }
1267
1268         if (!cpu_is_omap24xx())
1269                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1270         else
1271                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1272
1273         if (IS_ERR(host->fclk)) {
1274                 ret = PTR_ERR(host->fclk);
1275                 goto err_free_iclk;
1276         }
1277
1278         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1279         if (ret)
1280                 goto err_free_fclk;
1281
1282         if (pdata->init != NULL) {
1283                 ret = pdata->init(&pdev->dev);
1284                 if (ret < 0)
1285                         goto err_free_irq;
1286         }
1287
1288         host->nr_slots = pdata->nr_slots;
1289         for (i = 0; i < pdata->nr_slots; i++) {
1290                 ret = mmc_omap_new_slot(host, i);
1291                 if (ret < 0) {
1292                         while (--i >= 0)
1293                                 mmc_omap_remove_slot(host->slots[i]);
1294
1295                         goto err_plat_cleanup;
1296                 }
1297         }
1298
1299         return 0;
1300
1301 err_plat_cleanup:
1302         if (pdata->cleanup)
1303                 pdata->cleanup(&pdev->dev);
1304 err_free_irq:
1305         free_irq(host->irq, host);
1306 err_free_fclk:
1307         clk_put(host->fclk);
1308 err_free_iclk:
1309         if (host->iclk != NULL) {
1310                 clk_disable(host->iclk);
1311                 clk_put(host->iclk);
1312         }
1313 err_free_mmc_host:
1314         kfree(host);
1315 err_free_mem_region:
1316         release_mem_region(res->start, res->end - res->start + 1);
1317         return ret;
1318 }
1319
1320 static int mmc_omap_remove(struct platform_device *pdev)
1321 {
1322         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1323         int i;
1324
1325         platform_set_drvdata(pdev, NULL);
1326
1327         BUG_ON(host == NULL);
1328
1329         for (i = 0; i < host->nr_slots; i++)
1330                 mmc_omap_remove_slot(host->slots[i]);
1331
1332         if (host->pdata->cleanup)
1333                 host->pdata->cleanup(&pdev->dev);
1334
1335         if (host->iclk && !IS_ERR(host->iclk))
1336                 clk_put(host->iclk);
1337         if (host->fclk && !IS_ERR(host->fclk))
1338                 clk_put(host->fclk);
1339
1340         release_mem_region(pdev->resource[0].start,
1341                            pdev->resource[0].end - pdev->resource[0].start + 1);
1342
1343         kfree(host);
1344
1345         return 0;
1346 }
1347
1348 #ifdef CONFIG_PM
1349 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1350 {
1351         int i, ret = 0;
1352         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1353
1354         if (host == NULL || host->suspended)
1355                 return 0;
1356
1357         for (i = 0; i < host->nr_slots; i++) {
1358                 struct mmc_omap_slot *slot;
1359
1360                 slot = host->slots[i];
1361                 ret = mmc_suspend_host(slot->mmc, mesg);
1362                 if (ret < 0) {
1363                         while (--i >= 0) {
1364                                 slot = host->slots[i];
1365                                 mmc_resume_host(slot->mmc);
1366                         }
1367                         return ret;
1368                 }
1369         }
1370         host->suspended = 1;
1371         return 0;
1372 }
1373
1374 static int mmc_omap_resume(struct platform_device *pdev)
1375 {
1376         int i, ret = 0;
1377         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1378
1379         if (host == NULL || !host->suspended)
1380                 return 0;
1381
1382         for (i = 0; i < host->nr_slots; i++) {
1383                 struct mmc_omap_slot *slot;
1384                 slot = host->slots[i];
1385                 ret = mmc_resume_host(slot->mmc);
1386                 if (ret < 0)
1387                         return ret;
1388
1389                 host->suspended = 0;
1390         }
1391         return 0;
1392 }
1393 #else
1394 #define mmc_omap_suspend        NULL
1395 #define mmc_omap_resume         NULL
1396 #endif
1397
1398 static struct platform_driver mmc_omap_driver = {
1399         .probe          = mmc_omap_probe,
1400         .remove         = mmc_omap_remove,
1401         .suspend        = mmc_omap_suspend,
1402         .resume         = mmc_omap_resume,
1403         .driver         = {
1404                 .name   = DRIVER_NAME,
1405                 .owner  = THIS_MODULE,
1406         },
1407 };
1408
1409 static int __init mmc_omap_init(void)
1410 {
1411         return platform_driver_register(&mmc_omap_driver);
1412 }
1413
1414 static void __exit mmc_omap_exit(void)
1415 {
1416         platform_driver_unregister(&mmc_omap_driver);
1417 }
1418
1419 module_init(mmc_omap_init);
1420 module_exit(mmc_omap_exit);
1421
1422 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1423 MODULE_LICENSE("GPL");
1424 MODULE_ALIAS("platform:" DRIVER_NAME);
1425 MODULE_AUTHOR("Juha Yrjölä");